KR101412072B1 - Memory device for implementing hidden timing parameters management - Google Patents

Abstract

The present invention is directed to a memory device having hidden timing parameters. The memory device has a plurality of banks in which a plurality of memory cells are arranged, and each of the banks includes at least two or more sub-banks. In a sub-bank interleaving scheme in which sub-banks in one bank are operated one after another, successive operations between sub-banks are set to occur at a row active-to-low active time (tRRD) interval between the different banks . In the sub-bank interleaving scheme, the data writing time (tWR) to the memory cell is not included in the interval time interval of consecutive data writing operations between the sub-banks. The tWR time does not need to be met by the memory controller as a timing parameter specification, so the memory controller can be hidden without knowing it.

Description

[0001] The present invention relates to a memory device for managing hidden timing parameters,

The present invention relates to a memory device, and more particularly to a memory device that manages hidden timing parameters that can hide timing parameters to a memory controller.

The memory device operates in accordance with the definition of timing parameters such as the time to write data to the memory cell, the word line activation time, the precharge time, and the like. Due to the limitations of process shrink in semiconductor manufacturing, timing parameters are getting longer and longer. This causes a decrease in semiconductor yield. With the trend toward miniaturization of semiconductor processes, semiconductor yield reduction is expected to become more severe. Accordingly, there is a need for a method that can manage timing parameters in a memory system.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device that hides timing parameters to a memory controller to secure timing parameter margins.

A memory device according to an aspect of the present invention includes a plurality of banks in which a plurality of memory cells are arranged, each of the banks including at least two or more sub-banks, a sub- In the bank interleaved scheme, consecutive operations between subbanks are set to occur at a low active-to-low active time (tRRD) interval between the different banks.

According to embodiments of the present invention, sub-banks may be selectively accessed using one or more bits of row address signals addressing memory cells.

According to the embodiments of the present invention, the data write-in time tWR to the memory cell in the continuous data write operation between the sub-banks is set longer than the data write-in time to the memory cell in the continuous data write operation between the banks . The data write-in time (tWR) to the memory cell may not be included in the interval time interval of consecutive data write operations between the sub-banks.

In accordance with embodiments of the present invention, the bit line precharge time (tRP) of a memory cell in consecutive data write operations between subbanks is determined by a bit line precharge time Can be set longer than the aging time. The bit line precharge time (tRP) of the memory cell may not be included in the interval time interval of consecutive data write operations between subbanks.

In accordance with embodiments of the present invention, the time (tRCD) between the row active command and the column active command in consecutive data write operations between sub-banks is determined by the row active command and the column active Command may be set longer than the time between commands. The bit line precharge time (tRP) of the memory cell may not be included in the interval time interval of consecutive data write operations between subbanks.

According to embodiments of the present invention, the sub-banks may be arranged in the direction in which the word lines of the memory cells are arranged. The sub-banks may be arranged in the direction in which the bit lines of the memory cells are arranged. The sub-banks may be connected to data line sense blocks and data input / output lines that are independent of each other.

A memory device according to another aspect of the present invention includes a plurality of banks in which a plurality of memory cells are arranged, each bank including a plurality of subarrays, dividing the subarrays into at least two or more subarray groups, And abides by timing constraints between successive command combinations applied to the subarrays included in each of the subarray groups.

According to embodiments of the present invention, sub-array groups may be selectively accessed using one or more bits of row address signals addressing memory cells.

According to embodiments of the present invention, when one sub-array in a sub-array group is activated, the memory device may be deactivated because the sub-arrays adjacent to the activated sub-array belong to the keep away zone.

According to embodiments of the present invention, when a sub-array belonging to a keep away zone belongs to another sub-array group, the sub-array belonging to another sub-array group may be inactivated.

According to embodiments of the present invention, when a defective cell is generated in a sub-array in a sub-array group, the memory device may replace the defective cell with a corresponding sub-array in the corresponding sub-array group or redundancy cells in another sub-array .

According to embodiments of the present invention, the memory device may further include a storage unit for storing the size of the sub-array group indicating the number of sub-arrays included in each of the sub-array groups. The storage portion may be a non-volatile element composed of a fuse or an anti-fuse.

According to embodiments of the present invention, each of the sub-array groups may be connected to a data line sense block and data input / output lines that are independent of each other.

According to embodiments of the present invention, the timing constraints can be set to the time at which the column selection line of the sub-array operating on the previous instruction is turned off in the sub-arrays to which the sequential instructions are applied.

A memory system according to another aspect of the present invention includes a plurality of banks in which a plurality of memory cells are arranged, each of the banks including a memory device including at least two or more sub-banks, and a control unit for controlling the memory device do. In a sub-bank interleaving scheme in which sub-banks in one bank are operated one after another, the controller controls so that the continuous operation between the sub-banks is performed at a low active-to-low active time (tRRD) interval between the different banks .

According to embodiments of the present invention, the control unit is disposed in a memory module in which the memory device is mounted, and transmits a command signal and an address signal received from the memory controller to the memory device, And may be a buffer chip for monitoring whether or not to access the sub-banks in the bank.

According to embodiments of the present invention, the control unit converts a command signal and an address signal of the memory device into a command signal and an address signal in response to a read or write command requested from the host, and causes the command signal and the address signal to access the sub- Or a memory controller that monitors whether or not a memory card is used.

According to embodiments of the present invention, the control unit may not comply with the data write-in time (tWR) parameter specification to the memory cell in consecutive data write operations between the sub-banks.

According to embodiments of the present invention, the control unit may not comply with the bit line free-charge time (tRP) parameter specification of the memory cell in consecutive data write operations between sub-banks.

A memory system according to another aspect of the present invention includes a plurality of banks in which a plurality of memory cells are arranged, each of the banks including a plurality of subarrays, and the subarrays are divided into at least two or more subarray groups And a controller to control the memory device and comply with timing constraints between consecutive instruction combinations applied to the subarrays included in each of the subarray groups of the memory device.

According to embodiments of the present invention, the memory device may further include a storage unit for storing the size of the sub-array group indicating the number of sub-arrays included in each of the sub-array groups.

According to embodiments of the present invention, the control unit may further include a storage unit for storing the size of the sub-array group indicating the number of sub-arrays included in each of the sub-array groups.

According to embodiments of the present invention, the controller can calculate the row address bits that distinguish the server array group from the row address to be bounded between each server array, using the size of the sub-array group of the memory device.

According to embodiments of the present invention, when one of the subarrays in the subarray group of the memory device is activated, the controller may deactivate adjacent subarrays belonging to the keepaway zone of the activated subarray.

According to the embodiments of the present invention, when the sub-array belonging to the keep away zone belongs to another sub-array group, the control unit can deactivate the sub-array belonging to another sub-array group.

According to embodiments of the present invention, when a defective cell is generated in a sub-array in a sub-array group of a memory device, the defective cell can be replaced with a corresponding sub-array in the corresponding sub-array group or redundancy cells in another sub-array .

In the memory device of the present invention described above, in the sub-bank interleaving method, as the continuous data write operation becomes shorter in the tRRD time interval, the memory cell data writing time (tWR) can be made longer in each data write operation. Thus, it is possible to sufficiently secure the time required for data writing. This can compensate for the tWR parameter that is lengthened due to the miniaturization of the semiconductor process.

Also, the memory cell data write-in time tWR is not included in the interval time interval of consecutive data write operations of the sub-banks. The tWR time does not require the memory controller to adhere to the timing parameter specifications at consecutive data write operation timing of the sub-banks. In the sub-bank interleaving mode, the memory cell data writing time (tWR) can be hidden without knowing the memory controller. The hidden memory cell data writing time (tWR) does not affect data processing time and data throughput.

1 is a block diagram illustrating a first example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.
2 is a circuit diagram of the bank shown in Fig.
3A to 3D are diagrams for explaining the operation timing of the memory device of FIG.
4 is a block diagram illustrating a second example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.
5 is a block diagram illustrating a third example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.
Fig. 6 is a diagram for explaining the architecture of the first bank of Fig. 5 in detail.
Figure 7 is a diagram illustrating timing constraints for successive commands of different subarrays of Figure 6;
8 is a block diagram illustrating a first example of a memory system that may be used to implement one or more hidden timing parameter management method embodiments described herein.
9 is a block diagram illustrating a second example of a memory system that may be used to implement one or more hidden timing parameter management method embodiments described herein.
10 is a diagram for explaining the timing parameter specification between the memory controller and the memory device of FIG.
11 is a diagram illustrating a semiconductor memory device implementing one or more hidden timing parameter management method embodiments described herein.
FIG. 12 is a diagram showing an embodiment of a memory system to which the semiconductor memory device of FIG. 11 is applied.
Figure 13 is a block diagram illustrating a computing system with a memory system in accordance with one embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

In a semiconductor memory device, timing parameters include a row cycle time (tRC), a ras to / CAS delay (tRCD), a write recovery time (tWR) Timing parameters such as time to collapse (tRP), and low active-to-low active delay (tRRD).

The tRC parameter indicates the time between the active command and the next active command. The tRCD parameter indicates the time between the / RAS signal application and the / CAS signal application, and means the time between the row active command and the column active command. The tWR parameter indicates the time to write data to the memory cell after word line enable. The tRP parameter indicates the time to precharge the bit line to prepare the next active instruction after the tWR time. The tRRD parameter indicates the time between the low active command and the low active command, which means the low active-to-low active time between different banks.

The longer the tWR time, the greater the data write time in the memory cell. Thus, the memory device can sufficiently secure the time margin required for data writing.

On the other hand, as the semiconductor process is miniaturized, the yield of semiconductor is decreasing due to the problem that the timing parameters are getting longer. Of the lengthening timing parameters, tWR is a major factor in reducing semiconductor yield.

If we can hide the tWR parameters that are lengthened as the semiconductor process gets smaller, the semiconductor process will be easier and the yield will increase. Thus, the semiconductor manufacturing cost of the memory device can be reduced. The memory system including such a memory device can be supplied with a low-cost memory device having a high degree of integration, even if the process scaling limit is reached.

1 is a block diagram illustrating a first example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.

1, a memory device 100 includes a plurality of banks A BANK - H BANK 110, 120, 130, 140, 150, 160, 170, 180 in which a plurality of memory cells are arranged in rows and columns, . Each of the plurality of banks 110 to 180 may include a plurality of word lines WLs, a plurality of bit lines BLs, and a plurality of bit lines BLs between the word lines WLs and the bit lines BLs, And a plurality of memory cells MCs arranged at the intersections of the memory cells MCs. Each memory cell MC has a DRAM cell structure. The word lines WLs to which the memory cells MCs are connected are defined as rows of the banks 110 to 180 and the bit lines BLs to which the memory cells MCs are connected are connected to the banks 110 to 180 ) Columns.

In this embodiment, an example in which the memory device 100 is composed of eight banks A BANK to H BANK is described. The memory device 100 may include a variable number of banks in addition to the eight banks A BANK to H BANK.

Each of the plurality of banks 110 to 180 includes a first sub-bank 111, a second sub-bank 112, a first row decoder 113, a second row decoder 114, a first column decoder 115 ), And a second column decoder (116). The first row decoder 113 and the second row decoder 114 may receive the bank addresses BAs and the row addresses RAs. The first column decoder 115 and the second column decoder 116 may receive column addresses (not shown). One bank of the plurality of banks 110 to 180 is selected in accordance with the bank addresses BAs and the memory cells in the selected bank in accordance with the row addresses RAs and the column addresses (not shown) have.

The A bank 110 may be divided into a first sub-bank 111 and a second sub-bank 112. It can be seen that the first sub-bank 111 and the second sub-bank 112 are arranged in the direction in which the word lines WLs of the memory cells MCs are arranged, that is, in the row direction. The first sub-bank 111 may be connected to the first row decoder 113 and the first column decoder 115. The memory cells of the first sub-bank 111 may be addressed by the first row decoder 113 and the first column decoder 115. [ The second sub-bank 112 may be coupled to the second row decoder 114 and the second column decoder 116. The memory cells of the second sub-bank 112 may be addressed by the second row decoder 114 and the second column decoder 116.

The first sub-bank 111 and the second sub-bank 112 are selected by any one of the row address signals RAs provided to the first row decoder 113 and the second row decoder 114 . For example, the first sub-bank 111 or the second sub-bank 112 can be selected by the MSB signal (RA _MSB ) of the row address signal. The first sub-bank 111 may be selected by the / RA _MSB signal and the second sub-bank 112 may be selected by the RA _MSB .

The first sub-bank 111 and the second sub-bank 112 are connected to the respective data line sense amplifier blocks 117 and 118 and are connected to the data input / output lines I / O _AS1 and I / O _AS2 , Can be connected. The data read from the first sub-bank 111 may be output through the first data line sense amplifier block 117 and the first data input / output lines I / O _AS1 . The data read from the second sub-bank 112 may be output through the second data line sense amplifier 118 and the second data input / output lines I / O _AS2 .

Each of the B to H banks 120 to 180 may be divided into a first sub-bank and a second sub-bank in the same manner as the A-bank 110. [ The first sub-bank of each of the banks may be connected to the first row decoder, the first column decoder, the first data line sense amplifier block, and the first data input / output lines. The second sub-bank and the second sub-bank of each of the banks may be connected to the second row decoder, the second column decoder, the second data line sense amplifier block, and the second data input / output lines. Although the example in which the A bank to the H banks 110 to 180 are composed of two sub-banks is described in the present embodiment, the sub-banks may be composed of various numbers of sub-banks other than two. The various numbers of sub-banks may be connected to independent data line sense amplifier blocks and data input / output lines.

3A to 3D are diagrams for explaining the operation timing of the memory device 100 of FIG. FIG. 3A is a view for explaining a bank interleaving method, and FIGS. 3B to 3D are views for explaining a sub-bank interleaving method.

Referring to FIG. 3A, the bank interleaving scheme shows the timing of interleaving the A to H banks 110 to 180, that is, sequentially operating one by one. The bank interleaving mode may be a bank operation of any one of the remaining banks 120-180 other than the A bank 110 after the operation of the A bank 110, for example. Alternatively, the bank interleaving method may be performed by operation of the A bank 110 after operation of the A bank 110. [ The bank interleaving scheme of FIG. 3A is described by continuous A bank 110 operation.

The first active command ACT0 for the A bank 110 is applied and the first word line WL0 is enabled after tRCD time. The first word line WL0 is connected to the memory cells selected in the A bank 110. [ A data write operation is performed with selected memory cells connected to the first word line WL0. The memory cell data write operation of the A bank 110 is performed for the time tWR. After the time tWR, the bit lines of the memory cells in the A bank are precharged by the first precharge command PRE0. The bit line free-charge operation of the A bank 110 occurs during the tRP time. It can be seen that the first write operation for the A bank 110 occurs for tRCD + tWR + tRP time.

Thereafter, the second active command ACT1 for the A bank 110 is applied, and the second word line WL1 is enabled after tRCD time. The second word line WL1 is connected to the memory cells selected in the A bank 110. [ A data write operation is performed to the selected memory cells connected to the second word line WL1. The memory cell data write operation of the A bank 110 is performed for the time tWR. After the time tWR, the bit lines of the memory cells in the A bank 110 are precharged by the second precharge command PRE1. The bit line free-charge operation of the A bank 110 occurs during the tRP time. It can be seen that the second write operation for the A bank 110 occurs for tRCD + tWR + tRP time.

In the bank interleaving scheme, the first write operation and the second write operation for the A bank 110 are performed at a time interval of tRC + tWR + tRP. The tRC time is, for example, at least 50 ns.

Referring to FIG. 3B, the sub-bank interleaving scheme interleaves the sub-banks 111 and 112 in one of the A to H banks 110 to 180, Lt; / RTI > The sub-bank interleaving scheme is described, for example, as the operation for the sub-banks 111 and 112 of the A bank 110. [ Assume that the first active command ACT0 is an active command for the first sub bank 111 and the second active command ACT1 is an active command for the second sub bank 112. [

The first active command ACT0 for the first sub-bank 111 is applied and the first word line WL0 is enabled after tRCD time. The first word line WL0 is connected to the memory cells selected in the first sub-bank 111. [ A data write operation is performed with selected memory cells connected to the first word line WL0. The memory cell data write operation of the first sub-bank 111 is performed for a time tWR '. After the time tWR ', the bit lines of the memory cells in the first sub-bank 111 are precharged by the first precharge command PRE0. The bit line free-charge operation of the first sub-bank 111 occurs during the tRP time. Thereafter, the first active command ACT0 for the first sub-bank 111 is applied again, the first word line WL0 is enabled, the memory cell data write operation is performed, and the bit line pre- An operation can be performed.

The second active command ACT1 for the second sub-bank 112 is applied and the second word line WL1 is enabled after tRCD time. The second word line WL1 is connected to the memory cells selected in the second sub-bank 112. [ A data write operation is performed to the selected memory cells connected to the second word line WL1. The memory cell data write operation of the second sub-bank 112 is performed for a time tWR '. After the time tWR ', the bit lines of the memory cells in the second sub-bank 112 are precharged by the second precharge command PRE1. The bit line free-charge operation of the second sub-bank 112 occurs during the tRP time. Thereafter, the second active command ACT1 for the second sub-bank 112 is again applied, the second word line WL1 is enabled, the memory cell data write operation is performed, and the bit line pre- An operation can be performed.

In the sub-bank interleaving scheme, the first active command ACT0 for the first sub-bank 111 and the second active command ACT1 for the second sub-bank 112 are low active-to- - It can be applied in tRRD time interval which is low active time. The tRRD time is, for example, at least about 6 ns.

Since the bank interleaving scheme can not enable two word lines in one A bank 110, consecutive data write operations to the A bank 110 can only write data at tRC time intervals. On the other hand, in the sub-bank interleaving method, the data writing operation for the sub-banks 111 and 112 in the A bank 110 can write data at the time intervals of tRRD. The tRRD time is significantly shorter than the tRC time. As a result, the sub-bank interleaving scheme can have a longer memory cell data write-in time tWR 'in each data write operation as the continuous data write operation becomes shorter in the tRRD time interval.

In the sub-bank interleaving method, since the memory cell data writing time tWR 'is long, the time required for data writing can be sufficiently secured. This can compensate for the tWR parameter that is lengthened due to the miniaturization of the semiconductor process.

Also, the memory cell data write-in time tWR 'is not included in the interval time interval of consecutive data write operations of the sub-banks. The time tWR 'does not require the host, for example the memory controller, to comply with the timing parameter provisions in the successive data write operation timing of the sub-banks. That is, the memory cell data write time tWR 'in the sub-bank interleaving mode can be hidden without the memory controller knowing. The hidden memory cell data write time tWR 'does not affect data processing time and data throughput.

In this embodiment, an example in which the time tWR 'is sufficiently secured in the sub-bank interleaving method is described. The sub-bank interleaving scheme can secure a sufficiently long tRCD or tRP time instead of the tWR 'time.

FIG. 3C shows a case where the tRCD 'time is ensured in a continuous data write operation of the sub-banks, and FIG. 3D shows a case in which the tRP' time is secured. The tRCD 'and tRP' times are not included in the interval time interval of consecutive data write operations of the sub-banks. The tRCD 'and tRP' times can be hidden without the memory controller knowing the timing of consecutive data write operations of the sub-banks. Hidden tRCD 'or tRP' times do not affect data processing time and data throughput.

4 is a block diagram illustrating a second example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.

Referring to FIG. 4, the memory device 400 differs from the memory device 100 of FIG. 1 in that the A bank 110 ^I is composed of four sub-banks. The A bank 110 ^I may be divided into first to fourth sub-banks 411, 412, 413, and 414.

The first sub-bank 411 may be connected to the first row decoder 421, the first column decoder 431, the first data line sense amplifier block 441 and the first data input / output lines I / O _AS1 . have. The memory cells of the first sub-bank 411 may be addressed by the first row decoder 421 and the first column decoder 431. [ The data read from the first sub-bank 411 may be output through the first data line sense amplifier block 441 and the first data input / output lines I / O _AS1 .

The second sub-bank 412 may be coupled to the second row decoder 422, the second column decoder 432, the second data line sense amplifier block 442 and the second data input / output lines I / O _AS2 . have. The memory cells of the second sub-bank 412 may be addressed by the second row decoder 422 and the second column decoder 432. The data read out from the second sub-bank 412 can be output through the second data line sense amplifier block 442 and the second data input / output lines I / O _AS2 .

The third sub-bank 413 may be connected to the third row decoder 423, the third column decoder 433, the third data line sense amplifier block 443 and the third data input / output lines I / O _AS3 . have. The memory cells of the third sub-bank 413 may be addressed by the third row decoder 423 and the third column decoder 433. [ The data read out from the third sub-bank 413 can be output through the third data line sense amplifier block 443 and the third data input / output lines I / O _AS3 .

The fourth sub-bank 414 may be coupled to the fourth row decoder 424, the fourth column decoder 434, the fourth data line sense amplifier block 444 and the fourth data input / output lines I / O _AS4 . have. The memory cells of the fourth sub-bank 414 may be addressed by the fourth row decoder 424 and the fourth column decoder 434. [ The data read out from the fourth sub-bank 414 may be output through the fourth data line sense amplifier block 444 and the fourth data input / output lines I / O _AS4 .

The first to fourth sub-banks 411, 412, 413 and 114 may be selected by two of the row address signals RAs provided to the first to fourth row decoders 421 to 424 have. For example, when one of the first to fourth sub-banks 411, 412, 413 and 114 is selected by the MSB signal (RA _MSB ) and the MSB-1 signal (RA _{MSB -1} ) .

Each of the B to H banks 120 to 180 of FIG. 1 is also divided into four sub-banks, like the A-bank 110 ^I of FIG. 4, and the first to fourth sub- 1 can be selected by the MSB signal (RA _MSB ) and the MSB-1 signal (RA _{MSB -1} ) of the row address signal provided to the four row decoders. The first sub-bank of each of the banks may be connected to the first row decoder, the first column decoder, the first data line sense amplifier block, and the first data input / output lines. The second sub-bank of each of the banks may be connected to the second row decoder, the second column decoder, the second data line sense amplifier block, and the second data input / output lines. The third sub-bank of each of the banks may be connected to the third row decoder, the third column decoder, the third data line sense amplifier block, and the third data input / output lines. The fourth sub-bank of each of the banks may be connected to the fourth row decoder, the fourth column decoder, the fourth data line sense amplifier block, and the fourth data input / output lines.

In the present embodiment, although the memory device 400 is composed of eight banks A BANK to H BANK, and the A bank to the H bank are composed of four sub-banks, And may be composed of various numbers of sub-banks. The various numbers of sub-banks may be connected to independent data line sense amplifier blocks and data input / output lines.

5 is a block diagram illustrating a third example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.

Referring to FIG. 5, the memory device 500 includes a plurality of memory banks BANK0-BANK7 having a stack bank architecture. Memory banks (BANK0 - BANK7) may be separately arranged for noise dispersion. The memory banks BANK0 to BANK7 may be divided into four quadrants 50A, 50B, 50C and 50D based on pads arranged in the center of the memory device 500. [

The first bank BANK0 may be divided into a first quadrant 50A and a fourth quadrant 50D and the second bank BANK1 may be divided into a second quadrant 50B and a third quadrant 50C. have. The remaining even-numbered banks BANK2, BANK4, and BANK6 may be divided into a first quadrant 50A and a fourth quadrant 50D. The remaining odd-numbered banks BANK3, BANK5, and BANK7 may be divided into a second quadrant 50B and a third quadrant 50C.

The first bank BANK0 may be comprised of a first memory cell array block 510a disposed in the first quadrant 50A and a second memory cell array block 510b disposed in the fourth quadrant 50D. The second bank BANK1 may be comprised of a first memory cell array block 520a disposed in the second quadrant 50B and a second memory cell array block 520b disposed in the third quadrant 50C. The third bank BANK2 may be comprised of a first memory cell array block 530a disposed in the first quadrant 50A and a second memory cell array block 530b disposed in the fourth quadrant 50D.

Each of the remaining even-numbered banks BANK4 and BANK6 may be constituted by a first memory cell array block disposed in the first quadrant 50A and a second memory cell array block disposed in the fourth quadrant 50D. Each of the remaining odd-numbered banks BANK3, BANK5, and BANK7 may be composed of a first memory cell array block disposed in the second quadrant 50B and a second memory cell array block disposed in the third quadrant 50C .

Referring to the first quadrant 50A of the memory device 500, the first memory cell array block 510a of the first bank BANK0 and the first memory cell array block 530a of the third bank BANK2 form a stack Stack bank structure. The first memory cell array block 510a of the first bank BANK0 may be divided into two array groups 511 and 512. [ The first memory cell array block 530a of the third bank BANK2 may also be divided into two subarray groups 531 and 532. [ The subarray groups 511 and 512 of the first bank BANK0 and the subarray groups 531 and 532 of the third bank BANK2 are arranged in the direction in which the bit lines of the memory cells are arranged, Can be seen.

The first memory cell array blocks 510a and 530a of the first bank BANK0 and the third bank BANK3 are divided by a row decoder 513 in between. The divided first memory cell array blocks 510a and 530a may be connected to the row decoder 513 and the first and second column decoders 515 and 516. [ The memory cells of the divided first memory cell array blocks 510a and 530a may be addressed by the row decoder 513 and the first and second column decoders 515 and 516. [

The row decoder 513 can receive the bank addresses BAs and the row addresses RAs. The first and second column decoders 515 and 516 may receive column addresses (not shown). One bank of the first and third banks BANK0 and BANK3 is selected according to the bank addresses BAs and the sub memory cells in the bank selected in accordance with the row addresses RAs and the column addresses The memory cells of the array blocks 511, 512, 531 and 532 can be addressed.

The first subarray group 511 and the second subarray group 512 of the first bank BANK0 may be selected by any one of the row address signals RAs provided to the row decoder 513 have. For example, the first sub-array group 511 or the second sub-array group 512 can be selected by the MSB signal (RA _MSB ) of the row address signal. The first sub-array group 511 may be selected by the / RA _MSB signal and the second sub-array group 512 may be selected by the RA _MSB .

Like the first and third banks BANK0 and BANK2, the memory cell array blocks in which the fifth and seventh banks BANK4 and BANK6 are divided into two subarray groups are stacked. The subarray groups of the fifth and seventh banks BANK4 and BANK6 may be selected by the MSB signal (RA _MSB ) of the row address signal provided to the row decoder 513.

Memory cell array blocks in which the memory banks BANK0 to BANK7 of the other quadrants 50B, 50C and 50D are divided into two subarray groups are stacked. Memory banks (BANK0 - BANK7) within the sub-array group may be selected by the row decoder corresponding quadrant MSB signal (RA _MSB) of the row address signal provided to the arrangement (50B, 50C, 50D).

In the present embodiment, the memory banks BANK0 to BANK7 are formed of two sub-array groups, but the sub-array groups may have a different number of sub-array groups than two.

Fig. 6 is a diagram for explaining the architecture of the first bank of Fig. 5 in detail.

Referring to FIG. 6, the first sub-array group 511 and the second sub-array group 512 may include a plurality of sub-arrays 611-618. The subarrays 611-618 in the first subarray group 511 may be designed to share data input / output lines (not shown) and data line sense amplifier blocks (not shown). Similarly, the subarrays in the second subarray group 512 may be designed to share a data line sense amplifier block (not shown) with data input / output lines (not shown).

The subarrays 614 in the first subarray group 511 may be connected to the bitline sense amplifier blocks 621 and 622 disposed above and below the subarray 614. [ The bit line sense amplifier block 621 may be coupled to the sub-array 613. The bit line sense amplifier block 621 may be shared by the sub-arrays 613 and 614. The bit line sense amplifier block 622 may be coupled to the sub-array 615. The bit line sense amplifier block 622 may be shared by the subarrays 614 and 615.

In one sub-array 614 in the first sub-array group 511, when one word line WL1 is enabled, the data of the memory cells connected to the word line WL1 are applied to the bit line sense amplifier blocks 621 and 622 To be sensed and amplified. In this case, the sub-array 613 connected to the bit line sense amplifier block 621 and the sub-array 615 connected to the bit line sense amplifier block 622 must be inactivated. That is, the sub-arrays 613 and 615 adjacent to the activated sub-array 614 must be deactivated. The deactivated sub-arrays 613 and 615 may be referred to as a keep away zone.

The first sub-array group 511 may activate a sub-array of areas outside the keep away zone of the activated sub-array 614, e.g., the sub-array 612. When the sub-array 612 is activated, the sub-arrays 611 and 613 adjacent to the sub-array 612 belong to the keep away zone and must be deactivated.

On the other hand, the sub-array 618 in the first sub-array group 511 can be activated. The sub-array 618 of the first sub-array group 511 is adjacent to the second sub-array group 512. When the sub array 618 of the first sub array group 511 is activated, the sub array 617 of the first sub array group 511 and the sub array 631 of the second sub array group 512, It belongs to zone and should be disabled.

Defective cells may occur in the subarrays 611 - 618 in the first subarray group 511. Each of the sub-arrays 611-618 may include redundancy cells for relieving defective cells. Each of the subarrays 611 to 618 can replace the defective cell generated in the corresponding subarray with the redundant cell of the corresponding subarray. In addition, the sub-arrays 611-618 can replace the defective cells generated in the corresponding sub-array with the redundant cells of the other sub-array. The other sub-arrays to be replaced may be restricted to belong to the first sub-array group 511. [ That is, the first sub-array group 511 may be set to have repair flexibility within the first sub-array group 511. [

The second sub-array group 512 may also be set to have relief flexibility in the second sub-array group 512. [ Each of the sub-arrays in the second sub-array group 512 may include redundancy cells for relieving defective cells. The defective cells generated in each of the subarrays in the second subarray group 512 can be replaced with redundant cells of the corresponding subarray. The defective cells occurring in each of the subarrays in the second subarray group 512 can be replaced with redundant cells of the other subarrays.

The size of the sub-array group can be reduced by reducing the number of the sub-arrays 611-618 included in the first and second sub-array groups 511 and 512. [ Accordingly, the number of sub-array groups increases and the parallelism efficiency can be increased. On the other hand, the number of sub-arrays in the sub-array group can be reduced, thereby reducing the relief flexibility. It can be seen that there is a trade-off between sub-array size granularity and relief flexibility.

The size of the sub-array group may be stored in a storage unit (not shown) in the memory device 500. The storage unit may include a non-volatile element composed of a fuse or an anti-fuse. The size of the sub-array group may be set to a sufficiently large number including all sub-arrays. In addition, the size of the sub-array group may be specified according to the purpose of the user.

The first and second sub-array groups 511 and 512 may be connected to as many row decoders or latch type word line drivers as are simultaneously enabled to simultaneously enable a plurality of word lines. Since a plurality of row decoders can be a large burden in terms of chip area, a latch type word line driver can be employed.

Each of the first and second subarray groups 511 and 512 includes a plurality of subarrays and the subarrays are designed to share data line sense amplifier blocks (not shown) with data input / output lines (not shown) . An operation command can be continuously applied to different subarrays. Because sub-arrays share data input / output lines, there may be timing constraints on instruction combinations applied to different sub-arrays.

Figure 7 is a diagram illustrating timing constraints for successive commands of different subarrays of Figure 6;

7, one sub-array among the plurality of sub-arrays 611-618 in the first sub-array group 511 of FIG. 6 is referred to as a sub-array A, and the other sub-array is referred to as a sub-array B . There is no timing restriction between the active instruction ACT of the subarray A and the active instruction ACT of the subarray B as shown in the timing between the current command of the subarray A and the next instruction of the subarray B. This is because the active command ACT belongs to a row command and therefore no collision occurs on the path of the data input / output line shared by the subarray A and the subarray B.

There is no timing restriction between the active command (ACT) of subarray A and the precharge command (PRE) of subarray B. There is also no timing restriction between the active command ACT of subarray A and the refresh command REF of subarray B. This is because, as in the active command ACT, the free-charge command PRE and the refresh command REF also belong to the low-order command, so that collision of the data input / output line does not occur.

The write / read command WR / RD of the subarray B after the active command ACT of the subarray A is invalid. Because the column select line is on during the write or read command and the path to the data input / output line is formed by the column select line, the two word lines in different subarrays in the subarray group sharing the data input / Because the lines can not be enabled at the same time. In other words, in order to perform the write / read command (WR / RD) in the sub-array B, the active command would have been performed before, and the write / read operation is not effective because the word line is written / read in two enabled states at the same time.

There is no timing restriction between the active command (ACT), the precharge command (PRE), or the refresh command (REF) of subarray B after the precharge command (PRE) of subarray A.

A precharge-to-write time (tPRE2WR) interval is required between the write command (WR) of subarray B after the precharge command (PRE) of subarray A. Then, a free charge-to-read time tPRE2RD interval is required between the read command RD of the subarray B after the precharge command PRE of the subarray A. When one of the corresponding word lines is turned off by the precharge instruction PRE in the subarray A, one word line enable for the write or read operation in the subarray B becomes possible. The tPRE2WR time and tPRE2RD time can be seen as the time it takes for the word line of subarray A to turn off.

There is no timing restriction between the active instruction ACT of the subarray B, the precharge instruction PRE or the refresh instruction REF after the refresh instruction REF of the subarray A.

The refresh-to-write time (tREF2WR) interval is required between the refresh command (REF) of subarray A and the write command WR of subarray B. The refresh-to-read time tREF2RD interval is required between the read command RD of the subarray B after the refresh command REF of the subarray A. If one word line is turned off after refreshing if another word line is activated by the write / read command of the sub array B while the one word line is being refreshed by the refresh command REF of the sub array A, One word line enable for write or read operation in B is enabled. The tREF2WR time and tREF2RD time can be seen as the time it takes for the word line of subarray A to turn off.

A write-to-active time tWR2ACT interval is required between the write command WR of subarray A and the active command ACT of subarray B. A read-to-active time (tRD2ACT) interval is required between the active command (ACT) of the subarray B after the read command (RD) of the subarray A. Active operation in the subarray B becomes possible when data is written into the memory cell by the write / read command WR / RD of the subarray A or when the column select line is turned off when the read data is latched in the data line sense amplifier . The tWR2ACT time and tRD2ACT time can be seen as the time it takes for the column select line of subarray A to turn off.

The precharge command (PRE) or write / read command (WR / RD) of subarray B is not valid after subarray A write / read command (WR / RD). This is because two word lines in different subarrays within a subarray group sharing a data input / output line can not be enabled at the same time.

A write-to-refresh time tWR2REF interval is required between the refresh command REF of the subarray B after the write command WR of the subarray A. A read-to-refresh time tRD2REF interval is required between the refresh command REF of the subarray B after the read command RD of the subarray A. When the column select line by the write / read command WR / RD of the subarray A is turned off, the refresh operation in the subarray B becomes possible. The tWR2REF time and tRD2REF time can be seen as the time it takes for the column select line of subarray A to turn off.

8 is a block diagram illustrating a first example of a memory system that may be used to implement one or more hidden timing parameter management method embodiments described herein.

8, the memory system 800 includes a memory controller 810 and a memory module 820. [ The memory controller 810 may provide command signals CMD, address signals ADDR, and data DQ to the memory module 820. The memory module 820 may include a plurality of memory devices 100 and a buffer chip 822. The memory module 820 may further include a non-volatile memory device 824.

For example, nine memory devices 100 may be mounted in the memory module 820. [ One of the nine memory devices 100 may be used to correct errors generated in the remaining eight memory devices 100. That is, an 8-bit parity bit is required to correct a 1-bit error generated in each of the eight memory devices 100. [ To this end, one memory device 100 may be used. Accordingly, between the memory controller 810 and the memory module 820, X72 data DQ, which is the sum of X8 data DQ input / output to / from each memory device 100, can be transferred.

The memory devices 100 may be memory devices operating in a sub-bank interleaving manner as described in FIGS. The memory device 100 may include a plurality of banks comprised of at least two or more sub-banks. The memory device 100 may operate to interleave the sub-banks in any one of the plurality of banks one after another consecutively.

The memory device 100 can be shortened in tRRD time intervals, where consecutive data write operations in one bank are the low active-to-low active times between different banks. Accordingly, the data write operation in one bank is performed by setting the memory cell data write time tWR ', the time tRCD' between the application of the / RAS signal and the / CAS signal or the bit line free charge time tRP ' It will be long. tRCD ', tWR', tRP 'times are not included in the interval time interval of consecutive data write operations of the sub-banks. In successive data write operation timings, the host, e.g., the memory controller, does not need to adhere to the tRCD ', tWR', tRP 'timing parameter specifications. tRCD ', tWR', tRP 'The time can be hidden by the memory controller.

In addition, the memory device 100 may be a memory device 500 including a plurality of banks in which memory cell array blocks composed of at least two subarray groups described in FIG. 5 are stacked. The memory device 100 can activate a sub-array in an area outside the keep away zone of the activated sub-array in the sub-array group. Further, when sub-arrays belonging to the keep away zone belong to another sub-array group, sub-arrays belonging to other sub-array groups can be inactivated. The memory device 100 may replace the defective cells generated in the subarrays in the subarray group with the redundant cells in the corresponding subarray in the corresponding subarray group or another subarray. The memory device 100 may have timing constraints on instruction combinations that are successively applied to different subarrays.

The buffer chip 822 may receive the command signals CMD and the address signals ADDR from the memory controller 810 and transmit them to the memory devices 100. [ If the interface speed with the memory controller 810 is much higher, the performance degradation caused by the speed difference through the buffer chip 822 can be minimized.

In addition, the buffer chip 822 can control the operation of the memory device 100 to be selectively relaxed. Buffer chip 822 monitors whether the received command signal CMD and address signal ADDR access the sub-banks in one bank of memory device 100. [

Buffer chip 822 may monitor the MSB signal (RA _MSB ) of the row address signal selecting sub-banks of memory device 100. When the sub-banks are accessed, the buffer chip 822 outputs the memory cell data write-in time tWR 'during the data write operation in one bank, the time tRCD' between the / RAS signal application and the CAS signal application, The memory device 100 can be operated in a relaxed manner so that the line free charge time tRP 'can be long.

The non-volatile memory device 824 may store the size of the sub-array group of the memory device 500 (FIG. 5), i.e., the number of sub-arrays included in the sub-array group. The non-volatile memory device 824 may be comprised of a fuse, an anti-fuse, a PROM, a flash memory, or the like. The size of the sub-array group stored in the non-volatile memory device 824 may be provided to the memory controller 810 during power-up.

The memory controller 810 can calculate the row address to be a boundary between each subarray and the row address bits for distinguishing each subarray group using the subarray group information of the memory device 100. [ Accordingly, the memory controller 810 can activate a sub-array in an area outside the keep away zone of the activated sub-array in the sub-array group of the memory device 100. [ Further, when the sub-arrays belonging to the keep away zone belong to another sub-array group, the sub-arrays can be inactivated. The memory controller 810 can replace the defective cells generated in the sub-arrays in the sub-array group of the memory device 100 with the corresponding redundant cells in the corresponding sub-array or other sub-arrays in the sub-array group. The memory controller 810 may comply with timing constraints that exist in command combinations that are successively applied to different subarrays of the memory device 100. [

9 is a block diagram illustrating a second example of a memory system that may be used to implement one or more hidden timing parameter management method embodiments described herein.

9, a memory system 900 includes a plurality of hosts 901 and 902, a memory controller 910, and a memory device 100. The hosts 901 and 902 may be configured as a microprocessor or the like. The memory controller 910 may control the memory device 100 according to a read or write command (RD / WR) requested from the hosts 901 and 902. [ The memory controller 910 can generate the command signal CMD and the address signal ADDR on the basis of the read or write command RD / WR of the host 901 or 902 and transmit the command signal CMD and the address signal ADDR to the memory device 100. The memory controller 910 can also send and receive data DQ to / from the memory device 100 according to the read or write command (RD / WR) of the host 901 or 902.

The memory devices 100 may be memory devices operating in a sub-bank interleaving manner as described in FIGS. The memory device 100 may include a plurality of banks comprised of at least two or more sub-banks. The memory device 100 may operate to interleave the sub-banks in any one of the plurality of banks one after another consecutively.

The memory device 100 can be shortened in tRRD time intervals, where consecutive data write operations in one bank are the low active-to-low active times between different banks. Accordingly, the data write operation in one bank is performed by setting the memory cell data write time tWR ', the time tRCD' between the application of the / RAS signal and the / CAS signal or the bit line free charge time tRP ' It will be long. tRCD ', tWR', tRP 'times are not included in the interval time interval of consecutive data write operations of the sub-banks. At consecutive data write operation timings of the sub-banks, the memory controller 710 does not need to adhere to the tRCD ', tWR', tRP 'timing parameter specifications. The tRCD ', tWR', tRP 'times can be hidden by the memory controller 910.

In addition, the memory device 100 may be a memory device 500 including a plurality of banks in which memory cell array blocks composed of at least two subarray groups described in FIG. 5 are stacked. The memory device 100 can activate a sub-array in an area outside the keep away zone of the activated sub-array in the sub-array group. Further, when sub-arrays belonging to the keep away zone belong to another sub-array group, sub-arrays belonging to other sub-array groups can be inactivated. The memory device 100 may replace the defective cells generated in the subarrays in the subarray group with the redundant cells in the corresponding subarray in the corresponding subarray group or another subarray. The memory device 100 may have timing constraints on instruction combinations that are successively applied to different subarrays.

The memory controller 910 can convert the command signal CMD and the address signal ADDR of the memory device 100 according to a read or write command Rd / WR requested from the hosts 901 and 902. [ The memory controller 910 may include a transaction queue 911, a command queue 915, and a monitoring unit 916. The transcoding queue 911 includes an ordering unit 912 for ordering a read or write command (RD / WR) requested from a plurality of hosts 901 and 902, And a logic unit 913 for generating the command RD / WR as the command signal CMD and the address signal ADDR of the memory device 100. [ The command queue 915 may sequentially store the command signal CMD and the address signal ADDR generated through the logic unit 913 and then transmit the command signal CMD and the address signal ADDR to the memory device 100.

The monitoring unit 916 may monitor the command signal CMD and the address signal ADDR stored in the command queue 915 to determine whether to access subbanks in one bank of the memory device 100. [ The monitoring unit 916 may monitor the MSB signal (RA _MSB ) of the row address signal selecting the sub-banks of the memory device 100. When the sub-banks are accessed, the monitoring unit 916 outputs the memory cell data write-in time tWR 'during the data write operation in one bank, the time tRCD' between the / CAS signal application after the / RAS signal application, The memory device 100 can be operated in a relaxed manner so that the line free charge time tRP 'can be long.

The memory controller 910 can calculate the row address to be a boundary between each subarray and the row address bits for distinguishing each subarray group using the subarray group information of the memory device 100. [ Accordingly, the memory controller 910 can activate a sub-array in an area outside the keep away zone of the activated sub-array in the sub-array group of the memory device 100. [ Further, when the sub-arrays belonging to the keep away zone belong to another sub-array group, the sub-arrays can be inactivated. The memory controller 910 may replace the defective cells generated in the sub-arrays in the sub-array group of the memory device 100 with the corresponding redundant cells in the corresponding sub-array or other sub-arrays in the sub-array group. The memory controller 910 may comply with timing constraints that exist in command combinations that are successively applied to different subarrays of the memory device 100. [

The memory controller 910 observes whether the memory device 100 operates in accordance with the timing parameter specification in the data write operation, as shown in Fig. When the memory device 100 operates in the bank interleaving mode shown in FIG. 3A, the memory controller 910 reads out the write operation data DIN from the data write operation timings, for example, tWR time and tRP Observe time regulations. The tWR time may be specified to be, for example, at least 15 ns, and the tRP time may be defined to be, for example, at least 15 ns.

When the memory device 100 operates in the sub-bank interleaving manner of FIGS. 3B to 3D, for example, when different sub-banks are selected by toggling the MSB signal (RA _MSB ) of the row address signal, the memory controller 910 ) Need not comply with the tWR time specification and the tRP time specification among the data write operation timings. At this time, the tWR time of the memory device 100 to which the memory controller 910 complies is defined as 0 ns, and the tRP time can also be defined as 0 ns. As the tRP time is defined as 0 ns, the precharging operation that is actually operated in the memory device 100 becomes a hidden precharging operation.

On the other hand, even if the memory device 100 operates in the sub-bank interleaving mode of FIGS. 3B to 3D, the MSB signal (RA _MSB ) of the row address signal is not toggled, so that the same sub-banks may be selected. In this case, it can be seen that the memory device 100 operates in a manner similar to the subsequent same bank access operation in the bank interleaving mode. The memory controller 910 needs to comply with the tWR time specification and the tRP time specification among the data write operation timings. At this time, the tWR time of the memory device 100 to which the memory controller 910 complies may be defined as, for example, at least 25 ns, and the tRP time may be defined as at least 15 ns, for example.

The memory device implementing the at least one hidden timing parameter management method described herein may be included in a semiconductor memory device such as the DDR-SDRAM as shown in FIG.

Referring to FIG. 11, the DDR-SDRAM 1100 may include a memory cell array 1101 including a DRAM cell and various circuit blocks for driving the DRAM cell. For example, the timing register 1102 may be activated when the chip select signal CS changes from the inactive level (e.g., logic high) to the activation level (e.g., logic low). The timing register 1202 receives a clock signal CLK, a clock enable signal CKE, a chip select signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, A write enable signal WEB and a data input / output mask signal DQM and processes the received command signal to generate various internal command signals LRAS, LCBR, LWE, LCAS, LWCBR, LDQM).

Some internal command signals generated from the timing register 1102 are stored in the programming register 1204. For example, latency information or burst length information related to data output may be stored in the programming register 1104. The internal command signals stored in the programming register 1104 may be provided to the latency / burst length controller 1106. The latency / burst length controller 1106 may supply a control signal for controlling the latency or burst length of the data output to the column buffer / To the column decoder 1110 or to the output buffer 1112 through the input buffer 1108. [

The address register 1120 can receive an address signal ADD from the outside. The row address signal may be provided to the row decoder 1124 via the row address buffer 1122. Also, the column address signal may be provided to the column decoder 1110 through the column address buffer 1108. The row address buffer 1122 can further receive the refresh address signal generated in the refresh counter in response to the refresh instructions LRAS and LCBR and provides either the row address signal or the refresh address signal to the row decoder 1124 can do. In addition, the address register 1120 may provide a bank signal for selecting a bank to the bank selector 1126. [

The row decoder 1124 can decode the row address signal or the refresh address signal input from the row address buffer 1122 and activate the word line of the memory cell array 1101. [ The column decoder 1110 may decode the column address signal and perform a selection operation on the bit lines of the memory cell array 1101. [ As an example, a column selection line is applied to the semiconductor memory device 1100 so that a selection operation through a column selection line can be performed.

The sense amplifier 1130 may amplify the data of the memory cell selected by the row decoder 1124 and the column decoder 1110 and provide the amplified data to the output buffer 1112. The data for writing data cells is provided to the memory cell array 1101 through a data input register 1132 and the input and output controller 1134 can control data transfer operations through the data input register 1132.

The memory cell array 1101 may include a plurality of banks composed of at least two sub-banks. In the memory cell array 1101, subbanks in any one of the plurality of banks can be successively interleaved one by one. Consecutive data write operations in one bank can be shortened to a tRRD time interval that is a low active-to-low active time between different banks. Accordingly, the data write operation in one bank is performed by setting the memory cell data write time tWR ', the time tRCD' between the application of the / RAS signal and the / CAS signal or the bit line free charge time tRP ' It will be long. tRCD ', tWR', tRP 'times are not included in the interval time interval of consecutive data write operations of the sub-banks. At the timing of consecutive data write operations of the sub-banks, the memory controller does not need to comply with the tRCD ', tWR', tRP 'timing parameter specifications. tRCD ', tWR', tRP 'The time can be hidden by the memory controller.

In addition, the memory cell array 1101 may include a plurality of banks in which memory cell array blocks composed of two or more sub-array groups are stacked. In the memory cell array 1101, a sub-array in an area outside the keep away zone of the activated sub-array in the sub-array group can be activated. Further, when sub-arrays belonging to the keep away zone belong to another sub-array group, sub-arrays belonging to other sub-array groups can be inactivated. In the memory cell array 1101, defective cells generated in the subarrays in the subarray group can be replaced with redundant cells in the corresponding subarray in the corresponding subarray group or other subarrays. In the memory cell array 1101, there may be timing constraints on instruction combinations that are successively applied to different subarrays.

12 is a diagram showing an embodiment of a memory system to which the semiconductor memory device of FIG. 11 is applied.

12, the memory system 1200 may include a memory module 1210 and a memory controller 1220. The memory module 1210 may mount at least one semiconductor memory device 1230 on a module board. The semiconductor memory device 1230 may be implemented as a DRAM chip, and each semiconductor memory device 1230 may include a plurality of semiconductor layers. The semiconductor layers may include one or more master chips 1231 and one or more slave chips 1232. The transfer of signals between the semiconductor layers can be performed through a through silicon via (TSV).

The master chip 1231 and the slave chip 1232 may include the memory device 100 according to embodiments of the present invention. The memory devices 100 may be memory devices operating in a sub-bank interleaving manner as described in FIGS. The memory device 100 may include a plurality of banks comprised of at least two or more sub-banks. The memory device 100 may operate to interleave the sub-banks in any one of the plurality of banks one after another consecutively.

The memory device 100 can be shortened in tRRD time intervals, where consecutive data write operations in one bank are the low active-to-low active times between different banks. Accordingly, the data write operation in one bank is performed by setting the memory cell data write time tWR ', the time tRCD' between the application of the / RAS signal and the / CAS signal or the bit line free charge time tRP ' It will be long. tRCD ', tWR', tRP 'times are not included in the interval time interval of consecutive data write operations of the sub-banks. At the timing of consecutive data write operations of the sub-banks, the memory controller does not need to comply with the tRCD ', tWR', tRP 'timing parameter specifications. tRCD ', tWR', tRP 'The time can be hidden by the memory controller.

In addition, the memory device 100 may be a memory device 500 including a plurality of banks in which memory cell array blocks composed of at least two subarray groups described in FIG. 5 are stacked. The memory device 100 can activate a sub-array in an area outside the keep away zone of the activated sub-array in the sub-array group. Further, when sub-arrays belonging to the keep away zone belong to another sub-array group, sub-arrays belonging to other sub-array groups can be inactivated. The memory device 100 may replace the defective cells generated in the subarrays in the subarray group with the redundant cells in the corresponding subarray in the corresponding subarray group or another subarray. The memory device 100 may have timing constraints on instruction combinations that are successively applied to different subarrays.

Memory module 1210 may communicate with memory controller 1220 via a system bus. Data DQ, a command / address CMD / ADD and a clock signal CLK can be transmitted and received between the memory module 1210 and the memory controller 1220 via the system bus.

Figure 13 is a block diagram illustrating a computing system with a memory system in accordance with one embodiment of the present invention.

Referring to FIG. 13, a semiconductor memory device of the present invention may be mounted as a RAM 1320 in a computing system 1300 such as a mobile device or a desktop computer. The semiconductor memory device to be mounted with the ram 1320 can be applied to any of the above-described embodiments. For example, the RAM 1320 may be applied to the semiconductor memory device in the above embodiments, or may be applied in the form of a memory module. The RAM 1320 may also be a concept that includes a semiconductor memory device and a memory controller.

A computing system 1300 according to an embodiment of the present invention includes a central processing unit 1310, a RAM 1320, a user interface 1330 and a non-volatile memory 1340, As shown in Fig. The nonvolatile memory 1340 may be a mass storage device such as an SSD or a HDD.

In computing system 1300, RAM 1320 may include a memory device 100 in accordance with embodiments of the present invention. The memory devices 100 may be memory devices operating in a sub-bank interleaving manner as described in FIGS. The memory device 100 may include a plurality of banks comprised of at least two or more sub-banks. The memory device 100 may operate to interleave the sub-banks in any one of the plurality of banks one after another consecutively.

The memory device 100 can be shortened in tRRD time intervals, where consecutive data write operations in one bank are the low active-to-low active times between different banks. Accordingly, the data write operation in one bank is performed by setting the memory cell data write time tWR ', the time tRCD' between the application of the / RAS signal and the / CAS signal or the bit line free charge time tRP ' It will be long. tRCD ', tWR', tRP 'times are not included in the interval time interval of consecutive data write operations of the sub-banks. At consecutive data write operation timings of the sub-banks, the memory controller 710 does not need to adhere to the tRCD ', tWR', tRP 'timing parameter specifications. tRCD ', tWR', tRP 'can be hidden by the memory controller 710.

In addition, the memory device 100 may be a memory device 500 including a plurality of banks in which memory cell array blocks composed of at least two subarray groups described in FIG. 5 are stacked. The memory device 100 can activate a sub-array in an area outside the keep away zone of the activated sub-array in the sub-array group. Further, when sub-arrays belonging to the keep away zone belong to another sub-array group, sub-arrays belonging to other sub-array groups can be inactivated. The memory device 100 may replace the defective cells generated in the subarrays in the subarray group with the redundant cells in the corresponding subarray in the corresponding subarray group or another subarray. The memory device 100 may have timing constraints on instruction combinations that are successively applied to different subarrays.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (20)

A plurality of banks in which a plurality of memory cells are arranged,
Each of the banks including at least two sub-banks,
In a sub-bank interleaving scheme in which the sub-banks in the one bank are successively operated one by one, continuous operation between the sub-banks follows a low active-to-low active time (tRRD) interval between the different banks and,
Wherein a data write time (tWR) to the memory cell in a consecutive data write operation between the sub-banks is set to be longer than a data write time to the memory cell in a consecutive data write operation between the banks, Is not included in the interval time interval of consecutive data write operations between the data write operations. The method according to claim 1,
Wherein the sub-banks are selectively accessed using one or more bits of row address signals addressing the memory cells. delete delete The method according to claim 1,
Wherein a bit line free timing time (tRP) of the memory cell in a consecutive data write operation between the sub-banks is set to be longer than a bit line free timing time of the memory cell in a consecutive data write operation between the banks ≪ / RTI > Claim 6 has been abandoned due to the setting registration fee. 6. The method of claim 5,
Wherein a bit line free timing time (tRP) of the memory cell is not included in an interval time interval of consecutive data write operations between the sub-banks. The method according to claim 1,
The time tRCD between the row active command and the column active command in the continuous data write operation between the subbanks is set longer than the time between the row active command and the column active command in the continuous data write operation between the banks ≪ / RTI > Claim 8 has been abandoned due to the setting registration fee. 8. The method of claim 7,
And the time tRCD between the row active command and the column active command is not included in the interval time interval of consecutive data write operations between the sub-banks. Claim 9 has been abandoned due to the setting registration fee. The method according to claim 1,
Wherein the sub-banks are arranged in a direction in which the word lines of the memory cells are arranged. Claim 10 has been abandoned due to the setting registration fee. The method according to claim 1,
Wherein the sub-banks are arranged in a direction in which bit lines of the memory cells are arranged. The method according to claim 1,
Wherein the sub-banks are connected to data line sense blocks and data input / output lines that are independent of each other. A plurality of banks in which a plurality of memory cells are arranged,
Each of the banks including a plurality of subarrays,
Array sub-arrays, dividing the sub-arrays into at least two sub-array groups, observing timing constraints between consecutive instruction combinations applied to the sub-arrays included in each of the sub-
Wherein the timing constraints are set to a time at which the column select line of the subarray operating in the previous instruction is turned off in the subarrays to which the sequential instructions are applied. 13. The method of claim 12, wherein the sub-
And selectively accessed using one or more bits of row address signals addressing the memory cells. 13. The memory device of claim 12, wherein the memory device
Wherein when one of the subarrays in the subarray group is activated, the subarrays adjacent to the activated subarray belong to the keepaway zone and are deactivated. Claim 15 is abandoned in the setting registration fee payment. 15. The memory device of claim 14, wherein the memory device
And the sub-array belonging to the other sub-array group is deactivated when the sub-array belonging to the keep away zone belongs to another sub-array group. 13. The memory device of claim 12, wherein the memory device
Wherein when a defective cell is generated in the sub-array in the sub-array group, the defective cell is replaced with a redundant cell in the corresponding sub-array or another sub-array in the corresponding sub-array group. 13. The memory device of claim 12, wherein the memory device
And a storage unit for storing the size of the sub-array group indicating the number of the sub-arrays included in each of the sub-array groups. Claim 18 has been abandoned due to the setting registration fee. 18. The apparatus of claim 17, wherein the storage unit
Wherein the memory device is a non-volatile device composed of a fuse or an anti-fuse. Claim 19 is abandoned in setting registration fee. 13. The method of claim 12, wherein each sub-
And the data line sense block and the data input / output lines are connected to each other. delete

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