KR20120130149A - Flexible field-effect transistor and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A flexible field effect transistor and a manufacturing method thereof are provided to implement a low voltage operation graphene FET array on a plastic base material using ion gel as a gate insulator. CONSTITUTION: A source electrode, a drain electrode(308), and a gate electrode(312) are provided. A carbon nano structure semiconductor layer(304) is arranged to form a channel region between the source electrode and the drain electrode. An ion gel layer(310) forms insulator layers between the carbon nano structure semiconductor layer and the gate electrode and between the channel region and the gate electrode.

Description

FLEXIBLE FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD OF THE SAME

The present application relates to a flexible field effect transistor and a method for manufacturing the same, and an integrated circuit including the above. Specifically, a flexible field effect transistor including a semiconductor layer and an ion gel insulating layer including a carbon nanostructure, and a method for manufacturing the same, And an integrated circuit comprising the flexible field effect transistor.

Carbon nanostructures such as carbon nanotubes (CNT), graphene, and carbon nanofibers are used in nanoelectronics, nanoelectromechanical systems (NEMS), sensors, contact electrodes, and nanophotonics. ) And some of the most promising candidates for future growth in nanobiotechnology and the like. This is primarily due to the one-dimensional properties, unique electrical, optical and mechanical properties of the carbon nanostructures.

Meanwhile, graphene of the carbon nanostructures refers to a single layer of carbon having a hexagonal structure, that is, a single layer of (0001) cotton of graphite, and such graphene is known to have better physical properties than carbon nanotubes. In particular, since graphene has an electrical conductivity of 50 to 100 times that of silicon, much research is being conducted as a new material that can replace a semiconductor such as silicon.

Graphene has attracted attention in a range of electronic applications, such as displays, solar cells and sensors because of its exceptional electronic and optoelectronic properties. Recent technological developments in large-area synthesis of high quality graphene films have created new pathways for the application of graphene as high frequency devices. There are two general approaches to fabricating graphene devices over large areas. One is to use graphene grown directly on the SIC wafer, and the other is to transfer the graphene film synthesized on the metal layer to another useful substrate. The latter approach draws attention to the particular properties of graphene films, such as flexible / stretchable device fabrication and the possibility of fabrication over large areas. This approach can produce device arrays on rigid insulating wafers and base them on wafer size. Although several studies have reported graphene field effect transistors (FETs) on plastic substrates, flexible graphene FETs are still an important challenge in large scale manufacturing.

Graphene research for flexible electronics requires high-capacity gate insulators that can be formed at low temperatures with good interfaces with graphene films transferred to solution-processable, plastic sheets. Although many high-k (dielectric constant) inorganic insulators, such as HfO ₂ , Al ₂ O ₃ and ZrO ₂ have been applied in the manufacture of graphene FETs, they are not available for flexible devices based on plastic substrates because of their high growth temperature. Can't.

The present application is to provide a high performance low voltage-driven flexible field effect transistor by developing a flexible field effect transistor including a carbon nanostructure semiconductor layer and an ion gel insulating layer and a manufacturing method thereof, and further comprising the integrated circuit It is intended to provide a use for the present invention.

However, the problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

A first aspect of the present application provides a flexible field effect transistor, comprising:

A source electrode and a drain electrode;

A semiconductor layer including carbon nanostructures disposed to form a channel region between the source electrode and the drain electrode;

Gate electrode: and

An ion gel layer forming an insulator layer between the channel region and the gate electrode between the semiconductor layer including the carbon nanostructure and the gate electrode.

In an exemplary embodiment, the carbon nanostructure may include one selected from the group consisting of graphene, carbon nanotubes, carbon nanofibers, carbon nanowires, carbon nanocones, and combinations thereof. It is not limited to this.

In an exemplary embodiment, the carbon nanostructures may include, but are not limited to, carbon nanostructures. In an exemplary embodiment, the graphene may be formed by a chemical vapor deposition method on the metal catalyst layer, but is not limited thereto. For example, the metal catalyst layer may be a thin film or a thick film, the metal catalyst layer is Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U , V, Zr, Fe, brass (brass), bronze (bronze), stainless steel (stainless steel), may include one or more metals or alloys thereof selected from the group consisting of, and combinations thereof, but is not limited thereto. It doesn't happen. The chemical vapor deposition method may be carried out at atmospheric pressure or low pressure, may be carried out using a plasma, it can be used for all the graphene manufacturing method using a chemical vapor deposition method known in the art.

In an exemplary embodiment, the ion gel layer may include, but is not limited to, an ionic liquid and a block copolymer including at least three blocks. Here, the block copolymer may form a self-assembled polymer in the ionic liquid.

In one embodiment, the block copolymer may include at least A block and B block, but is not limited thereto. In one embodiment, the A block may comprise a low polar polymer that is hardly soluble in an ionic liquid, and the A block may be at least partially glassy at room temperature. In one embodiment, the B block may be miscible with the ionic liquid. For example, the A block includes at least one of polystyrene and poly (N-isopropyl acrylamide), and the B block is poly (methylmethacrylate) [ poly (methylmethacrylate)], poly (ethylacrylate) [poly (ethyl acrylate)] and poly (ethylene oxide) [poly (ethylene oxide)] but may include at least one, but is not limited thereto.

In one embodiment, the block copolymer may include poly (styrene-block-ethylene oxide-block-styrene), but is not limited thereto. It is not.

In one embodiment, the block copolymer is poly (N-isopropylacrylamide-block-ethyleneoxide-block-N-isopropylacrylamide) [poly (N-isopropyl acrylamide-block-ethylene oxide-block-N -isopropyl acrylamide)], but is not limited thereto.

In one embodiment, the ionic liquid may be selected from the group consisting of [BMIM] [PF ₆ ], [EMIM] [TFSI], [EMIM] [OctSO ₄ ], but is not limited thereto.

In an exemplary embodiment, the gate electrode may be offset from the source electrode and the drain electrode, but is not limited thereto.

In an exemplary embodiment, the source electrode and the drain electrode may include a metal and / or a conductive polymer, but is not limited thereto. For example, the conductive polymer may be polypyrrole, polythiophene, poly (3-alkylthiophene), polyaniline, polyphenylene sulfide, polyfuran, polyiso-thianaphthene, poly (p-petylenevinylene, poly (p-phenylene), poly (3,4-ethylenedioxythiophene), poly (ethylene glycol) diacrylate, 2-hydroxy-2-methylpropiophenone and combinations thereof It may be, but is not limited thereto.

In an exemplary embodiment, the gate electrode may include a metal and / or a conductive polymer, but is not limited thereto. For example, the conductive polymer may be polypyrrole, polythiophene, poly (3-alkylthiophene), polyaniline, polyphenylene sulfide, polyfuran, polyiso-thianaphthene, poly (p-petylenevinylene, poly (p-phenylene), poly (3,4-ethylenedioxythiophene), poly (ethylene glycol) diacrylate, 2-hydroxy-2-methylpropiophenone and combinations thereof It may be, but is not limited thereto.

A second aspect of the present application is a flexible electric field comprising a source electrode, a drain electrode and a gate electrode, comprising forming an ion gel layer to form an insulator layer between the gate electrode and a semiconductor layer comprising a carbon nanostructure. A method of manufacturing an effect transistor is provided.

In an exemplary embodiment, the source electrode and the drain electrode may include a metal and / or a conductive polymer, but is not limited thereto. For example, the conductive polymer may be polypyrrole, polythiophene, poly (3-alkylthiophene), polyaniline, polyphenylene sulfide, polyfuran, polyiso-thianaphthene, poly (p-petylenevinylene, poly (p-phenylene), poly (3,4-ethylenedioxythiophene), poly (ethylene glycol) diacrylate, 2-hydroxy-2-methylpropiophenone and combinations thereof It may be, but is not limited thereto.

In an exemplary embodiment, the gate electrode may include a metal and / or a conductive polymer, but is not limited thereto. For example, the conductive polymer may be polypyrrole, polythiophene, poly (3-alkylthiophene), polyaniline, polyphenylene sulfide, polyfuran, polyiso-thianaphthene, poly (p-petylenevinylene, poly (p-phenylene), poly (3,4-ethylenedioxythiophene), poly (ethylene glycol) diacrylate, 2-hydroxy-2-methylpropiophenone and combinations thereof It may be, but is not limited thereto.

In an exemplary embodiment, the source electrode, the drain electrode, the ion gel layer and the gate electrode may be formed by a printing method, but is not limited thereto.

In an exemplary embodiment, the ion gel layer may include patterning using a printing method using a nozzle, but is not limited thereto.

In an exemplary embodiment, the ion gel layer may include a polymer having a characteristic of being gelled by curing with an ionic liquid and ultraviolet rays, but is not limited thereto. This ion gel layer can be applied using a photopatterning process. For example, in a photopatterning process, an ion gel ink including a polymer monomer, an initiator, and an ionic liquid, which is cured and gelled by ultraviolet rays, is added dropwise onto a substrate on which a patterned semiconductor layer is formed, and the patterned mask By placing UV on the ion gel layer and then exposing UV, by the UV exposure, the initiator generates radicals and reacts with reactive times in the oligomer molecules, and polymerization of the reactive end groups in each oligomer molecule It is possible to form chemically cross-linked ion gels.

In an exemplary embodiment, the method of forming an ion gel comprises mixing or applying a block copolymer comprising at least three blocks to an ionic liquid such that the block copolymer forms a self-assembled polymerization network in the ionic liquid. It may include, but is not limited to. The ion gel may be thermally reversible, and thus, the ion gel forming method may further include forming a liquid solution by increasing the temperature of the ion gel above a critical solution temperature of the ion gel.

In one embodiment, the manufacturing method of the flexible field effect transistor,

Forming a source electrode, a drain electrode and a gate electrode on the substrate;

Forming a semiconductor layer including carbon nanostructures on the source electrode and the drain electrode;

Forming an ion gel layer on the semiconductor layer comprising the gate electrode and the carbon nanostructures to form an insulator layer between the gate electrode and the semiconductor layer comprising the carbon nanostructures:

It may be to include, but is not limited thereto.

In another embodiment, the method of manufacturing the flexible field effect transistor,

Forming a semiconductor layer comprising carbon nanostructures on the substrate;

Forming a source electrode and a drain electrode on the semiconductor layer;

Forming an ion gel layer on the semiconductor layer, the source electrode and the drain electrode to form an insulator layer;

Forming a gate electrode on the ion gel layer:

It may be to include, but is not limited thereto.

In another embodiment, the method of manufacturing the flexible field effect transistor,

Forming a source electrode and a drain electrode on the substrate;

Forming a semiconductor layer including carbon nanostructures on the substrate, the source electrode and the drain electrode;

Forming an ion gel layer on the semiconductor layer, the source electrode and the drain electrode to form the insulating layer;

Forming a gate electrode on the ion gel layer:

It may be to include, but is not limited thereto.

In another embodiment, the method of manufacturing the flexible field effect transistor,

Forming a gate electrode on the substrate;

Forming an ion gel layer on the substrate and the gate electrode to form an insulator layer;

Forming a source electrode and a drain electrode on the ion gel layer;

Forming a semiconductor layer including carbon nanostructures on the ion gel layer, the source electrode and the gate electrode:

It may be to include, but is not limited thereto.

In an exemplary embodiment, the carbon nanostructures include those selected from the group consisting of graphene, carbon nanotubes, carbon nanofibers, carbon nanowires, carbon nanoribbons, carbon nanocones, and combinations thereof. It may be, but is not limited thereto.

In an exemplary embodiment, the carbon nanostructures may include, but are not limited to, carbon nanostructures. In an exemplary embodiment, the graphene may be formed by a chemical vapor deposition method on the metal catalyst layer, but is not limited thereto. For example, the metal catalyst layer may be a thin film or a thick film, Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U, V, Zr , Fe, brass (bronze), bronze (bronze), stainless steel (stainless steel), may include one or more metals or alloys thereof selected from the group consisting of, and combinations thereof, but is not limited thereto.

In an exemplary embodiment, the ion gel layer may include an ionic liquid and at least three block copolymers, but is not limited thereto. For example, the at least three block copolymer may include poly (styrene-block-ethylene oxide-block-styrene), but is not limited thereto. It is not. For example, the at least triblock copolymer is poly (N-isopropylacrylamide-block-ethyleneoxide-block-N-isopropylacrylamide) [poly (N-isopropyl acrylamide-block-ethylene oxide-block-N -isopropyl acrylamide)], but is not limited thereto.

In one embodiment, the ionic liquid may be selected from the group consisting of [BMIM] [PF ₆ ], [EMIM] [TFSI], [EMIM] [OctSO ₄ ], and combinations thereof, but is not limited thereto. It doesn't happen.

According to a third aspect of the present disclosure, an integrated circuit including a flexible field effect transistor manufactured by the manufacturing method may be provided.

In an exemplary embodiment, the integrated circuit may further include a light emitting diode, but is not limited thereto.

The present application allows fabrication of low voltage actuated graphene FET arrays on plastic substrates using ion gels as gate insulators. The ion gel is formed of a room temperature ionic liquid and a gelling triblock copolymer, and the high capacity (high capacitance) of the ion gel gate insulator in these graphene FETs is high on-current. And low voltage operation. In addition, graphene FETs with iongel gates fabricated on plastic substrates exhibit very good mechanical flexibility.

1 is a flow chart illustrating a method of preparing a polymer gel according to an embodiment of the present application,
2 is a flow chart illustrating an exemplary method of treating a thermoreversible ion gel in accordance with an embodiment of the present disclosure.
3 is a cross-sectional view of a TFT according to an embodiment of the present application;
4 is a flowchart illustrating a method of manufacturing the TFT manufacturing method of FIG. 3;
5 is a cross-sectional view illustrating a TFT according to another embodiment of the present application;
FIG. 6 is a flowchart illustrating a method of manufacturing the TFT of FIG. 5.
7 is a cross-sectional view illustrating a TFT according to another embodiment of the present application;
8 is a flowchart showing a method of manufacturing the TFT of FIG.
9 is a cross-sectional view illustrating a TFT according to another embodiment of the present application;
10 is a flowchart illustrating a method of manufacturing the TFT of FIG. 9,
11A is a graph showing current-voltage transition characteristics of a field effect transistor manufactured on a rigid substrate according to an embodiment of the present disclosure;
11B is a graph showing the output characteristics of a device at five different gate voltages of a field effect transistor fabricated on a rigid substrate according to one embodiment of the present disclosure;
FIG. 11C is a graph showing the transition characteristics of a device at five different drain voltages of a field effect transistor fabricated on a rigid substrate in accordance with an embodiment of the present disclosure. FIG.
11D is a graph showing output characteristics of an ion gel gate device according to an embodiment of the present application,
12 is a view showing a process of manufacturing an ion gel gate transistor according to an embodiment of the present application;
13A is an arrangement image of a device on a plastic substrate, in accordance with an embodiment of the present disclosure;
13B is a graph showing the transition and output characteristics of a FET on a plastic substrate according to one embodiment of the present disclosure,
FIG. 13C is a graph illustrating a distribution of holes and electron mobility of the FET according to an embodiment of the present disclosure; FIG.
13D is a graph showing the effective carrier mobility (μ / μ ₀ ) normalized as a function of bending-induced bending radius of FETs according to one embodiment of the present disclosure,
14 is a view showing a FET manufacturing process according to another embodiment of the present application,
15A is a photograph of a transparent graphene FET array manufactured by a photo patterning process according to another embodiment of the present disclosure.
15B is an NIR spectrum showing light transparency of a laminated film according to another embodiment of the present application,
15C is a graph illustrating drain current (I _D ) -drain voltage (V _D ) of transparent graphene FETs according to another exemplary embodiment of the present disclosure.
15D is a graph showing I _D at various V _D as a function of gate voltage V _G according to another embodiment of the present disclosure,
15E is a graph showing the distribution of holes and electron mobility of graphene FET 50 printed in various batches according to another embodiment of the present disclosure,
16A is a photograph of a transparent graphene FET array manufactured by an aerosol jet printing process according to another embodiment of the present disclosure.
16B is a graph showing charge density-conductivity characteristics at three different drain voltages according to another embodiment of the present disclosure;
16C is a graph showing the change in normalized effect hole / electron mobility in an unbent state (μ / μ ₀ ) according to another embodiment of the present disclosure,
16D is a graph showing μ / μ ₀ change after hundreds of bending cycles caused to vary between 0% and 2% of tensile stress in a device according to another embodiment of the present disclosure;
17A is a photograph showing a graphene FET array all printed on plastic according to another embodiment of the present application.
17B is a graph showing conductivity versus charge density of graphene FET arrays all printed on plastic according to another embodiment of the present disclosure.

DETAILED DESCRIPTION Hereinafter, embodiments and examples of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present disclosure.

It should be understood, however, that the present invention may be embodied in many different forms and is not limited to the embodiments and examples described herein. In the drawings, the same reference numbers are used throughout the specification to refer to the same or like parts.

Throughout this specification, when a member is located "on" with another member, this includes not only when a member is in contact with another member, but also when there is another member between the two members. In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless specifically stated otherwise.

In one embodiment of the invention, the ion gel is a triblock copolymer comprising two chemically similar A blocks (collectively " copolymer chains ") that are almost insoluble in ionic liquids in a defined temperature range (collectively "B blocks"). The copolymer chain may also comprise a B block (collectively “B block”) that can be dissolved in an ionic liquid miscible with the ionic liquid.The critical gelation concentration (ie, the copolymer from which the osmotic network form is formed When an amount of triblock copolymer greater than 3) is added to the ionic liquid, micelles (collectively referred to as "microcells") formed by insoluble A blocks and bridged by miscible B blocks A polymer network comprising ") is formed in the ionic liquid to form an ion gel comprising a triblock copolymer and an ionic liquid.

Interactions between the ionic liquids, A blocks and B blocks of the copolymer chain can be considered when selecting the ionic liquids and block copolymers. The ionic liquid preferentially dissolves B blocks, but does not dissolve A blocks. When this shape occurs, the A blocks are non-covalently linked to form micelles. At least a portion of the B block connects between micelles, connecting A blocks of the same copolymer chain in different micelles. The connection of individual micelles by the B blocks imparts mechanical strength to the gel, and the more B blocks bridge the gap between the micelles, the greater the mechanical strength of the gel.

However, some copolymer chains may have A blocks located within the same micelle. And the B block of this copolymer chain is located around the micelle, but does not connect between the two micelles 108. Therefore, when the two A blocks are located in the same micelle, the copolymer chain does not contribute much to the strength of the ion gel.

Moreover, as briefly mentioned above, the B blocks are inherently well soluble in ionic liquids. The solubility of the B block in a given ionic liquid can be customized by the selection of the constituent monomers of the B block. More specifically, it is preferable that the B block does not form any crystalline domains in the ionic liquid, which may occur if the ionic liquid is not sufficiently mixed with the B block. The crystalline B block domain can reduce the partial dynamics of the B block, which in turn can reduce the mobility of the ionic liquid in the ion gel. Reducing the mobility of the ionic liquid in the ion gel may undesirably reduce the ionic conductivity of the ion gel. Therefore, it is preferable that the B block is miscible with the ionic liquid so that no crystalline B block domain is formed.

In one embodiment, the B block may comprise a polymer having a low glass transition temperature (T _g ). For example, T _g below the service temperature of the gel is preferred, and the B block is almost rubbery or viscous liquid at the service temperature. In one embodiment, the B block has a T _g of about 220 K (about -53 ° C.). Low T _g indicates fast segment kinetics, which will affect the mobility of ions in the ionic liquid.

The properties of the ion gel can be further customized for a particular application by selecting the molecular weight of the B block. As described above, the B block forms a connection between the micelles formed by the A block. Therefore, higher molecular weight (longer) B blocks can lead to increased average distances between micelles formed by self-assembled A blocks. One distance measurement between the micelles is the mesh size of the gel. The larger the mesh size, the larger the average distance between adjacent micelles. Thus, longer B blocks lead to gels with larger mesh sizes, and shorter B blocks lead to gels with smaller mesh sizes.

Preferred molecular weights of the B blocks range from about 10,000 g / mol to about 100,000 g / mol, more preferably from about 20,000 g / mol to about 50,000 g / mol. In some embodiments, larger B blocks lead to a smaller weight percentage (wt%) of the copolymer required in the ion gel causing gelation.

In addition, the B block may also include a constituent monomer dissolved in the ionic liquid. In some cases, this means B blocks with permanent polar functional groups or functional groups that can be polarized, including, for example, carbonyl groups, ether groups, amine groups, and the like. Some preferred B blocks may include poly (methylmethacrylate), poly (ethyleneoxide), poly (ethylacrylate), and the like.

On the other hand, the A block may be selected as essentially insoluble in the ionic liquid. In one embodiment, the A block selects one that is essentially insoluble in the ionic liquid at all temperatures experienced by the ion gel (eg, process temperature, use temperature, storage temperature, etc.). In another embodiment, do not dissolve in the ionic liquid at a temperature below the Upper Critical Solution Temperature (UCST) of the block copolymer / ionic liquid system and UCST of the block copolymer / ionic liquid system A block is selected that dissolves in more ionic liquid. The UCST is the temperature at which a mixture of block copolymer and ionic liquid changes from a micelle suspension to a molecular solution. In this way, a thermoreversible ion gel can be prepared.

Thermoreversible gels may be desirable in many cases. For example, thermoreversibility can be treated as a viscous solution at a high temperature and then cooled to a lower use temperature to allow the ion gel to form. This means that thermoreversible gels can be used in printing applications such as, for example, screen printing, flexographic printing, gravure printing, aerosol jet printing, inkjet printing, and the like; It may be allowed to be used extensively in processes including coating applications and the like.

Thermoreversibility can be customized through the selection of the constituent monomers of the A block, the molecular weight of the A block, and the selection of the ionic liquid. For example, the more miscible the A block is with the ionic liquid, the lower the UCST will be. In contrast, the less miscible A block will increase the UCST of the block copolymer / ionic liquid system. As another example, as the molecular weight (and length) of the A block increases, UCST is also expected to increase.

Preferred molecular weight ranges for each A block include about 2,000 g / mol to about 20,000 g / mol, more preferably about 5,000 g / mol to about 10,000 g / mol.

Regardless of whether the ion gel is thermoreversible, it is generally preferred that the ion gel is a gel at the temperature of use. As briefly described above, the formation of a gel requires a concentration of copolymer above the critical gelation concentration. Ion gels of the present application formed by self-assembly of triblock copolymers may have lower critical gelation concentrations than gels formed by in situ polymerization of monomers with homopolymers branched from the ionic liquid. For example, gels formed by in situ polymerization generally require a polymer for gel formation from about 10 wt% to about 30 wt%. In contrast, the gels herein form self-assembled gels at less than 10 wt% triblock copolymer, generally from about 4 wt% to about 5 wt% triblock copolymer. Lower concentrations of the copolymer in the ion gel result in ionic conductivity of the ion gel that is closer to the ionic conductivity of the bulk ionic liquid. Therefore, lower concentrations of the copolymer in the ion gel may enable elevated ionic conductivity when compared to ion gels containing the same ionic liquid formed by in situ polymerization.

The A block may comprise any relatively nonpolar polymer. Preferred A blocks may comprise polystyrene (PS), polybutadiene, polyisoprene, polyethylene, polydimethylsiloxane, polyisobutylene and poly (N-isopropyl acrylamide) (PNIPAm).

Preferred block copolymers are poly (styrene-block-ethyleneoxide-block-styrene) (SOS), and poly (N-isopropylacrylamide-block-ethyleneoxide-block-N-isopropyl acrylamide in non-thermo-reversible ion gels. ) (PNIPAm-PEO-PNIPAm).

The preferred molecular weight of the triblock copolymer is greater than about 10,000 g / mol, more preferably from about 14,000 g / mol to about 140,000 g / mol, and more preferably from about 30,000 g / mol to about 70,000 g / mol Can be. The ion gel may comprise any ionic liquid known in the art. Ionic liquids have a desirable resistance to block ionic conductivity, capacitance, and electrical breakdown (i.e., a window between the bias applied between positive and negative above a range in which the ionic liquid is electrically stable). And at least one of miscibility with the polymer system. For example, selecting an ionic liquid with higher ionic conductivity can reduce the polarization reaction time of the gel with respect to the applied electric field. Choosing an ionic liquid with higher ionic conductivity can also increase the capacitance of an ion gel of a given thickness relative to ionic liquids of the same thickness with lower ionic conductivity.

Ionic liquids in which the ionic conductivity varies more than two orders are known, and other ionic liquids can be synthesized to have smaller or greater ionic conductivity. For example, the ionic conductivity of 1-ethyl-3-methylimidazolium n-octylsulfate ([EMIM] [OctSO ₄ ]) is about 0.66 mS / cm and 1,3-dimethylimidazolium fluorohydro The ionic conductivity of genate is about 110 mS / cm. Therefore, the ion conductivity of the ion gel can be customized over a wide range of values simply through the selection of an appropriate ionic liquid.

Any ionic liquid known in the art can be used in the ion gel herein without particular limitation. For example, the ionic liquid is 1-ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) imide ([EMIM] [TFSI]), 1-butyl-3-methylimidazolium hexa Fluorophosphate ([BMIM] [PF ₆ ]), 1-ethyl-3-methylimidazolium n-octylsulfate ([EMIM] [OctSO ₄ ]), and combinations thereof. However, the present invention is not limited thereto.

In another embodiment, the ion gel may also be formed by a copolymer of pentablock or more.

1 is a flow chart illustrating a method of preparing a polymer gel according to an embodiment of the present application. First, a block copolymer is synthesized (102). For the triblock copolymer, the synthesis may include living anionic polymerization, living cationic polymerization, controlled radical polymerization, RAFT (reversible addition / fragmentation transition, Appropriate controlled polymerization synthesis methods are followed, such as Reversible Addition / Fragmentation Transfer), ATRP (Atom Transfer Radical Polymerization), NMP (Nitoxide Mediated Polymerization), and the like.

The block copolymer is then added 104 to the ionic liquid. In one embodiment, the block copolymer is added in an ionic liquid at room temperature with a co-solvent. For example, poly (styrene-block-ethyleneoxide-block-styrene) can be added to [BMIM] [PF6] with methylene chloride. In other embodiments, the block copolymer can be added directly to the ionic liquid without the use of additional solvent. In another embodiment, the copolymer can be added to the ionic liquid at elevated temperature to form an ionic solution. Regardless of the method of adding the copolymer to the ionic liquid, the mixture may be stirred for a sufficient time to form an essentially homogeneous mixture (eg, about 1 to about 24 hours).

Once the homogeneous mixture is formed, the gel is left to form (106). This can occur by changing the temperature of the block copolymer when it is initially added at a temperature that forms a solution in the ionic liquid. In another embodiment, the gel can be formed by simply ending the stirring of the mixture, or by evaporating the cosolvent.

2 is a flow chart illustrating an exemplary method of treating a thermoreversible ion gel. First, an ion gel is provided (202). The ion gel is then heated above UCST to form an ionic solution (204).

In another embodiment of the method, the ionic liquid is first heated above UCST and the block copolymer is added to the heated ionic liquid. In this embodiment, the block copolymer solution in the ionic liquid is formed directly.

The liquid solution may then be processed by a process, such as aerosol jet printing, inkjet printing, gravure printing, screen printing, flexographic printing, other methods of printing, coating methods, and the like (206).

Once the liquid solution has been subjected to the desired treatment, the liquid solution is cooled (208) below the upper critical dissolution temperature to form an ion gel.

The ion gels of the present disclosure can find a wide range of applications in many industries, including, for example, the electronics industry. As one application of the electronics industry, the use of a gel of ions herein as an electronic insulating layer in transistors will be described in more detail below. Although the following description mainly concerns transistors, the present application is not limited to only transistors. For example, the iongels herein can also find use in other electronic components, such as capacitors. For example, integrated circuits comprising transistors and capacitors, including iongel electronic insulators, can provide improved performance compared to any conventional device, and can also provide manufacturing or process advantages.

A typical transistor includes a semiconductor layer connected to a source electrode and a drain electrode, an electrically insulating layer over the semiconductor layer, a gate electrode over the insulating layer, and ends of the gate electrode align with edges of the source and drain electrodes.

The electronic insulating layer used in the transistor has a high dielectric constant, which is generally desirable to allow the insulating layer to have a high capacitance value at a small thickness. High capacitance allows high current flow in the semiconductor layer between the source and drain electrodes when a voltage above a turn-on voltage is applied to the gate electrode. It is also desirable for the electronic insulating layer to have a fast response time to the applied gate voltage so that the transistor can be switched from the off state to the on state and from the on state to the off state, preferably within a short time.

As mentioned above, the ion gel herein provides a relatively high ionic conductivity, which results in high polarization of the ion gel. As described in more detail below, the high polarization rate leads to high capacitance when the ion gel is used as an insulator layer in the transistor. The high ion conductivity of the ion gel can also lead to a relatively fast reaction time for the applied gate voltage.

3 is a cross-sectional view of a thin film transistor (TFT) according to an embodiment of the present disclosure, and FIG. 4 is a flowchart illustrating a method of manufacturing the TFT of FIG. 3. 3 and 4, the TFT 300 includes a substrate 302 and a carbon nanostructure semiconductor layer 304 deposited on the substrate 302. The TFT 300 also includes a source electrode 306 and a drain electrode 308 attached to the semiconductor layer 304. The source electrode 306 and the drain electrode 308 are connected to opposite terminals of the common voltage source (V _SD ) 314. The semiconductor layer 304, the source electrode 306 and the drain electrode 308 are partially or completely covered by the ion gel layer 310. Finally, the gate electrode 312 connected to the second voltage source 316 is located on the ion gel layer 310.

The source electrode 306 and the drain electrode 308 and the gate electrode 312 may comprise any suitable conductive material, including gold, silver, copper, conductive alloys, conductive polymers, and the like. In one embodiment, the gate electrode 312 may be supported by a polyester film placed on the ion gel layer 310.

The substrate 302 may include, for example, a polymer, or a mixture of polymers, fibers, or other flexible materials. In one embodiment, the substrate 302 may be a flexible transparent substrate, such a flexible transparent substrate can be used by a person skilled in the art to choose a material known in the art, non-limiting example, polyethylene terephthalate (Polyethylene terephthalate (PET), polycarbonate PC, polyethersulfone (PES), polyimide, polyacrylate, polyester, polyvinyl, polycarbonate, polyethylene, or polyethylene naphthalate PEN It may be, but is not limited thereto.

 Flexible substrates are generally preferred, as the transistors described herein can be particularly useful for forming flexible circuits on flexible substrates, such as those well adapted to production through processes including, for example, inkjet printing.

The semiconductor layer 304 may include carbon nanostructures, and the carbon nanostructures may include graphene, fullerenes, carbon nanotubes, carbon nanofibers, carbon nanowires, carbon nanocones, and the like. In one embodiment, the carbon nanostructure may be used to transfer or grow carbon nanotubes. The carbon nanostructure is a method of transferring or growing carbon nanotubes can be appropriately performed by those skilled in the art using methods known in the art. In another embodiment, the carbon nanostructures may include graphene, which graphene is formed by chemical vapor deposition on a metal catalyst layer or transferred onto a substrate or directly by the method described above. It may be grown, but is not limited thereto. For example, the metal catalyst layer may be a thin film or a thick film, the metal catalyst layer is Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Rh, Si, Ta, Ti, W, U , V, Zr, Fe, brass (brass), bronze (bronze), stainless steel (stainless steel), may include one or more metals or alloys thereof selected from the group consisting of, and combinations thereof, but is not limited thereto. It doesn't happen. The chemical vapor deposition method may be carried out at atmospheric pressure or low pressure, may be carried out using a plasma, it can be used for all the graphene manufacturing method using a chemical vapor deposition method known in the art.

Subsequently, the semiconductor 304 may be etched to form a desired pattern. This can be done using lithography and etching. Here, the "desired pattern" may be, for example, in the form of a conductive pattern constituting a TFT or in the form of a conductive pattern constituting a chip formed on a chip on substrate, but is not limited thereto. It is not.

Specifically, for example, first, a photoresist layer is formed on the semiconductor layer 304, and then the photoresist layer is exposed and developed through a mask in which the set pattern is formed to correspond to the set pattern. A photoresist pattern is formed. In this case, the photoresist pattern exposes a portion of the semiconductor layer 304 to be etched. Next, using the photoresist pattern as a mask, the semiconductor layer 304 exposed through the photoresist pattern is etched to form a desired pattern including the semiconductor layer 304 on the substrate 302. Thereafter, the photoresist pattern is removed from the mask layer using an ashing process or a lift off process. On the other hand, the photoresist pattern may not be removed if necessary.

The ion gel layer 310 includes any ion gel described above and may include any useful ion gel. For example, the non-thermally reversible ion gel may comprise SOS / [EMIM] [TFSI], SOS / [BMIM] [PF ₆ ] and SOS / [EMIM] [OctSO ₄ ]. The ion gel layer 310 also includes, for example, PNIPAm-PEO-PNIPAm / [EMIM] [TFSI], PNIPAm-PS-PEO-PS-PNIPAm / [EMIM] [TFSI] or other thermoreversible ion gels. can do.

As shown in FIG. 3, voltage application to the gate electrode 312 induces an electric field in the ion gel layer 310. In one embodiment, a negatively applied voltage induces an electric field that causes polarization of the ion gel layer 310 with cations attracted to the gate electrode and anions in the ionic liquid repelled from the gate electrode. . Polarization of the ion gel layer 310 induces charge build-up of negative carriers near the interface of the semiconductor layer 304 and the ion gel layer 310, similar to the electrostatic effect of conventional dielectric insulator layers.

In contrast, the positive voltage applied to the gate electrode 312 causes accumulation of positive charges in the ion gel layer 310 at the interface between the ion gel layer 310 and the semiconductor layer 304, and the adjacent interface of the semiconductor layer 304. Induces the result of the accumulation of negative charge in the region.

High ionic conductivity then provides a high polarization rate and is desirable to result in a large amount of charge accumulation in the adjacent interface region of semiconductor layer 304 for a given voltage. As noted above, the self-assembled ion gels of the present disclosure provide very elevated ionic conductivity compared to conventional polymer electrolytes. High ion conductivity is also desirable to provide elevated switching speeds for transistors. The switching speed is effectively limited by the time required to accumulate and / or dissipate charge at the interface of the ion gel layer 310 and the semiconductor layer 304.

The switching speeds achieved by transistors comprising ion gels made by the present application vary, but are generally significantly higher than transistors using polymer electrolytes. For example, a transistor using an ion gel layer 310 containing SOS / [BMIM] [PF ₆ ] ion gel may operate at a switching speed of 100 Hz or higher. Higher switching speeds can be achieved using other ion gels that are more ionically conductive. The switching speed can be achieved by using ionic conductivity, such as using block copolymers having larger ion conductive ionic liquids, lower concentrations of block copolymers, higher operating temperatures, lower T _g and B blocks with faster partial dynamics. Can be increased by any method of increasing. The switching speed may also depend on the size of the device, including channel width and length, ion gel layer 310 thickness, and the like.

The amount of charge accumulation in the adjacent interface region of semiconductor layer 304 is directly related to the source-drain voltage needed to produce a given current flow in semiconductor layer 304. Therefore, the high ion conductivity of the ion gel layer 310 lowers the operating voltage of the transistor, presumably lowering the power consumption of the device using the transistor comprising the ion gel layer 310 of the present application. This may be particularly advantageous for portable electronic devices that often rely on batteries with limited capacitance.

4 is a flowchart illustrating a method of manufacturing a TFT of FIG. 3. First, the substrate 302 is prepared (402). As noted above, the substrate 302 may comprise a flexible material, including, for example, a polymer, or a mixture of polymers, fibers, and the like. Flexible substrates are generally preferred, as the transistors described in the present disclosure are particularly well suited for production through processes that include inkjet printing, which may be particularly useful for forming flexible circuits on flexible substrates. The flexible substrate is selected from the group consisting of, for example, polyester, polyvinyl, polycarbonate, polyethylene, polyacetate, polyimide, polyethersulfone, polyacrylate, polyethylenenaphthalate, polyethylene terephthalate, and combinations thereof. Can be one. In one embodiment, the substrate may be large enough to accommodate enough TFTs 300 to form a circuit, such as billions, or more TFTs 300.

Subsequently, a semiconductor layer 304 is deposited on the substrate (404). The semiconductor layer 304 may include carbon nanostructures, and the carbon nanostructures may include graphene, fullerenes, carbon nanotubes, carbon nanofibers, carbon nanowires, carbon nanocones, and the like. Carbon nanostructures such as graphene can be grown on the metal catalyst layer, the metal catalyst layer, for example, one selected from the group consisting of Cu, Fe, Ni, Co, Pt, Ir, Pd and Ru It may be to include a metal or an alloy thereof, but is not limited thereto. The thickness of the metal catalyst layer is not particularly limited and may be appropriately selected by those skilled in the art in a range suitable for the characteristics of the desired electric and electronic device. Examples of the metal catalyst layer include, but are not limited to, chemical vapor deposition (CVD), sputtering, e-beam evaporation, sol-gel combustion of a metal mixture, and metal precursors. It can be formed by using the ion exchange precipitation method, electroplating, electroless plating (Electroless Plating) used.

Specifically, for example, the graphene is grown on the metal catalyst layer of the pattern by using a chemical vapor deposition method. Metal catalyst layer film by a thermal chemical vapor deposition method that decomposes a precursor containing carbon such as acetylene (C ₂ H ₂ ) or methane (CH ₄ ) using thermal energy or a plasma chemical vapor deposition method that decomposes using plasma energy. Selectively grow graphene. In addition, as a non-limiting example, graphene may be formed using an arc discharge, laser vaporization, electrolysis, flame synthesis, or the like.

A source electrode 306 and a drain electrode 308 are then deposited over the semiconductor layer 304 (406). The source electrode 306 and the drain electrode 308 include a metal or a conductive polymer and may be formed using materials and methods used in the art. The metal source electrode 306 and the drain electrode 308 are, for example, Al doped zinc oxide (AZO), indium tin oxide (ITO), cobalt (Co), iron (Fe), nickel (Ni), chromium, and the like. (Cr), gold (Au), silver (Ag), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), tungsten (W), ruthenium (Ru), palladium (Pd) and cadmium It can be formed from one or more selected from the group consisting of (Cd). In addition, the conductive polymer is, for example, polypyrrole, polythiophene, poly (3-alkylthiophene), polyaniline, polyphenylene sulfide, polyfuran, polyiso-thianaphthene, poly (p-petylenevinylene, Poly (p-phenylene), poly (3,4-ethylenedioxythiophene), poly (ethylene glycol) diacrylate, 2-hydroxy-2-methylpropiophenone and combinations thereof The source electrode 306 and the drain electrode 308 can be formed.

They form the source electrode 306 and the drain electrode 308 by chemical vapor deposition (CVD), physical vapor deposition (PVD) or printing methods. The chemical vapor deposition may be one of metal organic chemical vapor deposition (MOCVD), atmospheric chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma accelerated chemical vapor deposition (PECVD) and atomic layer deposition (ALD). After the source electrode 306 and the drain electrode 308 are formed, the source electrode 306 and the drain electrode 308 which are in electrical contact with a semiconductor layer including the carbon nanostructure by patterning, for example, by a lithography process. Can be formed.

Subsequently, the ion gel layer 310 is formed on the region of the semiconductor layer 304 including the source electrode 306 and the drain electrode 308 (408). The ion gel layer 310 may partially or completely cover the source electrode 306 and the drain electrode 308, or substantially cover the entire semiconductor layer 304 between the source electrode 306 and the drain electrode 308. Can be covered.

The ion gel layer 310 may be deposited through any useful process and may be deposited in gel or liquid form. When the ion gel layer 310 is deposited in a gel form, the ion gel layer 310 may be simply applied on the semiconductor layer 310 by using pressure. The ion gel layer 310 may be deposited in a liquid form. In one embodiment, the ion gel including the thermoreversible ion gel layer 310 may be deposited in liquid form by heating above its upper limit critical dissolution temperature (UCST). Then, the ion gel layer 310 can be cooled to below the UCST causing gelation. In another embodiment that includes a non-thermally reversible ion gel layer 310, the block copolymer and the ionic liquid are dissolved in a solvent and a cosolvent, deposited onto the TFT, and the cosolvent is removed from the ion gel layer 310. Can be evaporated. In addition, the ion gel layer 310 may include a polymer having a characteristic of being cured by ultraviolet rays and gelled, and may include a process of irradiating ultraviolet rays and curing the ion gel after deposition.

Depositing the ion gel layer 310 in liquid form may be acceptable, for example, using a continuous deposition process that includes printing. Any suitable method of printing may be used, including, for example, aerosol jet printing, inkjet printing, rotogravure printing, screen printing, flexographic printing coating methods, and the like. In addition, the ion gel layer 310 may include patterning using a printing method using a nozzle, but is not limited thereto.

Finally, the gate electrode 312 is deposited on the ion gel layer 310 (410). The gate electrode 312 may be deposited using any suitable process, including any deposition method described with respect to the source electrode 306 and the drain electrode 308. Moreover, gate electrode 312 may optionally be supported by a film, such as, for example, a polymer film. Then, the polymer film may be attached to the ion gel layer 310 by aligning the gate electrode 312 with the TFT 300.

5 is a cross-sectional view illustrating an exemplary TFT in another embodiment of the present application, and FIG. 6 is a flowchart illustrating a method of manufacturing the TFT of FIG. 5. TFT 500 of FIG. 5 is similar to TFT 300 of FIG. However, source electrode 506 and drain electrode 508 are positioned adjacent substrate 502, and carbon nanostructure semiconductor layer 504 is formed between source electrode 506 and drain electrode 508. An ion gel layer 510 is formed on the source electrode 506, the drain electrode 508, and the carbon nanostructure semiconductor layer 504, and a gate electrode 512 is formed on the ion gel layer 510. The TFT 500 is manufactured. The structure of the TFT 500 allows the source electrode 506 and the drain electrode 508 to be deposited prior to the deposition of the semiconductor layer 504 on the substrate 502, thereby providing an advantage in the processing process. For example, the deposition of the source electrode 506 and the drain electrode 508 prior to the deposition process of the semiconductor layer 504 may be any, such as the high temperature used to deposit the source electrode 506 and the drain electrode 508. The semiconductor layer 504 is protected from extreme process conditions. The entire manufacturing method 600 then includes providing 602 a substrate 502 and depositing a source electrode 506 and a drain electrode 508 on the substrate 502 (604). Subsequently, a semiconductor layer 504 is deposited on the substrate 502, the source electrode 506 and the drain electrode 508 using any of the methods described above with respect to FIG. 4. The semiconductor layer 504 completely covers at least a portion of the substrate 502, the source electrode 506, and the drain electrode 508. The region of the semiconductor layer 504 between the source electrode 506 and the drain electrode 508 defines the channel length and channel width of the TFT 500. Then, an ion gel layer 510 is formed on the semiconductor layer 504 (608). The ion gel layer 510 can be deposited using any of the process techniques described above, extending at least the length and width of the channel. Finally, a gate electrode is deposited on the ion gel layer 510 (610).

7 is a cross-sectional view illustrating a TFT in another embodiment of the present application, and FIG. 8 is a flowchart illustrating a method of manufacturing the TFT of FIG. 7. 7 and 8, a substrate 702 is provided 802, and a gate electrode 712 is deposited 804 on the substrate 702. An ion gel layer 710 is then deposited over at least a portion of the gate electrode 712 and the substrate 702 (806). A source electrode 706 and a drain electrode 708 are deposited 808 on the ion gel layer 710. Finally, a carbon nanostructure semiconductor layer 704 is deposited 810 on at least a portion of the ion gel layer 710 extending between the source electrode 706 and the drain electrode 708. The source electrode 706 and drain electrode 708 is a common voltage source 714 is coupled to (common voltage source, V _SD), a gate electrode 712 is a voltage source (716) (voltage source, V _G) Connected.

As is common with conventional transistors, FIG. 7 shows that the gate electrode 712 need not be aligned in line with the channel between the source electrode 706 and the drain electrode 708. The high polarization of the ion gel layer 710 allows the ion gel layer 710 to be strongly polarized such that the interface of the ion gel layer 710 and the semiconductor layer 704 can be polarized regardless of the exact arrangement of the gate electrode 712. will be. This may reduce the number of defective TFTs 700, or may allow for reduced manufacturing precision to allow for increased throughput during the manufacture of TFTs 700.

9 is a cross-sectional view illustrating a TFT in another embodiment of the present application. As shown in Fig. 9, the TFT 900 configuration can allow an increase in the speed of the manufacturing process. In particular, the TFT 900 is characterized by a gate electrode 912, a source electrode 906, and a drain electrode 908 located on the surface of the substrate 902. The carbon nanostructure semiconductor layer 904 is located on the substrate 902 and partially or completely covers the source electrode 906 and the drain electrode 908. At least a portion of the substrate 902 on which the gate electrode 912, the source electrode 906, the drain electrode 908, and the semiconductor layer 904 are located is partially or completely covered by the ion gel layer 910. The source electrode 906 and the drain electrode 908 are connected to a common voltage source 914 (V _SD ), and the gate electrode 912 is connected to a separate voltage source 916 (V _G ). .

10 is a flowchart illustrating a method of manufacturing the TFT of FIG. 9. Referring to FIG. 10, first, a substrate 902 is provided (1002). A source electrode 906, a drain electrode 908, and a gate electrode 912 are then deposited on the substrate 902 (1004). Electrode deposition may be via conventional methods, such as, for example, thermal evaporation through a stencil, or the electrodes 906, 908, 912 may be printed on the substrate 902. Subsequently, a semiconductor layer 904 is deposited (1006) on the substrate 902 and over at least a portion of the source electrode 906 and the drain electrode 908, for example, spin coating, printing, solvent Deposition is carried out using any useful method including evaporation and the like. Finally, the ion gel layer 910 includes at least a portion of the semiconductor layer 904 between at least a portion of the gate electrode 912 and the source electrode 906 and the drain electrode 908 over the area of the substrate 902. Deposit (1008).

Depositing the source electrode 906, the drain electrode 908 and the gate electrode 912 in the same process step can simplify the fabrication of the TFT 900. For example, this geometry allows the deposition process of all three electrodes prior to the deposition of the ion gel layer and also the deposition of all three electrodes 906, 908, 912. This may protect the ion gel layer 910 used to deposit the electrodes 906, 908, 912 from any process parameter (eg, high temperature), which may be undesirable.

One of the TFTs described above can be used to form an integrated circuit. Integrated circuits may include tens, hundreds, thousands or more TFTs, and may also include other components such as, for example, resistors, capacitors, LEDs, other transistors, and the like. The TFTs may be deposited on the same substrate and may be on the same plane or in multiple layers on the substrate. Individual TFTs can be formed by any of the present methods described herein.

Hereinafter, the present invention will be described in more detail with reference to Examples, but the scope of the present invention is not limited by these Examples.

Low voltage actuated graphene FET arrays were fabricated on poly (ethylene terephthalate) (PET) plastic substrates using ion gels as gate insulators. The ion gel is formed comprising a room temperature ionic liquid and a gelating triblock copolymer, which exhibits a very high capacity of 5.17 μF / cm ² . The high capacity of the ion gel gate insulator in graphene FETs enables both high on-current and low voltage operation. In addition, graphene FETs with iongel gates fabricated on plastic substrates exhibit very good mechanical flexibility.

As a comparative example, typical bottom-gated graphene FETs were fabricated on SiO ₂ / Si wafers. As an example of the present application, a top-gated device having an ion gel gate insulator was constructed to measure the performance of the graphene film and to compare the properties of SiO ₂ and the ion gel insulator. 11A shows the transfer characteristics (I _D -V _G ) of graphene FETs fabricated on SiO ₂ insulators (t-300 nm). Channel width W and length L were 10 m and 20 m, respectively. Graphene films were deposited by chemical vapor deposition (CVD) methods; Hall and electron mobility were calculated from a linear manner of transfer characteristics using the following equation:

;

;

Where C _i is the specific capacitance of the insulator, V _th is the threshold voltage, and μ is the field effect mobility. Calculated hole and electron mobility is V _D = -1 V, respectively, 828 ± 58 and 189 ± 42 cm ² / (V? S). In addition, the electron conduction of graphene FETs was quite weak, and the Dirac point was about +40 V. Such asymmetry in the mobility of the two carriers and the displacement at the Dirac point can be explained by the different scattering cross-sectional areas for electrons and holes and the electric field created by the impurities charged on the SiO ₂ substrate, respectively. FIG. 11B is a graph showing the output characteristics I _D -V _D of graphene FETs having SiO ₂ -gates at five different gate voltages V _G. The device showed a clear increase in conductivity induced by gate voltage and perfect linear behavior due to the metal / zero band gap semiconductor junction.

The gate insulator is a key element of the graphene device because of its important role in determining the operating voltage range. Although HfO ₂ or Al ₂ O ₃ formed by atomic layer deposition (ALD) is a natural choice, thermal limitations of plastic substrates have hindered the use of ALD processes. Ion gel gate insulators with high capacitances that can be formed at low temperatures may be suitable as solid gate insulators in graphene transistors. The ion gel provided a specific capacitance of 5.17 μF / cm ² at 10 Hz which is greater than the typical value for a 300 nm thick SiO ₂ insulator. This surprising high capacitance of the ion gel is due to the formation of an electric double layer only nanometers thick at the ion gel / graphene and ion gel / gate electrode interfaces under an electric field. FIG. 11C is a graph showing the transfer characteristics of an upper gate graphene transistor fabricated using an ion gel gate insulator at five different V _D. A characteristic V-type bipolar r behavior has been identified, where the positive and negative V _G regions represent electron and hole transport, respectively. Mean hole and electron mobility were 320 ± 35 and 135 ± 26 cm ² / (V? S) at V _D = −1 V, respectively. This decrease in carrier mobility of the graphene transistor with the ion gel gate may be due to two effects. One is a polymer residue remaining on the graphene surface after transfer printing of graphene on the substrate. Another is the surface roughness of the graphene film, where the graphene / iongel interface is rougher than the graphene / SiO ₂ interface. Moreover, compared to SiO ₂ gate insulators, the asymmetry factor between hole and electron conductivity was significantly reduced, and the Dirac point changed to almost zero because the counterion in the ion gel neutralized the charged impurities trapped on the SiO ₂ substrate. did. The output characteristics of the graphene transistor with ion gel gate in the device showed V _G and drain current modulation (FIG. 11D). At V _G = -4 V and V _D = -1 V, the drain current was about 2.4 mA. This is higher than transistors with SiO ₂ -gates (˜0.4 mA at V _G = -40 V and V _D = −1 V) and is a direct result of the large capacitance of the ion gel gate insulator.

The main advantage of graphene lies in its very good mechanical properties, which are essential for achieving flexible and stretchable electronics. To demonstrate such properties of graphene, graphene FET arrays with ion gel gates were fabricated on flexible poly (ethylene terephthalate) (PET) plastic sheets. 12 shows a flow chart of the fabrication steps of a graphene transistor array having an ion gel gate on the plastic substrate. In the first step, large area, high quality graphene films were grown on rectangular specimens of Cu foil (25 μm thick) as metal catalysts using chemical vapor deposition. Primarily single and bilayers of graphene were grown on the Cu foil. A poly (methyl methacrylate) (PMMA) polymer support was coated onto the graphene film formed on the Cu foil to transfer the graphene film from the Cu foil to the plastic substrate. The support attached to the foil was deposited with a wet etching solution to remove the metal layer. The film was then transferred by transfer printing to a PET sheet comprising a source electrode and a drain electrode (Cr / Au, 10 nm / 60 nm) formed by thermal deposition. The device pattern of the graphene film was formed by photolithography and reactive ion etching (RIE) with O ₂ plasma. Poly (styreneblock-methyl methacrylate-block-styrene) (PS-PMMA-PS) triblock copolymer and 1-ethyl-3-methylimidazolium bis (trifluoromethyl) for iongel gate insulator formation Sulfonyl) imide ([EMIM] [TFSI]) ionic liquids were dissolved in methylene chloride at a 0.7: 9.3: 90 ratio (w / w) and then drop-cast onto a graphene pattern with Au source and drain contacts. After solvent removal, an ion gel film was formed through the physical bonding of the PS blocks in the ionic liquid. The upper gate electrode (Au, 100 nm) was thermally evaporated through the shadow mask.

13A and 13B show the transfer and output characteristics of graphene FETs on PET and the flexibility of the device substrate obtained above. There was no difference in mobility and on-current compared to that produced on Si wafers. The device has a high on-current and operates at low voltage (-3 V) with a Dirac point of nearly zero. 13C is a graph showing the distribution of holes and electron mobility of graphene FET arrays (total-50 devices) on PET. Gaussian fitting shows hole and electron mobility of 203 ± 57 and 91 ± 50 cm ² / V · s, respectively, at a drain bias of −1 V. All measurements were performed under ambient conditions.

Mechanical flexibility and robustness are important properties for the application of graphene FETs in flexible electronics. Symmetric bending test was performed on the graphene FET array. 13D shows the change in the effective carrier mobility, normalized to the value of the graphene FETs under unbending conditions. Only 20% change was observed at μ / μ _o as the bending radius varied from 6 to 0.6 cm.

In summary, graphene films bonded to ion gel insulators provide an important route to mechanically flexible, high performance and low voltage graphene devices. Graphene technology can create opportunities for devices that require specific form factors such as mechanical flexibility or stretchability.

The high performance low voltage graphene field effect transistor array utilizes solution-processable to fabricate high capacity ion gel gate insulators on flexible polymer substrates. The high capacity of the ion gel resulting from the formation of the electrical double layer under the application of gate voltage resulted in high on-current and low voltage operation of 3 V or less. Graphene FETs fabricated on plastic substrates exhibit hole and electron mobility of 203 ± 57 and 91 ± 50 cm ² / (V s), respectively, at a drain bias of −1 V. Moreover, ion gel gate graphene FETs on plastic substrates exhibited excellent mechanical flexibility. This method represents an important step towards flexible and stretchable electronics in graphene applications.

14 is a view showing a graphene FET manufacturing process using a graphene pattern according to another embodiment of the present application.

First, in the photopatterning process, poly (ethyleneglycol) diacrylate (PEG-DA), monomer, 2-hydroxy-2-methylpropiophenone (HOMPP) initiator, and 1-ethyl-3-methylimidazolium An ion gel ink comprising bis (trifluoromethylsulfonyl) imide ([EMIM] [TFSI]) ionic liquid was added dropwise onto the patterned graphene substrate. A square patterned Cr mask was placed on the ion gel layer. UV (λ = 365 nm, 100 mW / cm ² ) was exposed for 5 seconds. By the UV exposure, the initiator generates radicals and reacts with acrylates in the oligomer molecules. The polymerization of acrylate end groups in each oligomer molecule formed chemically cross-linked ion gels. The unexposed ionic liquid solution was washed with chloroform. To form the gate electrode, the ion gel patterned substrate was placed on a PEDOT: PSS thin film.

In an aerosol jet printing process, an ion gel ink comprising poly (styrene-methylmethacrylate-styrene) (PS-PMMA-PS) and [EMIM] [TFSI] in ethyl acetate was printed onto the patterned graphene. By solvent evaporation, the PS-PMMA-PS triblock copolymer in the [EMIM] [TFSI] ionic liquid formed a physical gel through non-covalent bonding of the PS moiety that was immiscible with the ionic liquid. In the last step, a PEDOT: PSS gate electrode was printed on the channel. The conductivity of the printed PEDOT: PSS was measured at 100 S / cm.

15A shows a photograph of a transparent graphene FET array fabricated by the photopatterning process. The graphene channel was defined as the area under the ion gel gate insulator. Its channel width W and length L were 100 and 200 µm, respectively. As shown in FIG. 15B, the light transparency of the laminated film was shown in the visible to NIR spectral range. In order to exclude the density effect of the graphene FETs, the layer was not patterned. At 550 nm, the transparency of PET was weakly wavelength dependent, about 88%. The transparency was reduced by about 3% after graphene transfer onto PET. The ion gel, graphene film and PET in combination had ˜80% light transparency.

Typical drain current (I _D ) -drain voltage (V _D ) characteristics of the transparent graphene FETs are shown in FIG. 15C. The device showed a clear increase in conductivity induced by gate voltage and complete linear behavior. The drain current at V _G = -4 V and V _D = -1 V was about 2.0 mA. The very large capacitance of the ion gel gate insulators enabled low low voltage and high current operation. 15D shows I _D at different V _D as a function of gate voltage V _G. The device has a high on-current and operates at low voltages below 3 V and has a Dirac point of nearly zero. Clear bipolar behavior can be observed in the gate dependence of the I _D , where the positive and negative V _G regions represent electron and hole transport, respectively.

The negative gate bias attracted positive [EMIM] ions at the gate electrode and formed an electric double layer (EDL) at the ion gel / gate interface. On the other hand, negative [TFSI] ions were separated at the counter ion gel / graphene interface. The two EDLs formed at the gate / ion gel and the ion gel / graphene interface with a charge-neutral diffusion layer between them. Because of the negligible diffusion layer capacitance, the interfacial capacitance of the ion gel can be modeled as a series combination of electric double layer capacitance (CEDL) and quantum capacitance (Cq) of the graphene. CEDL was measured to be 7.29 μF / cm ² at 10 Hz, which was not affected by gate potential. C _q is a function of gate potential or charge density. The lowered potential on the two capacitors is given by:

Where h is a reduced Planck 'constant, ν _F is a Fermi velocity (1.1 × 10 6 m / s), e is an electron charge value, and n is the charge density. Based on this equation, as shown on the right side of FIG. 15D, V _G is converted to n and the conductivity is expressed as a function of charge density. Curves obtained at three different drain voltages overlap well in the margin of error. From the slope of the linear scheme, carrier mobility was calculated using μ = (dσ / d n ) / e . FIG. 15E shows the distribution of holes and electron mobility of 50 graphene FETs printed in different batches. Gaussian fittings exhibit hole and electron mobility of 384 ± 83 cm ² / Vs and 159 ± 64 cm ² / Vs, respectively.

16A shows a photograph of a transparent graphene FET array made by an aerosol jet printing process. The device has a channel width of 10 μm and a length of 150 μm. 16B shows charge density-conductivity characteristics at three different drain voltages. The conductivity reached a minimum at the charge neutral point and increased rapidly with the gate potential on both sides. The C _EDL of the PS-PMMA-PS / [EMIM] [TFSI] substrate-ion gel was determined to be 5.17 μF / cm ² at 10 Hz. Hall and electron mobility were calculated to be 285 ± 39 cm ² / Vs and 128 ± 30 cm ² / Vs, respectively. The slight decrease in carrier mobility of the graphene FETs based on aerosol jet-printed ion gels may be due to residual ethyl acetate used to dissolve PS-PMMA-PS and [EMIM] [TFSI]. Although the photo-patternable ion gel system (mentioned above) does not use a solvent, the residual ethyl acetate molecules at the graphene / ion gel interface can serve as charge trap sites. In addition, the output characteristic is shown as the inset of FIG. 16B.

The mechanical flexibility and robustness of the transparent graphene FETs were measured by performing front and back bending tests. FIG. 16C shows the change in effective hole / electron mobility normalized by hole / electron mobility in the unbent state (μ / μ ₀ ). Negative and positive stresses correspond to tension and compression, respectively. In the range of stress of ± 2%, only 20% change in both hole and electron mobility was observed. A fatigue test was also run on the graphene FETs. FIG. 16D shows the μ / μ ₀ change after several hundred bending cycles causing the tensile stress to vary between 0% and 2% in the device. Only 20% change was observed at μ / μ ₀ after 250 cycles. Here, an array of graphene FETs all printed on plastics was prepared (FIG. 17A). PEDOT: PSS source / drain electrodes were printed onto the patterned graphene channels using aerosol jet printing (W and L were 20 and 100 μm). The ion gel and the gate electrode were printed in the same manner as described above. Compared with the graphene source / drain electrode based, there was no significant difference in the mobility. The hole and electron mobility were measured at 255 ± 48 cm ² / Vs and 135 ± 27 cm ² / Vs, respectively.

It will be understood by those of ordinary skill in the art that the foregoing description of the embodiments is for illustrative purposes and that those skilled in the art can easily modify the invention without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

300: TFT 302: substrate
304: carbon nanostructure semiconductor layer 306: source electrode
308: drain electrode 310: ion gel layer
312: gate electrode 314: common voltage source
500: TFT 502: substrate
504: carbon nanostructure semiconductor layer 506: source electrode
508: drain electrode 510: ion gel layer
700: TFT 702: substrate
704 carbon nanostructure semiconductor layer 706 source electrode
708: drain electrode 710: ion gel layer
712: gate electrode 714: common voltage source
716: voltage source 900: TFT
902: substrate 904: carbon nanostructure semiconducting layer
906: source electrode 908: drain electrode
910: ion gel layer 912: gate electrode
914 common voltage source

Claims (1)

A source electrode and a drain electrode;
A semiconductor layer including carbon nanostructures disposed to form a channel region between the source electrode and the drain electrode;
A gate electrode; And
An ion gel layer forming an insulator layer between the channel region and the gate electrode between the semiconductor layer including the carbon nanostructure and the gate electrode;
A flexible field effect transistor comprising a.

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