KR20120119893A - Duty cycle correction circuit - Google Patents

Abstract

 A duty cycle correction circuit (DCC) for correcting and outputting a duty ratio of a clock signal. The method relates to a duty cycle correction circuit for generating a corrected clock signal by receiving a control signal and correcting the duty ratio of an input clock signal. A duty cycle correction circuit having a duty cycle control unit for detecting a duty ratio of the correction clock signal and outputting a detection signal, and a control signal generation unit for generating the control signal in response to the detection signal; Is provided.

Description

Duty cycle correction circuit {DUTY CYCLE CORRECTION CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit design technology, and more particularly, to a duty cycle correction circuit (DCC) for correcting and outputting a duty rate of a clock signal.

Generally, semiconductor devices including DDR SDRAM (Double Data Rate Synchronous DRAM) have various internal circuits for various operations. Among these internal circuits, duty cycle correction circuits can receive a clock signal and correct it to a desired duty ratio. (Duty Cycle Correction Circuit, DCC). The duty cycle correction circuit receives, for example, an internal clock signal output from a delay locked loop (DLL) and a phase locked loop (PLL) provided in a semiconductor device, and sets a duty ratio of 50:50. An internal clock signal having a duty ratio of 50:50 serves as a basis for stable circuit operation of a semiconductor device.

On the other hand, in general, the duty cycle correction circuit occupies a relatively large circuit area, has a very complicated structure, and has a very large current consumption. Therefore, efforts are recently underway to improve such a problem of the duty cycle correction circuit.

The present invention has been proposed to solve the above problems, and to provide a circuit that simplifies the internal configuration of the duty cycle correction circuit.

A duty cycle correction circuit according to an aspect of the present invention for achieving the above object, the duty cycle control unit for generating a correction clock signal by correcting the duty ratio of the input clock signal by receiving a control signal; A duty cycle detector for detecting a duty ratio of the corrected clock signal and outputting a detection signal; And a control signal generator for generating the control signal in response to the detection signal.

A duty cycle detection circuit according to another aspect of the present invention for achieving the above object includes a first pulse detector for detecting a first logic level of the input clock signal; A second pulse detector for detecting a second logic level of the input clock signal; And a detection signal output unit configured to output a detection signal corresponding to the duty ratio of the input clock signal after the output signal of the second pulse detector is activated.

In particular, the detection signal output unit may include: an input unit configured to receive an output signal of the first pulse detector in response to an output signal of the second pulse detector; A latching unit for latching a signal transmitted through the input unit; And an output unit for outputting the output signal of the latching unit as the detection signal in response to the output signal of the second pulse detection unit.

A duty cycle control circuit according to another aspect of the present invention for achieving the above object includes a delay unit for delaying and outputting an input clock signal by a predetermined time; A clock signal output unit for outputting a corrected clock signal in response to the input clock signal and an output clock signal of the delay unit; And an adjusting unit for adjusting a transition time of the corrected clock signal in response to a control signal.

In particular, the adjuster may mix the input clock signal and the output clock signal of the delay unit during the delay time reflected by the delay unit.

According to yet another aspect of the present invention, there is provided a method of operating a duty cycle detection circuit, the method including: sequentially detecting first and second logic levels corresponding to one period of an input clock signal; And detecting a duty ratio of the input clock signal in response to a detection signal corresponding to the second logic level.

In particular, the determination value corresponding to the duty ratio of the input clock signal is output after the detection signal corresponding to the second logic level is activated.

The duty cycle correction circuit according to an exemplary embodiment of the present invention further simplifies the internal configuration, thereby speeding up the operation speed of the circuit, and minimizing the area and current consumption of the circuit.

The present invention reduces the area of the circuit by simplifying the configuration of the duty cycle correction circuit, thereby minimizing the size of the semiconductor chip including the same, increasing the operating speed, and minimizing the current consumption. You can get it.

In addition, the effect of obtaining a more accurate determination value in detecting the duty ratio can be obtained.

1 is a block diagram illustrating a duty cycle correction circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram for explaining the duty cycle detection unit 120 of FIG. 1.
3 is a circuit diagram illustrating the first pulse detector 210 of FIG. 2.
4 is a circuit diagram illustrating the detection signal output unit 230 of FIG. 2.
5 is a timing diagram for explaining the circuit operation of FIGS. 2 to 4;
6 is a circuit diagram illustrating the duty cycle control unit 110 of FIG. 1.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

1 is a block diagram illustrating a duty cycle correction circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the duty cycle correction circuit includes a duty cycle controller 110, a duty cycle detector 120, a control signal generator 130, and a clock output unit 140.

The duty cycle controller 110 receives the control signal CTR and feeds back the corrected duty ratio of the input clock signal CLK_IN and outputs it as the corrected clock signal CLK_CCD. As will be described later, the correction clock signal CLK_CCD at the beginning of the circuit operation is almost the same as the input clock signal CLK_IN, and the correction clock signal CLK_CCD may have a duty ratio of 50:50 after the duty cycle correction operation. .

The duty cycle detector 120 detects the duty ratio of the correction clock signal CLK_CCD as the output signal by the duty cycle controller 110 and outputs an up detection signal DET_UP and a down detection signal DET_DN. In other words, the up detection signal DET_UP is activated or the down detection signal DET_DN is activated according to the duty ratio of the correction clock signal CLK_CCD.

The control signal generator 130 generates a control signal CTR in response to the up detection signal DET_UP and the down detection signal DET_DN, and the generated control signal CTR is input to the duty cycle controller 110. do. Subsequently, the duty cycle controller 110 corrects the duty ratio of the input clock signal CLK_IN in response to the control signal CTR, and outputs the duty ratio as the correction clock signal CLK_CCD. Here, the control signal CTR may have various forms according to the design. If the control signal generator 130 performs a counting operation in response to the up detection signal DET_UP and the down detection signal DET_DN, When designed as a counter, the control signal CTR will be composed of a code consisting of a plurality of bits.

The clock output unit 140 generates an output clock signal CLK_OUT in response to the corrected clock signal CLK_CCD. Here, as the duty cycle correction operation is completed, the correction clock signal CLK_CCD has a duty ratio of 50:50, and the output clock signal CLK_OUT also has a desired duty ratio.

2 is a block diagram illustrating the duty cycle detector 120 of FIG. 1.

Referring to FIG. 2, the duty cycle detector 120 includes a first pulse detector 210, a second pulse detector 220, and a detection signal output unit 230.

The first pulse detector 210 detects a logic 'high' section of the correction clock signal CLK_CCD. The first pulse detector 210 receives the correction clock signal CLK_CCD and generates a first output signal OUT1. The second pulse detector 220 detects a logic 'low' period of the correction clock signal CLK_CCD. The second pulse detector 220 receives the inverted correction clock signal / CLK_CCD and generates a second output signal OUT2. Next, the detection signal output unit 230 outputs an up detection signal DET_UP and a down detection signal DET_DN corresponding to the duty ratio of the correction clock signal CLK_CCD after the second output signal OUT2 is activated. As will be described again later, the up detection signal DET_UP is activated when the duty ratio of the correction clock signal CLK_CCD is smaller than 50% (eg, 40:60), and the down detection signal DET_DN is configured to perform the correction clock signal CLK_CCD. It is activated when the duty ratio is greater than 50% (eg 60:40).

FIG. 3 is a circuit diagram illustrating the first pulse detector 210 of FIG. 2. For reference, the second pulse detector 220 may have a configuration similar to that of the first pulse detector 210, which will be described below, and receives the inverted correction clock signal / CLK_CCD instead of the correction clock signal CLK_CCD. The two output signals OTU2 are different.

Referring to FIG. 3, the first pulse detector 210 includes a discharge unit 310 and an output unit 320.

The discharge unit 310 is for discharging the charges charged in the first capacitor C1 in response to a logic 'high' section of the correction clock signal CLK_CCD. The discharge unit 310 may include a first inverter INV1 and a first PMOS transistor. P1, first and second NMOS transistors N1 and N2, and first capacitor C1 are provided. The output unit 320 is configured to activate the first output signal OUT1 to logic 'high' in response to the discharge amount of the first capacitor C1 and includes a second inverter INV2.

A brief circuit operation of the first and second pulse detectors 210 and 220 will be described again with reference to FIG. 5, but the first and second pulse detectors 210 and 220 may respond to the reset signal RST to be described later. Perform precharging operation. The first output signal OUT1 generated by the first pulse detector 210 may determine an activation time corresponding to a section in which the correction clock signal CLK_CCD maintains a logic 'high', and the second pulse detector 220 The second output signal OUT2 generated in the C1 is activated in response to a section in which the inversion correction clock signal / CLK_CCD maintains a logic 'high', that is, a section in which the correction clock signal CLK_CCD maintains a logic 'low'. The time point is determined.

4 is a circuit diagram illustrating the detection signal output unit 230 of FIG. 2.

Referring to FIG. 4, the detection signal output unit 230 may include an input unit 410 for receiving the first output signal OUT1 in response to the second output signal OUT2, and a signal transmitted through the input unit 410. A latching unit 420 for latching the output unit and an output unit for outputting the output signal of the latching unit 420 as an up detection signal DET_UP and a down detection signal DET_DN in response to the second output signal OUT2 ( 430. The input unit 410 may include a first transfer unit TG1 in which a PMOS transistor and an NMOS transistor are paired, and the latching unit 420 may include first and second inverters INV1 and INV2. The output unit 430 may include a second transfer unit TG2 outputting the up detection signal DET_UP and a third inverter INV3 outputting the down detection signal DET_DN.

Meanwhile, according to an exemplary embodiment of the present invention, a reset signal generator 440 is further provided to generate a reset signal RST in response to the reference clock signal CLK_REF. Here, the reset signal RST is a signal activated after the second output signal OUT2 is activated, and is output in synchronization with the reference clock signal CLK_REF having a predetermined frequency.

FIG. 5 is a timing diagram for describing the circuit operation of FIGS. 2 to 4.

2 to 5, first, the input clock signal CLK_IN is input to the duty cycle controller 110. Since no correction operation is reflected in the input clock signal CLK_IN before the duty cycle correction operation, the duty cycle controller 110 outputs a correction clock signal CLK_CCD which is almost the same as the input clock signal CLK_IN.

On the other hand, in the period where the reset signal RST is logic 'high', the first PMOS transistor P1 (see FIG. 3) of the first pulse detector 210 is turned on and the first capacitor C1 is charged. Is charged. That is, the first pulse detector 210 drives the first node ND1 to logic 'high' by performing a precharging operation in a section where the reset signal RST is logic 'high', and the first output signal OUT1. ) Is printed as logic 'low'. Like the first pulse detector 210, the second pulse detector 220 performs a precharging operation in response to the reset signal RST and outputs the second output signal OUT2 as logic 'low'.

Hereinafter, for convenience of description, a case where the logic 'high' section of the correction clock signal CLK_CCD is longer than the logic 'low' section will be taken as an example.

The first pulse detector 210 receives the corrected clock signal CLK_CCD, and the second pulse detector 220 receives the inverted corrected clock signal / CLK_CCD. As shown in FIG. 3, the second NMOS transistor N2 of the first pulse detector 210 is turned on in response to a logic 'high' period of the correction clock signal CLK_CCD. At this time, since the first NMOS transistor N1 is turned on in response to the reset signal RST, the charge charged in the first capacitor C1 is discharged little by little. In FIG. 5, the discharge amount of the second capacitor C2 is illustrated in addition to the first capacitor C1, and the second capacitor C2 corresponds to the second pulse detector 220.

Meanwhile, since the logic 'high' section of the correction clock signal CLK_CCD is longer than the logic 'high' section of the inverted correction clock signal / CLK_CCD, the discharge amount of the first capacitor C1 is discharged to the second capacitor C2. It becomes more than whole quantity. In other words, the voltage level of the first node ND1 corresponding to the first pulse detector 210 may be lowered faster than the voltage level of the second node (not shown) corresponding to the second pulse detector 220. . Thereafter, the first and second output signals OUT1 and OUT2 transition from logic 'low' to logic 'high' in response to the voltage levels of the first node ND1 and the second node. ), The first output signal OUT1 transitions to a logic 'high' before the second output signal OUT2 because the voltage level of N1 is lowered faster than the voltage level of the second node. In other words, an activation time point at which the first output signal OUT1 transitions corresponding to the logic 'high' period of the correction clock signal CLK_CCD is determined, and the second output signal OUT2 is the inversion correction clock signal / CLK_CCD. An activation time point at which a transition is made corresponding to the logic 'high' section, that is, the logic 'low' section of the correction clock signal CLK_CCD is determined.

Subsequently, the generated first and second output signals OUT1 and OUT2 are input to the detection signal output unit 230 (see FIG. 4). Since the first output signal OUT1 transitions before the second output signal OUT2 in FIG. 5 as an example, the circuit operation of FIG. 4 will be described based on this.

First, when the first output signal OUT1 is logic 'high' and the second output signal OUT2 is logic 'low', the first transfer unit TG1 receives the first output signal OUT1 and latches it. In operation 420, the latching unit 420 latches a logic 'high' that is the first output signal OUT1. Thereafter, when the second output signal OUT2 transitions to logic 'high', the second transfer unit TG2 is turned on so that the up detection signal DET_UP becomes logic 'low' and the down detection signal DET_DN is logic. 'High'. Here, the down detection signal DET_DN is logic 'high' as a result of the duty ratio of the correction clock signal CLK_CCD being greater than 50%.

On the contrary, when the logic 'low' section of the correction clock signal CLK_CCD is longer than the logic 'high' section, the up detection signal DET_UP becomes logic 'high' and the down detection signal DET_DN becomes logic 'high'. Here, the logic that the up detection signal DET_UP is logic 'high' is a conclusion that the duty ratio of the correction clock signal CLK_CCD is less than 50%.

The duty cycle detector 120 according to an embodiment of the present invention sequentially detects a logic 'high' section and a 'logical' low section of the correction clock signal CLK_CCD and sequentially outputs the first output signal OUT1 and the second output. The output signal UP2 is output, and the up detection signal DET_UP and the down detection signal DET_DN are output after the second output signal OUT2 is activated regardless of whether the first output signal OUT1 is activated. In other words, when one period of the correction clock signal CLK_CCD is logic 'high' and logic 'low', the up detection signal DET_UP and the down detection signal DET_DN corresponding to the duty ratio of the correction clock signal CLK_CCD are It is output in response to a logic 'low' period of the correction clock signal CLK_CCD.

Through this operation, the duty cycle detector 120 may generate the up detection signal DET_UP and the down detection signal DET_DN in response to the same number of pulses. That is, the first and second pulse detectors 210 and 220 perform a discharge operation corresponding to the logic 'low' sections of the same number of correction clock signals CLK_CCD as the logic 'high' sections of the correction clock signals CLK_CCD. The detection signal output unit 230 generates the up detection signal DET_UP and the down detection signal DET_DN accordingly. In other words, this means that the duty cycle detector 120 performs a very accurate operation in detecting the duty ratio of the corrected clock signal CLK_CCD.

Meanwhile, the reset signal generator 440 (see FIG. 4) outputs the second output signal OUT2 in synchronization with the reference clock signal CLK_REF. In other words, after the second output signal OUT2 is activated to logic 'high', the reset signal RST is activated to logic 'high' in response to the reference clock signal CLK_REF. In response to the reset signal REF, the first and second pulse detectors 210 and 220 perform a precharging operation to the corresponding node, in the case of the first pulse detector 210, to the first node ND1.

6 is a circuit diagram illustrating the duty cycle controller 110 of FIG. 1. For convenience of description, the control signal CTR generated by the control signal generation unit 130 is defined as a code type signal, and a reference numeral 'CTR <0: N>' is designated.

Referring to FIG. 6, the duty cycle controller 110 includes a delay unit 610, a clock signal output unit 620, and an adjusting unit 630 and 640.

The delay unit 610 is for delaying and outputting the input clock signal CLK_IN by a predetermined time and is composed of a plurality of inverters. As will be described later, the delay time reflected by the delay unit 610 corresponds to a time for mixing the input clock signal CLK_IN and the output clock signal of the delay unit 610 by the controllers 630 and 640.

The clock signal output unit 620 outputs the corrected clock signal CLK_CCD in response to the input clock signal CLK_IN and the output clock signal of the delay unit 610. The first and second driving controllers 321 and 322 ) And a drive unit 623.

Here, the pull-up driving controller 621 generates the pull-up driving signal PU in response to the input clock signal CLK_IN and the output clock signal of the delay unit 610, and the pull-down driving controller 622 generates the input clock. The pull-down driving control signal DN is generated in response to the signal CLK_IN and the output clock signal of the delay unit 610. Subsequently, the driver 623 outputs the correction clock signal CLK_CCD in response to the pull-up driving signal PU and the pull-down driving control signal DN, and corrects the clock in response to the pull-up driving signal PU. A first PMOS transistor P1 that is a pull-up driver for pull-up driving an output terminal outputting the signal CLK_CCD and a first pull-down driver that pulls down an output terminal in response to a pull-down driving control signal DN. An NMOS transistor NM1 is provided.

Meanwhile, the controllers 630 and 640 adjust the transition time of the correction clock signal CLK_CCD in response to the control signals CTR <0: N>. In the embodiment of the present invention, the controller 630, 640 is connected to the output terminal of the pull-down drive controller 622 as an example, and this configuration will be described below. For reference, the adjusters 630 and 640 may be connected to the output terminal of the pull-up driving controller 621 according to the design.

The adjusting unit 630 or 640 may supply a driving force corresponding to the control signal CTR <0: N> to the output terminal of the pull-down driving control unit 622 in response to the input clock signal CLK_IN. And a second supply unit 640 for supplying a driving force corresponding to the control signal CTR <0: N> to the output terminal in response to the output clock signal of the delay unit 610.

Here, the first supply unit 630 may include a path forming unit 631 for forming a current path connected to an output terminal of the transfer unit 632 and the pull-down driving control unit 622 in response to the input clock signal CLK_IN, A transfer unit 632 is provided to transfer the supply power supply voltage VDD to the path forming unit 631 in response to the control signal CTR <0: N>. Accordingly, the path forming unit 631 performs a turn on / off operation in response to the input clock signal CLK_IN, and the transfer unit 632 responds to the control signal CTR <0: N> to supply power voltage ( The number of paths through which VDD) is supplied varies. That is, the driving force corresponding to the control signal CTR <0: N> is transmitted to the output terminal of the pull-down driving controller 622. Subsequently, the first supply unit 630 includes a basic driver 633 for supplying a basic driving force to an output terminal of the pull-down driving controller 622 in response to the input clock signal CLK_IN.

Meanwhile, the second supply unit 640 has a symmetrical structure similar to that of the first supply unit 630, and operates according to the output clock signal of the delay unit 610 instead of the input clock signal CLK_IN, and supplies the supply power voltage VDD. Instead, supply the ground supply voltage (VSS).

Hereinafter, the circuit operation of the duty cycle controller 110 of FIG. 6 will be briefly described. According to an embodiment of the present invention, in adjusting the duty ratio of the correction clock signal CLK_CCD, the correction clock corresponding to the rising edge of the input clock signal CLK_IN according to the control signals CTR <0: N>. As an example, the falling edge of the signal CLK_CCD is adjusted.

First, when the input clock signal CLK_IN transitions from logic 'high' to logic 'low', the pull-up driving controller 621 generates a pull-up driving signal PU of logic 'low' and pull-down driving. The control unit 622 generates a logic 'low' pull down driving control signal DN. Accordingly, the first PMOS transistor P1 of the driver 623 is turned on and transitions from logic 'low' to logic 'high' of the correction clock signal CLK_CCD. At this time, since the driving force according to the control signals CTR <0: N> is not reflected, the correction clock signal CLK_CCD always has the same phase.

Subsequently, when the input clock signal CLK_IN transitions from logic 'low' to logic 'high', the path forming unit 631 of the first supply unit 630 and the path forming unit of the second supply unit 640 are delay units ( It is turned on for the time reflected in 610. Therefore, the driving force corresponding to the control signal CTR <0: N> is supplied to the output terminal of the pull-down driving controller 622, and the transition time of the correction clock signal CLK_CCD is adjusted according to the driving force. In other words, the slew rate corresponding to the falling edge of the corrected clock signal CLK_CCD is adjusted.

Hereinafter, a detailed description thereof will be described. For convenience of explanation, it will be assumed that the control signals CTR <0: N> are four-bit code signals. For reference, when the control signal is a 4-bit code signal, four MOS transistors are provided in the transfer units of the first and second supply units 630 and 640.

First, when the control signal is '0000', all of the transfer units 632 of the first supply unit 630 are turned on, and all of the transfer units of the second supply unit 640 are turned off. Therefore, the corrected clock signal CLK_CCD transitions from the logic 'high' to the logic 'low' fastest in the section corresponding to the delay time reflected by the delay unit 610. Next, when the control signal is '1111', all of the transfer units 632 of the first supply unit 630 are turned off, and all of the transfer units of the second supply unit 640 are turned on. Therefore, the correction clock signal CLK_CCD transitions to the logic 'low' most slowly in the section corresponding to the delay time reflected by the delay unit 610.

In other words, as the control signal changes from '0000'-> '0001'-> '0011'-> '0111'-> '1111', the transition point corresponding to the falling edge of the correction clock signal CLK_CCD is gradually pushed back. This circuit operation means that the duty ratio of the correction clock signal CLK_CCD is changed according to the control signal CTR <0: N.

The duty cycle correction circuit according to an exemplary embodiment of the present invention further simplifies the internal configuration, thereby speeding up the operation speed of the circuit, and minimizing the area and current consumption of the circuit. It is also possible to obtain a more accurate determination value in detecting the duty ratio.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

In addition, the duty cycle correction circuit according to an embodiment of the present invention is an example in which the falling edge of the correction clock signal CLK_CCD is adjusted, but the inverter is output to the output terminal where the correction clock signal CLK_CCD is output through a simple circuit change. It is also possible to adjust the rising edge of the correction clock signal CLK_CCD by adding or supplying a driving force to the output terminal of the pull-up driving controller 621.

In addition, the position and type of the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently according to the polarity of the input signal.

110: duty cycle control unit
120: duty cycle detection unit
130: control signal generator
140: clock output unit

Claims (10)

A duty cycle controller configured to receive a control signal and correct a duty ratio of the input clock signal to generate a corrected clock signal;
A duty cycle detector for detecting a duty ratio of the corrected clock signal and outputting a detection signal; And
A control signal generator for generating the control signal in response to the detection signal,
The duty cycle detection unit,
A first pulse detector for detecting a first logic level of the corrected clock signal;
A second pulse detector for detecting a second logic level of the corrected clock signal; And
And a detection signal output unit configured to output a detection signal corresponding to the duty ratio of the correction clock signal after the output signal of the second pulse detection unit is activated.
A first pulse detector for detecting a first logic level of the input clock signal;
A second pulse detector for detecting a second logic level of the input clock signal; And
Detection signal output unit for outputting a detection signal corresponding to the duty ratio of the input clock signal after the output signal of the second pulse detector is activated
A duty cycle detection circuit having a.
The method of claim 2,
The output signal of the first pulse detector is determined to be activated when the input clock signal maintains the first logic level. The duty cycle detection circuit, characterized in that the activation time point is determined in correspondence to the interval maintaining the level.
The method of claim 2,
Each of the first and second pulse detectors,
A discharge unit for discharging the precharged charge in response to a corresponding logic level of the input clock signal; And
And an output unit for activating its output signal in response to the discharge amount of the discharge unit.
The method of claim 2,
The detection signal output unit,
An input unit configured to receive an output signal of the first pulse detector in response to an output signal of the second pulse detector;
A latching unit for latching a signal transmitted through the input unit; And
And an output unit for outputting the output signal of the latching unit as the detection signal in response to the output signal of the second pulse detection unit.
The method of claim 2,
And a reset signal generator configured to generate a reset signal that is activated after the output signal of the second detector is activated.
The method according to claim 6,
And the first and second pulse detectors perform a precharging operation in response to the reset signal.
Sequentially detecting first and second logic levels corresponding to one period of the input clock signal; And
Detecting a duty ratio of the input clock signal in response to a detection signal corresponding to the second logic level
Method of operation of the duty cycle detection circuit comprising a.
9. The method of claim 8,
Detecting the duty ratio,
Receiving and latching a detection signal corresponding to the first logic level in response to the detection signal corresponding to the second logic level; And
And outputting the output signal of the latching step as a determined value corresponding to the duty ratio of the input clock signal in response to the detection signal corresponding to the second logic level.
9. The method of claim 8,
The determination value corresponding to the duty ratio of the input clock signal is output after the detection signal corresponding to the second logic level is activated.

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