KR20070031599A - Clock Buffer Circuit of Delay Locked Loop - Google Patents

Abstract

The present invention relates to a clock buffer circuit for correcting and outputting a distorted duty ratio when a severely distorted external clock signal is input, wherein the test mode decoder is configured to decode a test mode signal to generate control signals for controlling duty correction; A clock buffer controller configured to receive an external clock signal and generate a duty-corrected internal clock signal under the control of the control signals; Provided is a clock buffer circuit of a DLL including a clock buffer for receiving the duty-corrected internal clock signal and generating a DL clock signal having an accurate duty ratio.

Clock Buffer, Duty, External Clock

Description

Clock buffer circuit of DLL {Clock Buffer Circuit of Delay Locked Loop}

1 is a circuit diagram showing a clock buffer circuit according to a first preferred embodiment of the present invention.

2A to 2D are circuit diagrams illustrating the clock signal controller of FIG. 1.

3A to 3C are timing diagrams illustrating waveforms of signals of the clock buffer circuit of FIG. 1.

4 is a circuit diagram illustrating a clock buffer of FIG. 1.

<Description of Symbols for Main Parts of Drawings>

110: test mode decoder

120: clock buffer control unit

130: clock buffer

The present invention relates to a clock buffer circuit of a delay lock loop (DLL) used for double data rate synchronous dynamic random access memory (DDR SDRAM), in particular a clock buffer circuit capable of correcting and outputting an external clock signal having a duty ratio that is distorted. It is about.

The DLL is a clock generator for compensating skew between an external clock and data or a skew between an external clock and an internal clock. The DLL controls timing of data going out of the DRAM based on a clock input from the outside of the DRAM. The reason why the DLL is used in DRAM is that the phase is delayed by the input clock buffer, line loading, data output buffer, and other logic circuits that the external clock enters into the DRAM. To prevent this. In other words, the phase delayed by the DRAM internal circuit is referred to as clock skew, and a circuit for compensating this to prevent the phase of data output from the inside from being out of phase with the clock is a DLL. The DLL makes the data sensed in the DRAM core (CORE) output through the output buffer equal to the timing of the incoming clock based on the external clock.

The clock buffer used in the DLL receives the external clock signal and buffers it to generate the internal clock signal of the DLL. In this case, the clock buffer outputs the DLL clock signal without any correction even when an external clock signal having a distorted duty ratio is input for various reasons such as a change in PVT (Process, Voltage, Temperature), an interface problem between the chip set and the DRAM. If the duty cycle uses the distorted external clock signal in the DLL as it is, the higher the frequency, the higher the possibility that the external clock signal passes through the delay block (not shown) of the DLL and the pulse of the clock signal is eliminated. Of course, the DLL is configured to perform a duty cycle correction operation before or after the locking loop, but the duty cycle correction (DCC) capability is limited depending on the degree of distortion of the duty ratio.

Therefore, if the DLL clock having the distorted duty ratio is finally outputted, accurate data cannot be delivered to the chip set. This slows down the performance of the DLL, which leads to a total memory performance problem.

An object of the present invention is to provide a clock buffer circuit that corrects and outputs a distorted duty ratio using a test mode signal when an external clock signal having a severely distorted duty ratio is input.

The clock buffer circuit of the DLL according to the present invention for achieving the above object is a test mode decoder for decoding the test mode signal to generate control signals for controlling the duty correction; A clock buffer controller configured to receive an external clock signal and generate a duty-corrected internal clock signal under the control of the control signals; And a clock buffer configured to receive the duty corrected internal clock signal and generate a DL clock signal having an accurate duty ratio.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments to complete the disclosure of the present invention and complete the scope of the invention to those skilled in the art. It is provided to inform you. Like reference numerals in the drawings denote like elements.

1 is a block diagram illustrating a clock buffer circuit of a DLL according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the clock buffer circuit includes a test mode decoder 110, a clock buffer controller 120, and a clock buffer 130. The test mode decoder 110 and the clock buffer controller 120 are provided to generate an internal clock signal having an accurate duty ratio at all times regardless of the duty ratio of the external clock signals EXCLK and EXCLKb. These 110 and 120 may select an external clock signal to be buffered according to the distortion degree of the duty ratio.

In FIG. 1, the test mode decoder 110 decodes the test mode signals DTEST1 and DTEST2 to control the generation of control signals T1, T1b, T2, and T2b for controlling generation of duty-corrected internal clock signals DTCLK and DTCLKb. , T3, T3b, T4, T4b). The test mode signals DTEST1 and DTEST2 detect the duty ratio distortion of the clock signal finally output from the DLL in the test mode. The test mode signals are information on the duty ratio of the clock signal finally output from the DLL. Have Therefore, by using the test mode signal, the duty-corrected internal clock signals DTCLK and DTCLKb can be generated. The detailed description will be described below. Here, the number of control signals T1, T1b, T2, T2b, T3, T3b, T4, and T4b is not limited thereto but may be made larger than this. The clock buffer controller 120 receives the external clock signals EXCLK and EXCLKb and receives the duty-corrected internal clock signal DTCLK, under the control of the control signals T1, T1b, T2, T2b, T3, T3b, T4, and T4b. DTCLKb). The clock buffer 130 buffers the duty-corrected internal clock signals DTCLK and DTCLKb to generate a DL clock signal DLL_CLK.

2A to 2D are circuit diagrams showing the detailed configuration of the clock buffer controller 120 shown in FIG. 1, and FIGS. 3A to 3C are external clock signals and output signals which are input signals of the clock buffer controller shown in FIG. A timing diagram showing a waveform of an internal clock signal.

2A to 2D, the clock buffer controller 120 includes a plurality of clock buffer controllers, each of which consists of two inverters and two tri-state buffers. The two inverters included in each of the clock buffer controllers output the internal clock signals DTCLK and DTCLKb with the correct duty ratio regardless of the duty ratio of the external clock signals EXCLK and EXCLKb. (Inverters are designed in different sizes with the PMOS and NMOS transistors connected in series between the power supply and ground.)

Hereinafter, the operation of the clock buffer controller 120 will be described in more detail with reference to FIGS. 2A to 2D and FIGS. 3A to 3C.

The clock buffer controller shown in FIG. 2A is designed to have the same size of 50:50 PMOS and NMOS transistors of the inverters 121a and 123a. Therefore, when the control signals T1 and T1b are enabled, each of the three-state buffers 122a and 124a has an internal clock signal having the duty ratio of the external clock signals EXCLK and EXCLKb input as shown in FIG. 3A. Outputs (DTCLK and DTCLKb) respectively.

In the clock buffer controller shown in Fig. 2B, the NMOS size of the inverter 121b is designed to be smaller than the PMOS size, and the NMOS size of the inverter 123b is designed to be larger than the PMOS size. Specifically, the inverter 121b has a smaller NMOS size than the PMOS size, so that the transition time to the logic high level is shorter than the transition time to the logic low level, and the transition time to the logic low level is greater than the transition time to the logic high level. It takes a long time The inverter 123b has a smaller PMOS size than the NMOS size, so that the transition to the logic low level takes less time than the transition to the logic high level, and the transition to the logic high level takes longer than the transition to the logic low level. . Accordingly, as shown in FIG. 3B, when the external clock signal EXCLK having the high pulse width distorted passes through the inverter 121b, the high pulse width of the external clock signal EXCLK is reduced to about 30%. In this case, the high pulse width of the wide external clock signal EXCLK is narrowed, and the duty ratio of the internal clock signal DTCLK becomes more accurate to about 50:50. The high pulse width of the external clock signal EXCLKb, in which the high pulse width is narrowly distorted, becomes wide by about 70%. In this case, the high pulse width of the narrow external clock signal EXCLKb becomes wider, and the duty ratio of the internal clock signal DTCLKb becomes more accurate to about 50:50.

As a result, when the external clock signals EXCLK and EXCLKb as shown in Fig. 3B are input, the tri-state buffers 122b and 124b are enabled by the control signals T2 and T2b, as shown in Fig. 3B. The internal clock signals DTCLK and DTCLKb having the correct duty ratio are output. That is, the external clock signals EXCLK and EXCLKb having the duty ratio as shown in FIG. 3B pass through the inverter 121b 123b of FIG. 2B in which the PMOS and NMOS size ratios are properly adjusted, and have an internal clock having a duty ratio of about 50:50. The signals DTCLK and DTCLKb are output.

In the clock buffer controller shown in Fig. 2C, the PMOS size of the inverter 121c is designed to be smaller than the NMOS size, and the PMOS size of the inverter 123c is designed to be larger than the NMOS size. Therefore, the inverter 121c has a smaller PMOS size than the NMOS size, so that the transition time to the logic low level is shorter than the transition time to the logic high level, and the transition time to the logic high level is longer than the transition time to the logic low level. Takes The inverter 123c has a smaller NMOS size than the PMOS size, so that the transition to the logic high level takes less time than the transition to the logic low level and the transition to the logic low takes longer than the transition to logic high. More specifically, as shown in FIG. 3C, when the external clock signal EXCLK having a narrowly distorted high pulse width passes through the inverter 121c, the high pulse width of the external clock signal EXCLK in which the high pulse width is narrow is narrowed. This is about 70% wider. In this case, the high pulse width of the narrow external clock signal EXCLK becomes wider, and the duty ratio of the internal clock signal DTCLK becomes more accurate to about 50:50. The high pulse width of the external clock signal EXCLKb, which has been relatively distorted with a high pulse width, is narrowed to about 30%. In this case, the high pulse width of the wide external clock signal EXCLKb becomes narrow, and the duty ratio of the internal clock signal DTCLKb becomes more accurate to about 50:50.

As a result, when the external clock signals EXCLK and EXCLKb as shown in Fig. 3C are input, the tri-state buffers 122c and 124c are enabled by the control signals T3 and T3b, as shown in Fig. 3C. The internal clock signals DTCLK and DTCLK with the correct duty ratio are output. That is, the external clock signals EXCLK and EXCLKb having the duty ratio as shown in FIG. 3C pass through the inverter 121c 123c of FIG. 2C in which the PMOS and NMOS size ratios are properly adjusted, and have an internal clock having a duty ratio of about 50:50. The signals DTCLK and DTCLKb are output.

In the clock buffer controller shown in Fig. 2D, the PMOS size of the inverter 121d is designed to be smaller than the NMOS size, and the PMOS size of the inverter 123d is designed to be larger than the NMOS size. Since the clock buffer controller shown in FIG. 2D also operates in the same manner as the clock buffer controller shown in FIGS. 2B and 2C, a detailed description thereof will be omitted.

The PMOS and NMOS sizes of the above-described inverters are not limited to FIGS. 2A to 2D but may be variously designed within a range of 30% to 70%.

As described above, the inverters may properly adjust the PMOS and NMOS size ratios so as to produce the internal clock signals DTCLK and DTCLKb having the correct duty ratio at all times regardless of the duty ratio of the external clock signals EXTCLK and EXCLKb input from the outside. Can be. The three-state buffers output duty-corrected internal clock signals DTCLK and DTCLKb in response to the control signals T1 to T4 and T1b to T4b generated by the test mode signals DTEST1 and DTEST2.

In other words, after the PMOS and NMOS sizes of the inverter are designed differently, the external clock signal is properly adjusted for the PMOS and NMOS sizes by using a test mode signal having information on the duty ratio of the clock signal finally output from the DLL. If the output is passed as an internal clock signal, the internal clock signal is output with an accurate duty ratio even if the duty ratio of the external clock signal is distorted.

4 is a diagram showing the detailed configuration of the clock buffer shown in FIG.

Referring to FIG. 4, the clock buffer 130 is operated by receiving the internal clock signals DTCLK and DTCLKb whose duty is corrected, instead of directly applying the external clock signal, as shown in FIGS. 3B to 3D. Generates the correct DL clock signal (DLL_CLK) at about 50:50. The clock buffer 130 includes a differential amplifier 131, a clock generator 132, and a clock generation controller 133. The differential amplifier 131 differentially amplifies and outputs the internal clock signals DTCLK and DTCLKb when the enable signal EN is activated. The clock generator 132 combines the output signal of the differential amplifier 131 and the output signal of the clock generation controller 133 to output the DL clock signal INT_CLK. The clock generation control unit 133 receives the clock enable signal CLK_ENb under the control of the output signal of the differential amplifier 131 and transfers the clock enable signal CLK_EN having a phase opposite to that of the clock enable signal CLK_ENb. .

In FIG. 4, the differential amplifier 131 is composed of PMOS transistors P1 and P2 and NMOS transistors N1-N3, which are connected between the power supply voltage VDD and the node A. P2 is connected between the power supply voltage VDD and the node B, and the gates of the PMOS transistors P1 and P2 are turned on / off by receiving the node A signal. The NMOS transistor N1 is connected between the node A and the node C and is turned on / off by receiving an internal clock signal DTCLK as a gate. The NMOS transistor N2 is connected between the node B and the node C and is turned on / off by receiving an internal clock signal DTCLKb as a gate. The NMOS transistor N3 is connected between the node C and the ground VSS and is turned on / off by receiving an enable signal EN as a gate. The clock generator 132 includes an inverter IV3-IV5 and a NAND gate ND1. The inverters IV3-IV5 receive and buffer the output signal of the differential amplifier 131, that is, the node B signal. The NAND gate ND1 inverts and outputs the signal output through the inverters IV3-IV5 and the signal output through the clock generation controller 133. The clock generation controller 133 includes inverters IV1 and IV2 and a transfer gate TG1. The inverter IV1 inverts the output signal of the differential amplifier 131 and outputs it. The transfer gate TG1 transfers the clock enable signal CLK_ENb in response to the output signal of the differential amplifier 131 and the output signal of the inverter IV1. The inverter IV2 inverts the output signal of the transfer gate TG1 and outputs it.

Hereinafter, the operation of the clock buffer will be described in more detail with reference to FIG. 4.

First, after the enable signal EN is activated, when the internal clock signals DTCLK and DTCLKb are input, the differential amplifier 131 differentially amplifies the internal clock signals DTCLK and DTCLKb. At this time, when the NMOS transistor N2 is turned on before the NMOS transistor N1, the node B becomes the level of the ground voltage VSS before the node A, and the PMOS transistors P1 and P2 are turned on. In this case, the node B is at the level of the ground voltage VSS, and the transfer gate TG1 is turned on. The NAND gate ND1 receives a logic high signal as one input terminal and a clock enable signal CLK_EN output from the clock generation controller 133 as another input terminal. The NAND gate ND1 receives a signal as shown in FIGS. 3A to 3D. Outputs the EL clock signal DLL_CLK. On the contrary, when the NMOS transistor N1 is turned on before the NMOS transistor N2, the node A is turned to the level of the ground voltage VSS before the node B, and the PMOS transistors P1 and P2 are turned on. In this case, the node B is at the level of the power supply voltage VDD, and the transfer gate TG1 is turned off. Since the NAND gate ND1 receives a logic low level through one input terminal, the DL clock signal DLL_CLK is fixed to logic high regardless of a signal input to the other input terminal.

As described above, the clock buffer operates by receiving new internal clock signals DTCLK and DTCLKb having a more accurate duty ratio than in the related art, thereby preventing the clock pulses from disappearing even at a high frequency and mixing in the DCC clock. I can do it smoothly. That is, when the clock buffer of the DLL is controlled by the test mode decoder and the clock buffer controller, it is possible to generate a new DL clock signal DLL_CLK having an accurate duty ratio. As a result, the new DL clock signal with the correct duty ratio ensures that the data supply between the DRAM and the chipset can be transferred accurately and without error.

The present invention can be used for all semiconductor devices, computer systems, etc. that require a DLL.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can prevent the high pulse width of the clock signal from disappearing by rotating the delay loop even when an external clock signal whose duty ratio is severely distorted while being input at a high frequency is input, and the operation of the DCC mixing block is prevented. You can afford to create a DLL's output clock with more accurate duty cycle correction.

In addition, according to the present invention, it is possible to provide a digital DLL structure with enhanced safety and duty cycle correction function during high frequency operation.

Claims (7)

A test mode decoder that decodes the test mode signal to generate control signals for controlling duty correction; A clock buffer controller configured to receive an external clock signal and generate a duty-corrected internal clock signal under the control of the control signals; And a clock buffer configured to receive the duty-corrected internal clock signal and generate a DL clock signal having an accurate duty ratio. The method of claim 1, And the clock buffer controller is configured of a plurality of clock buffer controllers having different sizes in order to generate the duty-corrected internal clock signal. The method of claim 2, Each of the plurality of clock buffer controllers is controlled by each of the control signals to generate the duty-corrected internal clock signal. The method of claim 2, Each of the plurality of clock buffer controllers may include a first inverter for inverting and outputting the external clock signal; A second inverter for inverting and outputting an inverted signal of the external clock signal; A first tri-state buffer for inverting and outputting the output signal of the first inverter; And a second tri-state buffer for inverting and outputting the output signal of the second inverter. The method of claim 4, wherein Each of the first and second inverters includes a PMOS transistor and an NMOS transistor connected in series between a power supply voltage and a ground voltage, and generate the duty-corrected internal clock signal by adjusting the PMOS and NMOS sizes differently. A clock buffer circuit of a DLL. The method of claim 4, wherein The first inverter has the PMOS size larger than the NMOS size, and the second inverter has the PMOS size smaller than the NMOS size. The method of claim 4, wherein Wherein the first inverter has a smaller PMOS size than the NMOS size, and the second inverter has a larger PMOS size than the NMOS size.

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