KR20120112032A - Voltage generation circuit - Google Patents

Abstract

PURPOSE: A voltage generation circuit is provided to prevent noise from being provided to an audible band by a supply ripple. CONSTITUTION: A first switching element(TR1) and a second switching element(TR2) are serially connected between high potential power and low potential power. An error signal generation circuit(30) generates an error signal(Err) according to an output voltage(VOUT) generating in the output terminal. The error signal generation circuit comprises a resistance device(322), a resistance device(324), a voltage source(34), and an amplifier(36). A triangle wave signal generating circuit(40) generates a triangle wave signal(Vramp) in which a level is changed according to a reset signal cycle. A comparison circuit(50) includes an operational amplifier including an inverting input terminal and a non-inverting input terminal. [Reference numerals] (69) Wave shaping circuit; (71) Pulse generation circuit

Description

Voltage Generation Circuitry {VOLTAGE GENERATION CIRCUIT}

The present invention relates to a technique for generating a predetermined voltage.

Background Art A technique for generating a predetermined voltage and supplying it to a driving load under control of a transistor connected to a direct current power source (DC-DC converter) has been conventionally proposed. For example, Patent Literature 1 proposes a technique for changing a period for controlling conduction / non-conduction of a transistor to low load and high load. Specifically, two systems of a reference clock signal of a predetermined frequency and a control clock signal of a variable frequency according to a load are generated in parallel, and at high loads, the transistor is controlled according to the reference clock signal, and at low loads, the control clock signal is loaded. To control the transistor. According to the above structure, it is possible to reduce power consumption at low load.

Japanese Patent Laid-Open No. 2008-236822

However, in the technique of Patent Literature 1, under low load, as the load decreases, the frequency of the control clock signal decreases, so that the operating frequency of the transistor may enter the audible band. When the voltage generated by the DC-DC converter is used as the power supply voltage, the ripple component synchronized with the operating frequency of the transistor is superimposed on this power supply voltage. When the conventional DC-DC converter is used as a power supply voltage of a circuit for processing an audible band signal, there is a problem that noise is superimposed on the signal.

In view of the above circumstances, the present invention is to solve the problem of not generating power supply noise even if the load is light.

MEANS TO SOLVE THE PROBLEM In order to solve the above subject, the means employ | adopted by this invention is demonstrated. In addition, in order to make understanding of this invention easy, in the following description, although correspondence of the element of this invention and the element of embodiment mentioned later is added in parentheses, it is not the meaning which limits the scope of the present invention to the illustration of embodiment. In addition, the following description does not limit this invention.

The voltage generation circuit of the present invention includes a first switching element TR1, an output node N and a second switching element TR2 connected in series between a high potential power supply and a low potential power supply, and the voltage of the output node. An error signal generator 30 for generating an error signal Err that is a difference between the detection voltage V1 and the reference voltage V2, and a control signal CTL that is active for a period corresponding to the magnitude of the error signal. The first switching element in the first period from the start of the active period until the reference time elapses, when the control signal generation unit 50 and the active period of the control signal are longer than the reference time Tref. Is turned on, and when the active period of the control signal is shorter than the reference time, the first driver 81 to turn on the first switching element in the active period and the second to turn on or off the second switching element. 2 drive parts (82 84) and when the frequency of the control signal is controlled in the range from the lower limit frequency fmin to the upper limit frequency fmax, and the active period of the control signal is shorter than the reference time, the frequency of the control signal is set to the lower limit. When the frequency is set and the active period of the control signal is longer than the reference time, the frequency control unit 60 controls the frequency of the control signal to increase as the time difference between the active period and the reference time becomes longer.

According to the present invention, since the first switching element and the second switching element operate in synchronization with the control signal, the frequency of the control signal does not lower than the lower limit frequency. Therefore, the voltage output from the output node does not include a frequency component lower than the lower limit frequency. Therefore, when the voltage of the output node is smoothed and used as a power supply, the frequency component of the power supply ripple of the rear end circuit can be made higher than the lower limit frequency.

More specifically, it is preferable that the said lower limit frequency is higher than an audible band. In this case, it is possible to prevent noise from entering the audible band due to power supply ripple, even if a circuit in a later stage processes a signal in the audible band.

In the above-described voltage generation circuit, the second driving unit turns on the second switching element when the first switching element is switched from on to off, and the reference time elapses after the first switching element is turned on. When the potential of the output node is lower than the low potential power before a time point, the second switching element is turned off at the reference time point, and when the potential of the output node is lower than the low potential power after the reference time point. The second switching element is turned off when the potential of the output node is lower than the low potential power supply.

According to the present invention, the second switching element is turned on when the first switching element is turned off, and turned off when the potential of the output node is lower than the low potential power supply. However, if the potential of the output node is lower than the low potential power before the reference time point, the second switching element is kept on even if the potential of the output node is lower than the low potential power, and the second switching element is turned off at the reference time point. Let's do it. Therefore, even if the load is light to some extent, the second switching element and the first switching element are always operated for a reference time. Therefore, the lower limit frequency of the ripple component which overlaps with the voltage of an output node can be set.

Further, when the second switching element is operated when the potential of the output node is lower than the low potential power supply, the power consumption increases, but as the load becomes heavy, the consumption of reactive power decreases. Therefore, the power consumption can be reduced as compared with the case where the lower limit frequency is set for the operating frequency of the transistor using the bleeder resistor.

In the above-described voltage generation circuit, the frequency controller includes a capacitor 65, a comparator 68 for comparing the voltage of the capacitor with a predetermined voltage, a supply 61, 62 for supplying current to the capacitor, and 64), and a discharge section 63 for discharging the charge charged in the capacitor, wherein the supply section supplies a current of a predetermined value to the capacitor when the control period is shorter than the reference time. When the active period of the control signal is longer than the reference time, a time difference between the active period and the reference time supplies a current larger than the predetermined value to the capacitor, and the other time is equal to the predetermined value. Supply a current to the capacitor, generate a reset signal RES for controlling the discharge unit based on the first output signal from the comparison unit, and generate the reset signal. Group control signal supplied to the generator, and generates the control signal portion preferably generates the control signal in synchronization with the reset signal.

According to the present invention, when the voltage of the capacitor reaches a predetermined voltage, a reset signal is generated, and the charge charged in the capacitor is discharged by the reset signal, so that the frequency controller functions as an oscillator circuit. In addition, since the charging current to the capacitor is controlled to be as large as the difference between the active period and the reference time when the active period of the control signal is longer than the reference time, the period of the reset signal is shortened. That is, when the load increases to some extent, the frequency of the control signal may be increased according to the size of the load.

A reference signal generator 70 for generating the reference signal 72a inverting the signal that becomes active in the period from the start of the active period of the control signal until the reference time has elapsed in the voltage generation circuit described above; And the second driving section detects a period during which the potential of the output node is less than the potential of the low potential power source, and generates a detection signal 82a, and the detection signal and the reference signal. A logic circuit 83 for calculating the logical product and a signal for controlling on / off of the first switching element are supplied to a set terminal, and a second output signal 83a from the logic circuit is supplied to a reset terminal, It is preferable to include an SR flip-flop 84 for supplying a third output signal DR2 to the gate of the second switching element.

According to the present invention, since the rise of the detection signal is masked by the reference signal by the logic circuit, even if the rise of the detection signal occurs until the reference time has elapsed since the first switching element is turned on, the detection of the second switching element is performed by masking it. On may be continued and the second switching device may be turned off at a time point when the reference time has elapsed since the first switching device is turned on. Accordingly, the second switching element and the first switching element are always operated for a reference time. Therefore, the lower limit frequency of the ripple component which overlaps with the voltage of an output node can be set.

1 is a block diagram of a voltage generation circuit according to an embodiment of the present invention.
2 is a timing chart of each signal.
3 is a graph showing the relationship between the frequency of the reset signal and the load.
4 is a timing chart showing the relationship between the voltage of the node and various signals in the first region.
5 is an explanatory diagram for explaining the relationship between the voltage of a node in the first region and the on time of the P-channel transistor and the N-channel transistor.

1 is a block diagram of a voltage generation circuit 100 according to an embodiment of the present invention, and FIG. 2 is a timing chart thereof. The voltage generation circuit 100 is a power supply circuit (DC-DC converter) that generates an output voltage VOUT corresponding to the input voltage VIN generated by the DC power supply and supplies it to the output terminal 14. A drive load (not shown) is connected to the output terminal 14. As shown in FIG. 1, the voltage generation circuit 100 includes a P-channel transistor TR1, an N-channel transistor TR2, a choke coil L, and a smoothing capacitance C. As shown in FIG.

Transistor TR1 (switching element) and transistor TR2 (switching element) are connected in series between the power supply. Specifically, the drain of the transistor TR1 and the drain of the transistor TR2 are connected to each other at the output node N, the input voltage VIN is supplied to the source of the transistor TR1, and the source of the transistor TR2 is Grounded. The choke coil L is interposed between the connection point N of the transistors TR1 and TR2 and the output terminal 14 (driving load). The smoothing capacitance C is connected to the output terminal 14 to smooth the output voltage VOUT.

The error signal generation circuit 30 generates an error signal Err corresponding to the output voltage VOUT generated at the output terminal 14. As shown in FIG. 1, the error signal generation circuit 30 includes a resistance element 322, a resistance element 324, a voltage source 34, and an amplifier (error amplifier) 36. The resistive element 322 and the resistive element 324 generate the feedback voltage V1 by the divided voltage of the output voltage VOUT returned from the output terminal 14. The voltage source 34 is a direct current power source that generates a predetermined comparison voltage V2. The feedback voltage V1 is supplied to the noninverting input terminal of the amplifier 36, and the comparison voltage V2 is supplied to the inverting input terminal of the amplifier 36. The amplifier 36 generates an error signal Err by amplifying the difference voltage between the feedback voltage V1 and the comparison voltage V2. Specifically, the higher the output voltage VOUT with respect to the comparison voltage V2, the higher the error signal Err, and the lower the output voltage VOUT with respect to the comparison voltage V2, the lower the error signal Err. .

The triangular wave signal generation circuit 40 of FIG. 1 generates a triangular wave signal Vramp whose level is changed by a period of the reset signal RES (see FIG. 2). The triangular wave signal generation circuit 40 includes a current source 42, a transistor 44, and a capacitor 46. The voltage between both ends of the capacitor 46 is supplied to the comparison circuit 50 as a triangular wave signal Vramp. The current source 42 is a constant current source that generates a predetermined current and supplies it to the capacitor 46. The transistor 44 is a switch interposed between the both ends of the capacitor 46. In the period where the transistor 44 is in the off state, the potential of the node 45 rises linearly because the capacitor 46 is charged with a constant current. On the other hand, the reset signal RES in the form of a pulse is supplied to the gate of the transistor 44. In the active period of the reset signal RES, the transistor 44 is turned on, and the charge charged in the capacitor 46 is discharged. Thus, a triangular wave signal Vramp is obtained.

The comparison circuit 50 of FIG. 1 is composed of an operational amplifier including an inverting input terminal and a non-inverting input terminal. The error signal Err generated by the error signal generation circuit 30 is supplied to the non-inverting input terminal of the comparison circuit 50, and the triangular wave signal Vramp is supplied to the inverting input terminal of the comparison circuit 50. The comparison circuit 50 compares the error signal Err and the triangular wave signal Vramp to generate a control signal CTL according to the result of the comparison. Specifically, as shown in FIG. 2, when the error signal Err exceeds the triangular wave signal Vramp, the control signal CTL is set to a high level, and the error signal Err converts the triangular wave signal Vramp. In the case of lowering, the control signal CTL is set to a low level.

As described above, at light loads, the level of the error signal Err is lowered, and as the load becomes heavier, the pulse width WX of each control pulse PX becomes longer (the lower the load, the shorter the pulse width WX). ]. As understood from the above description, the comparison circuit 50 generates a pulse width for generating a control signal CTL in which a pulse PX of the pulse width WX is disposed in accordance with an error signal Err (output voltage VOUT). It functions as a modulation circuit.

The reset signal generation circuit 60 of FIG. 1 generates the reset signal RES of a predetermined period when the active period (high level) of the control signal CTL is shorter than the predetermined reference time Tref, and the control signal CTL. In the case where the active period of?) Is longer than the reference time Tref, a reset signal RES is generated in which the period becomes shorter as the time difference between the reference time Tref and the active period becomes longer.

The node 66 connects the transistors 63 and 64, the capacitor 65, the first current source 61, and the comparator 68. The reset signal generation circuit 60 includes a first current source 61 for outputting a first current i1 and a second current source 62 for outputting a second current i2, transistors 63 and 64, and a capacitance. An element 65 is provided. When the difference time signal Z is inactive (high level), the transistor 64 is turned off and the capacitor 65 is charged by the first current i1, but the difference time signal Z is active (low level). ), The transistor 64 is turned on, and the capacitor 65 is charged by the first current i1 and the second current i2.

The non-inverting input terminal of the comparator 68 is connected to the node 66, while the inverting input terminal is supplied with the comparison voltage V3 from the voltage source 67. The output signal of the comparator 68 becomes a high level when the voltage of the node 66 exceeds the comparison voltage V3. The waveform shaping circuit 69 generates the reset signal RES which becomes high level for a predetermined period in synchronization with the rising edge of the output signal of the comparator 68. The reset signal RES is supplied to the gate of the transistor 63. When the reset signal RES is at a high level, the transistor 63 is turned on and the charge accumulated in the capacitor 65 is discharged. That is, the period of the reset signal RES is a time from the voltage of the node 66 to the ground after the discharge of the capacitor 65 becomes the voltage V3 of the voltage source 67. The current flowing into the capacitor 65 is larger in that the transistor 64 is turned on. Therefore, the longer the active period of the difference time signal Z, the shorter the period of the reset signal RES. Since the reset signal RES is fed back to the gate of the transistor 63, the reset signal generation circuit 60 functions as an oscillation circuit. In this embodiment, the magnitudes of the first current i1 and the second current i2 are the same. In addition, the reset signal RES is supplied to the triangle wave signal generation circuit 40 and the differential time signal generation circuit 70. The triangle wave signal generation circuit 40 and the differential time signal generation circuit 70 operate in synchronization with the reset signal RES. For this reason, as shown in FIG. 2, the triangular wave signal Vramp, the control signal CTL, and the MaxPon signal 71a are synchronized with the reset signal RES. Thus, the reset signal generation circuit 60 functions as a frequency control section for controlling the frequency of the control signal CTL.

The differential time signal generation circuit 70 includes a pulse generation circuit 71 for generating a MaxPon signal 71a that becomes high as the reference time Tref after the reset signal RES becomes active, the inverter 72, A NAND circuit 73 is provided. The high level period of the MaxPon signal 71a represents the maximum time for which the P-channel transistor TR1 is turned on. In other words, the P-channel transistor TR1 does not turn on after the reference time Tref.

In addition, the MaxPon signal 71a is inverted in the inverter 72, and the inversion of the logical product of the inverted MaxPon signal 71a and the control signal CTL is calculated in the NAND circuit 73. As a result, the differential time signal Z becomes active (low level) when the high level period of the control signal CTL is longer than the reference time Tref, as shown in FIG. As described above, when the difference time signal Z is active, the transistor 64 is turned on. As shown in FIG. 2, the slope of the voltage Y of the node 66 is a period during which the difference time signal Z is active. It becomes steep at (Tx).

The driving unit 80 of FIG. 1 supplies a driving signal DR1 obtained by calculating the logical product inversion of the control signal CTL and the MaxPon signal 71a to the P-channel transistor TR1. 1 drive unit). In the transistor TR1, the driving signal DR1 is turned on during a low level period. The MaxPon signal 71a defines the maximum time that the transistor TR1 is on. In addition, the drive unit 80 includes a comparator 82, an end circuit 83, and an SR flip-flop 84. These structures function as a second driver for generating a drive signal DR2 for controlling the on / off of the N-channel transistor TR2.

The output signal of the SR flip-flop 84 becomes the drive signal DR2. The drive signal DR1 is supplied to the set terminal of the SR flip-flop 84. Therefore, when the drive signal DR1 transitions from low level to high level and the transistor TR1 switches from on to off, the drive signal DR2 transitions from low level to high level.

The timing at which the drive signal DR2 transitions from the high level to the low level is determined by the output signal 83a of the AND circuit 83 supplied to the set terminal. The AND circuit 83 calculates the logical product of the signal 72a inverting the MaxPon signal 71a and the output signal 82a of the comparator 82 and outputs the signal 83a.

The voltage of the node N (drain of the transistor TR2) is supplied to the inverting input terminal of the comparator 82, while the voltage of the source of the transistor TR2 is supplied to the non-inverting input terminal. Therefore, when the voltage (ground voltage) of the source of the transistor TR2 is higher than the voltage of the drain of the transistor TR2, the output signal 82a of the comparator 82 becomes a high level.

The time when the P-channel transistor TR1 is turned on is the time when the driving signal DR1 becomes active (low level), and gradually increases when the load becomes heavy, and becomes constant when the reference time Tref is reached. On the other hand, the time when the N-channel transistor TR2 is turned on is the time when the drive signal DR2 becomes active (high level). Since the drive signal DR1 is supplied to the set terminal of the SR flip-flop, when the P-channel transistor TR1 is switched from on to off, the N-channel transistor TR2 is turned on.

The timing at which the N-channel transistor TR2 is switched from on to off is then defined by the signal 83a supplied to the reset terminal. The AND circuit 83 generating the output signal 83a functions as mask means for masking the output signal 82a of the comparator 82 using the signal 72a inverting the MaxPon signal 71a. That is, the rise of the output signal 83a that occurs from the time when the drive signal DR1 becomes active until the reference time Tref elapses is masked by the signal 72a. As a result, the timing at which the N-channel transistor TR2 is switched from on to off is a time point when the reference time Tref elapses after the drive signal DR1 becomes active. On the other hand, when the rise of the output signal 82a of the comparator 82 occurs after the drive time DR1 becomes active after the reference time Tref has elapsed, the N-channel transistor TR2 is at this point. Switch from on to off.

In this way, by controlling the timing at which the N-channel transistor TR2 is switched from on to off, it is possible to control the operation time of the P-channel transistor TR1 and the N-channel transistor TR2 so as not to be shorter than the reference time Tref. .

In the above configuration, the frequency of the reset signal RES is changed as shown in FIG. Among these, PFM control is performed in the first region X1 corresponding to the light load and the second region X2 corresponding to the heavy load, and the PWM operates at the upper limit frequency fmax in the third region X3 corresponding to the heavy load. Control is executed.

First, the magnitude of the load in the first region X1 corresponding to the light load is less than R1. This is the case where the active period of the control signal CTL is shorter than the reference time Tr. In this case, since the difference time signal Z becomes inactive, the transistor 64 is turned off. For this reason, the second current i2 does not flow into the node 66. Therefore, since the frequency of the reset signal RES is determined only by the first current i1, this frequency becomes a constant lower limit frequency fmin.

By the way, the voltage generation circuit 100 of this embodiment is used as a power supply of the circuit which processes audible band signal. The signal output from the node N is integrated by the coil L or the smoothing capacity C to become the output voltage VOUT, but the voltage change of the node N cannot be completely removed. When the ripple component that overlaps the output voltage VOUT enters the audible band, the power supply ripple becomes signal noise in the circuit of the subsequent stage. Therefore, in this embodiment, the lower limit frequency fmin is set to a frequency higher than the audible band.

4 shows the voltage VN of the node N in the first region X1. In the first region X1, the driving signal DR1 is activated in the active period of the control signal CTL, and the P-channel transistor TR1 is turned on. In the on period of the P-channel transistor TR1, the output current IL is discharged from the node N, and the voltage VN increases.

Subsequently, the drive signal DR2 becomes active from the start of the inactive period of the control signal CTL to the end of the active period of the MaxPon signal 71a, and the N-channel transistor TR2 is turned on. In the on period of the N-channel transistor TR2, the output current IL is sucked into the node N and the voltage VN decreases.

In the first region X1, even if the voltage VN becomes a negative value, the on-period of the N-channel transistor TR2 continues. Substantial power supplied to the load is obtained by subtracting the area S2 of the negative voltage VN from the area S1 of the positive voltage VN. In other words, the portion of the negative voltage VN becomes invalid power that is not supplied to the load. However, even when the load is light, the lower limit frequency fmin in the PFM control can be defined by operating the P-channel transistor TR1 and the N-channel transistor TR2.

Next, with reference to FIG. 5, the relationship between the voltage VN of the node N in the 1st area | region X1, and the ON time of a P-channel transistor and an N-channel transistor is demonstrated. 5A illustrates the case where the error signal Err is zero. In this case, the area S1 is equal to the area S2. As a result, no power is supplied to the load, and the power corresponding to the area S2 is not necessary. When the load is slightly increased from this state, as shown in Fig. 5B, it becomes S1-S2> 0. In this case, electric power corresponding to the difference between the area S1 and the area S2 is supplied to the load. As the load increases, S2 = 0 as shown in Fig. 5C. In this case, the voltage VN of the node N is not negative and power is not wasted.

As described above, although power is consumed even when no power is consumed at the load, reactive power decreases as the load becomes heavy. In the case of setting the lower limit frequency in the DC-DC converter using the conventional PFM control, it is considered to install a bleeder resistor in parallel with the load. The power is always consumed by the bleeder resistor so that the operating frequency does not fall below the lower limit. In this case, even if the load becomes heavy, power is always consumed by the bleeder resistor. In contrast, in the present embodiment, when the load becomes heavy, the reactive power decreases, so that the efficiency can be improved.

In addition, you may apply the voltage generation circuit demonstrated in embodiment mentioned above to a digital amplifier, for example. In addition, the voltage generation circuit described in the above-described embodiments may be applied to a device such as Codec, for example, by being placed in a large-scale integrated circuit (LSI). Such a digital amplifier can be applied to, for example, a mobile phone such as a smart phone.

In addition, in the said embodiment, the input voltage VIN may be in the range of 2.5-4.5V as an example, and 4.2V may be sufficient, for example. In addition, the output voltage VOUT may be, for example, 1.8V. The reference time Tref may be 100 ns, for example. In addition, although the frequency of an audio band is generally known, you may assume the range of 20-20000 Hz, for example.

In addition, about fmin of embodiment mentioned above, a value higher than an audible sound may be sufficient as needed.

100: voltage generating circuit 14: output terminal
TR1, TR2: Transistor L: Choke Coil
C: smoothing capacity 30: error signal generation circuit
40: triangle wave signal generation circuit 50: comparison circuit
60: reset signal generation circuit Z: differential time signal
61: first current source 62: second current source
65: capacitive element 70: differential time signal generation circuit
71: pulse generation circuit 80: drive unit
82: comparator 81: NAND circuit
83: end circuit 84: SR flip-flop
DR1, DR2: Drive signal Err: Error signal
RES: reset signal Vramp: triangle wave signal
CTL: control signal 71a: MaxPon signal.

Claims (7)

A first switching element, an output node and a second switching element connected in series between a high potential power supply and a low potential power supply;
An error signal generator for generating an error signal that is a difference between a detection voltage and a reference voltage according to the voltage of the output node;
A control signal generator for generating a control signal that becomes active for a period corresponding to the magnitude of the error signal;
If the active period of the control signal is longer than the reference time, the first switching element is turned on in the first period from the start of the active period until the reference time elapses, and the active period of the control signal is the reference time. A first driving unit which turns on the first switching element in the active period when it is shorter than the time;
A second driver for controlling the second switching element on or off;
The frequency of the control signal is controlled in a range from a lower limit frequency to an upper limit frequency. When the active period of the control signal is shorter than the reference time, the frequency of the control signal is set as the lower limit frequency, and the active period of the control signal. And a frequency controller for controlling the frequency of the control signal to increase as the time between the active period and the reference time becomes longer when the reference time is longer than the reference time. The method of claim 1,
And the lower limit frequency is higher than an audible band. The method according to claim 1 or 2,
Wherein the second driver comprises:
When the first switching device is switched from on to off, the second switching device is turned on,
The second switching element is turned off at the reference time point when the potential of the output node is lower than the low potential power before the reference time point after the first switching element is turned on,
The voltage generating circuit is turned off when the potential of the output node is lower than the low potential power after the reference time point, when the potential of the output node is lower than the low potential power. . The method according to claim 1 or 2,
The frequency control unit,
A capacitive element,
A comparison unit for comparing the voltage of the capacitor with a predetermined voltage;
A supply unit for supplying current to the capacitor;
A discharge unit for discharging electric charges charged in the capacitor;
Wherein the supply unit includes:
When the active period of the control signal is shorter than the reference time, a current having a predetermined value is supplied to the capacitor,
When the active period of the control signal is longer than the reference time, the difference between the active period and the reference time supplies a current larger than the predetermined value to the capacitive element, and the other time provides a current of the predetermined value. Supplied to the capacitor,
Generating a reset signal for controlling the discharge unit based on a first output signal from the comparison unit, and supplying the reset signal to the control signal generation unit,
And the control signal generator generates the control signal in synchronization with the reset signal. The method according to claim 1 or 2,
A reference signal generator for generating a reference signal inverting a signal that becomes active in the period from the start of the active period of the control signal until the reference time elapses;
Wherein the second driver comprises:
A detection signal generator that detects a period during which the potential of the output node is less than the potential of the low potential power supply and generates a detection signal;
A logic circuit for calculating the logical product of the detection signal and the reference signal;
A signal for controlling the on / off of the first switching element is supplied to a set terminal, a second output signal from the logic circuit is supplied to a reset terminal, and a third output signal is generated to generate a gate of the second switching element. And an SR flip-flop for supplying to the voltage generation circuit. The method of claim 1,
And the first switching element is a P-channel transistor, and the second switching element is an N-channel transistor. A digital amplifier comprising the voltage generation circuit according to claim 1.

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