KR20120111411A - Apparatus for converting resolution - Google Patents

Abstract

PURPOSE: A resolution converting device is provided to change resolution by changing a program of an FPGA even though a desired scaling down ratio changes high. CONSTITUTION: A resolution converting device includes memories(33a,33b) and an FPGA(Field Programmable Gate Array)(32). The memory temporarily stores image data of high resolution. The FPGA outputs representative data in each section corresponding to low resolution among the image data of high resolution while controlling the memory. [Reference numerals] (31) ISP; (32) EPGA; (33a) First memory; (34) LCD module(320X240); (AA) Mega pixel image 1.3M

Description

Apparatus for converting resolution}

The present invention relates to a resolution converting apparatus, and more particularly, to a resolution converting apparatus for converting high resolution video data into low resolution video data.

In general, the resolution of an image obtained by photographing is higher than that of a display module, for example, a liquid crystal display (LCD) module. Moreover, for small display modules added to a piece of equipment, the difference is very large.

Therefore, a general resolution converting apparatus refers to an apparatus for converting high resolution image data into low resolution image data for image reduction.

1 is a block diagram illustrating an example of a conventional resolution converting apparatus.

Referring to FIG. 1, a mega pixel image obtained by photographing, for example, an image of 1.3 mega pixels is signal processed by an image signal processor (ISP) 11.

In addition, the mega pixel image from the ISP 11 is changed to the set image size by the video graphic array (VGA) engine 12.

Here, due to the characteristics of the VGA engine 12, there is a limit to the resolution-reducible ratio. For example, when an image of 1.3 mega pixels is input to a VGA engine 12 through an ISP 11, only one VGA engine 12 may output 320 x 240 pixels. The resolution cannot be output. The problem associated with this is described with reference to FIG.

2 is a block diagram for explaining another example of a conventional resolution converter.

Referring to FIG. 2, a mega pixel image obtained by photographing, for example, an image of 1.3 mega pixels is signal processed by an image signal processor (ISP) 21.

In addition, an image of 1.3 mega pixels from the ISP 21 is first reduced by the first VGA engine 22 to the set image size and the second VGA engine 23. ) Is entered.

In addition, the first reduced image from the first VGA engine 22 is finally changed to a resolution of 320 x 240 pixels by the second VGA engine 23 to display a corresponding display module example. For example, it is input to the LCD module 24.

Therefore, when the VGA engine is typically used as a resolution converting device as described above, as the resolution reduction ratio desired by the user increases, the more expensive VGA engine is used. There is a problem that it is necessary.

An embodiment of the present invention is to provide a resolution conversion device that does not need to add hardware even if the resolution reduction ratio desired by a user is changed.

Furthermore, an embodiment of the present invention is to provide a resolution converting apparatus that does not need to change hardware even if the resolution reduction ratio desired by the user is variously changed.

According to an aspect of the present invention, a resolution converting apparatus for converting high resolution image data into low resolution image data may include a memory and a field programmable gate array (FPGA). The high resolution video data is temporarily stored in the memory. The FPGA outputs representative data for each section corresponding to the low resolution among the high resolution image data temporarily stored in the memory while controlling the operation of the memory.

In addition, the memory may be divided into a first memory and a second memory.

The first memory and the second memory may each be random access memory (RAM).

In addition, each of the first memory and the second memory may be an SDRAM (Synchronous Dynamic Random Access Memory).

In addition, the FPGA may include a first memory controller, a second memory controller, and an image controller. The first memory controller controls an operation of the first memory. The second memory controller controls an operation of the second memory. The image control unit controls the first memory control unit and the second memory control unit to alternate the high resolution image data to the first memory and the second memory through the first memory control unit and the second memory control unit. While storing, the representative data for each section of the high resolution image data stored in the first memory and the second memory are read and output through the first memory controller and the second memory controller.

In addition, the FPGA (FPGA) further comprises a CPU (CPU) interface for communication with an external central processing unit (CPU), the image control unit is the external through the CPU interface (CPU) interface Communicate with the CPU.

The first memory may store the data of the odd frame in the high resolution image data, and the second memory may store the data of the even frame in the high resolution image data. have.

The FFP reads representative data for each section corresponding to the low resolution from among the data of the odd frame stored in the first memory while the second memory stores the data of the even frame. While the first memory stores data of odd-numbered frames, the representative data for each section corresponding to the low resolution may be read and output from the data of even-numbered frames stored in the second memory.

In addition, when the FGA reads and outputs the representative data for each section corresponding to the low resolution from among odd-numbered frames or even-numbered frames, corresponding to the interlace display method, corresponding to the low resolution. Representative data for each section can be read and output twice per frame.

According to an embodiment of the present invention, by using the memory and the FPGA, high resolution image data is converted into low resolution image data. That is, by the programming of the FFP and the memory, high resolution image data may be converted into low resolution image data.

Accordingly, the following effects can be obtained as compared to the VGA engine 12 having a limited resolution-reducible ratio due to its characteristics.

First, even if the resolution reduction ratio desired by the user is changed to high, the program of the FPGA may be changed, so there is no need to add hardware.

Second, even if the resolution reduction ratio desired by the user is variously changed, the program of the FFP may be changed, so there is no need to change the hardware.

1 is a block diagram illustrating an example of a conventional resolution converting apparatus.
2 is a block diagram for explaining another example of a conventional resolution converter.
3 is a block diagram illustrating a resolution converting apparatus according to an embodiment of the present invention.
FIG. 4 is a block diagram illustrating an internal configuration of the FFP of FIG. 3.
FIG. 5 is a timing diagram for describing an operation of the FFP of FIG. 4.

The following description and the annexed drawings are for understanding the operation according to the present invention, and a part that can be easily implemented by those skilled in the art may be omitted.

In addition, the specification and drawings are not provided to limit the invention, the scope of the invention should be defined by the claims. Terms used in the present specification should be interpreted as meanings and concepts corresponding to the technical spirit of the present invention so as to best express the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram for explaining the resolution converting apparatuses 32, 33a, and 33b of one embodiment of the present invention.

In FIG. 3, a mega pixel image obtained by photographing, for example, an image of 1.3 mega pixels is signal-processed by an image signal processor (ISP) 31 to implement an embodiment of the present invention. It is input to the example resolution converters 32, 33a, and 33b.

The resolution converters 32, 33a, and 33b according to the embodiment of the present invention receive a mega pixel image from an ISP 31, for example, an image of 1.3 mega pixels, and has a low resolution. For example, the display is changed to a resolution of 320 x 240 pixels and output to the corresponding display module, for example, the LCD module 34.

Referring to FIG. 3, the resolution converting devices 32, 33a, and 33b according to an embodiment of the present invention are apparatuses for converting high resolution video data into low resolution video data, and include memories 33a and 33b and fPGE. (FPGA: Field Programmable Gate Array, 32).

High-resolution video data is temporarily stored in the memories 33a and 33b.

The FPGA 32 outputs representative data for each section corresponding to the low resolution among the high resolution image data temporarily stored in the memories 33a and 33b while controlling the operations of the memories 33a and 33b. . The method of outputting the representative data for each section in the image data may be derived in various cases. For example, grayscale data of the center pixel for each section or average grayscale data for each section may be representative data for each section.

According to the resolution converting apparatuses 32, 33a, and 33b, by using the memories 33a and 33b and the fPGA 32, high resolution image data is converted into low resolution image data. That is, the high resolution image data may be converted into the low resolution image data by the programming and memories 33a and 33b of the FPGA 32.

Accordingly, the following effects can be obtained as compared to the VGA engine 12 having a limited resolution-reducible ratio due to its characteristics.

First, even if the resolution reduction ratio desired by the user is changed to high, the program of the FFP 32 may be changed, so there is no need to add hardware.

Second, even if the resolution reduction ratio desired by the user is variously changed, the program of the FFP 32 may be changed, so there is no need to change the hardware.

In the present embodiment, the memories 33a and 33b are divided into a first memory 33a and a second memory 33b. In addition, each of the first memory 33a and the second memory is a random access memory (RAM), for example, a synchronous dynamic random access memory (SDRAM).

The internal configuration and operation of the FFP 32 will be described in detail with reference to FIGS. 4 and 5.

FIG. 4 illustrates an internal configuration of the FFP 32 of FIG. 3. In FIG. 4, the same reference numerals as used in FIG. 3 indicate objects of the same function.

3 and 4, the FPGA 32 includes a first memory controller 323a, a second memory controller 323b, and an image controller 321.

The first memory controller 323a controls the operation of the first memory 33a.

The second memory controller 323b controls the operation of the second memory 33b.

The image control unit 321 controls the first memory control unit 323a and the second memory control unit 323b to display high resolution image data through the first memory control unit 323a and the second memory control unit 323b. Representative data for each section among the high resolution image data stored in the first memory 33a and the second memory 33b while being alternately stored in the memory 33a and the second memory 33b are the first memory controller 323a. ) And through the second memory controller 323b.

Meanwhile, in the present embodiment, the FpG 32 further includes a CPU interface 322 for communication with an external central processing unit (CPU). Accordingly, the image control unit 321 communicates with an external central processing unit (CPU) through, for example, an IC (Inter-Integrated Circuit) communication protocol through the CPU interface 322.

Hereinafter, the operation of the fPGA 32 determined by the control and operation of the image controller 321 will be described in detail.

FIG. 5 is a timing diagram for describing an operation of the fPGA 32 of FIG. 4. In FIG. 5, reference numeral 51 indicates a pulse indicating a vertical driving start point in the vertical synchronization signal Vsync of mega pixel image data from the ISP (ISP 31 of FIG. 3). Reference numeral 52 denotes a pulse indicating a start point of vertical driving in the vertical synchronization signal Vsync of the reduced image data output from the image controller 321 to the LCD module. Referring to FIGS. 3 to 5, the operation of the FFP 32 of FIG. 4 will be described.

The fPGA 32, which is controlled and operated by the image controller 321, stores data of odd-numbered frames in the first memory 33a in the high resolution image data (t1 to t5 vertical driving in FIG. 5). Cycle). In addition, the FpG 32 stores data of even-numbered frames in the second memory 33b in the high resolution image data (vertical driving period starting at time t5 of FIG. 5).

Here, the FpG 32 is stored in the first memory 33a while the second memory 33b stores the data of even-numbered frames (a vertical driving period starting at time t5 in FIG. 5). The representative data for each section corresponding to the low resolution of 320 x 240 pixels among the stored odd-numbered frames are read and output to the LCD module 34.

FFP 32 is stored in the second memory 33b while the first memory 33a stores data of odd-numbered frames (t1 to t5 vertical driving cycles in FIG. 5). Representative data for each section corresponding to the low resolution of 320 × 240 pixels among the even-numbered frames is read and output.

As described above, the efficient use of the first memory 33a and the second memory 33b enables fast resolution conversion.

In some cases, the display module, for example, the LCD module 34 may adopt an interlace display method instead of a progressive display method. That is, as shown in FIG. 5, the high resolution image data input to the FPGA 32 is 30 frames per second, and the low resolution to be input to the LCD module 34. Image data may be 60 frames per second (fps).

In this case, when the FG P 32 reads and outputs the representative data for each section corresponding to the low resolution among the data of the odd frame or the even frame, the corresponding display resolution corresponds to the interlace display method. Representative data of each section is read and output twice per frame.

For example, in the t1 to t5 vertical driving cycles of FIG. 5, the representative data for each section corresponding to the low resolution of 320 x 240 pixels among the even-numbered frames stored in the second memory 33b is t2 to t3 time. Is read once and output once during t4 ~ t5 time, and is read twice for one frame.

As described above, according to the embodiment of the present invention, by using the memory and the FPGA, high resolution image data is converted into low resolution image data. That is, high resolution image data may be converted into low resolution image data by programming and memory of FPGA.

Accordingly, the following effects can be obtained as compared to the VGA engine 12 having a limited resolution-reducible ratio due to its characteristics.

First, even if the resolution reduction ratio desired by the user is changed to high, the program of the FPGA may be changed, so there is no need to add hardware.

Second, even if the resolution reduction ratio desired by the user is variously changed, since the program of the FPGA is changed, there is no need to change the hardware.

The present invention has been described above with reference to preferred embodiments. It will be understood by those skilled in the art that the present invention may be embodied in various other forms without departing from the spirit or essential characteristics thereof. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and the inventions claimed by the claims and the inventions equivalent to the claimed invention are to be construed as being included in the present invention.

It may be used not only for image data but also for other digital data.

11,21,31 ... ISP, 12,22,23 ... VGA engine,
24,34 ... LCD module, 32 ... FPGA,
33a ... first memory, 33b ... second memory,
321 image control, 322 CPU interface,
33a ... first memory, 33b ... second memory,
323a ... first memory controller, 323b ... second memory controller,
Vsync ... Vertical sync signal.

Claims (9)

In the resolution converting apparatus for converting high resolution video data into low resolution video data,
A memory for temporarily storing the high resolution image data; And
And a field programmable gate array (FPGA) for outputting representative data for each section corresponding to the low resolution among the high resolution image data temporarily stored in the memory while controlling the operation of the memory. The method of claim 1,
And the memory is divided into a first memory and a second memory. The method of claim 2,
And a first memory and a second memory are random access memory (RAM). The method of claim 3,
And the first memory and the second memory are SDRAMs (Synchronous Dynamic Random Access Memory). The method of claim 2, wherein the FFP (FPGA),
A first memory controller configured to control an operation of the first memory;
A second memory controller which controls an operation of the second memory; And
The first memory controller and the second memory controller are controlled to alternately store high resolution image data in the first memory and the second memory through the first memory controller and the second memory controller. And a video controller for reading the representative data for each section from among the high resolution image data stored in the first memory and the second memory through the first memory controller and the second memory controller. The method of claim 5, wherein the FFP (FPGA),
Further comprising a CPU interface for communication with an external central processing unit (CPU),
And the image control unit communicates with the external central processing unit (CPU) through the CPU interface. The method of claim 2, wherein the FFP (FPGA),
Storing odd-numbered frames of data in the high resolution image data in the first memory,
And an even-numbered frame of the high resolution image data is stored in the second memory. The method of claim 7, wherein the FFP (FPGA),
While the second memory stores the data of the even frame, the representative data for each section corresponding to the low resolution is read and output from the data of the odd frame stored in the first memory,
And resolving the representative data for each section corresponding to the low resolution from among the data of the even frame stored in the second memory while the first memory stores the data of the odd frame. The method of claim 8, wherein the FFP reads and outputs the representative data for each section corresponding to the low resolution among the data of the odd frame or the even frame.
A resolution converting apparatus for reading and outputting the representative data for each section corresponding to the low resolution twice per frame according to an interlace display method.

Images