KR20120111375A - Three dimensional semiconductor memory devices and methods of fabricating the same - Google Patents

Abstract

PURPOSE: A 3D semiconductor memory device and a manufacturing method thereof are provided to minimize the etch loss of the top electrode by covering a first outside will of the top electrode using an extension unit of an electrode-dielectric film. CONSTITUTION: An electrode structure includes electrodes(GSE1,GSE2,CE,SSE2,SSE1) and insulating patterns(505a,505nUa,505Ua). The electrodes are repetitively laminated on a substrate(100). The top electrode among the electrodes has a first outside wall and a second outside wall facing each other. A vertical active pattern(520) passes through the electrode structure. An electrode-dielectric film(570) is interposed between a sidewall of the vertical active pattern and each electrode.

Description

THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a three-dimensional semiconductor memory device and a manufacturing method thereof.

Due to their small size, versatility and / or low manufacturing cost, semiconductor devices are becoming an important element in the electronics industry. As the electronics industry develops, there is an increasing demand for better performance and / or lower cost semiconductor devices. In order to meet these requirements, the trend toward higher integration of semiconductor devices is intensifying. In particular, high integration of semiconductor memory devices for storing logic data is further intensified.

The degree of integration of a conventional two-dimensional semiconductor memory device may act as a main determinant of the planar area occupied by the unit memory cells. As a result, the degree of integration of the two-dimensional semiconductor memory element can be greatly influenced by the level of the fine pattern formation technology. However, the technology of forming fine patterns is approaching the limit, and also, there are problems such as an increase in the manufacturing cost of semiconductor memory devices due to the need for expensive equipment.

In order to overcome these limitations, a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells has been proposed. However, the three-dimensional semiconductor memory device may cause problems such as deterioration in reliability due to its structural shape.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a three-dimensional semiconductor memory device capable of improving reliability and a method of manufacturing the same.

Another object of the present invention is to provide a three-dimensional semiconductor memory device optimized for high integration and a method of manufacturing the same.

Provided are three-dimensional semiconductor memory devices for solving the above technical problem. According to an exemplary embodiment, a three-dimensional semiconductor memory device includes an electrode structure including electrodes and insulating patterns alternately and repeatedly stacked on a substrate, and a top electrode among the electrodes may include a first outer wall and a second outer wall facing each other. Having; A vertical active pattern penetrating the electrode structure; And an electrode-dielectric film interposed between the sidewalls of the vertical active pattern and the electrodes. At least a portion of the electrode-dielectric film between the top electrode and the vertical active pattern may extend to cover the bottom surface, the top surface, and the first outer wall of the top electrode. The wall portion of the extension of the electrode-dielectric film covering the first outer wall of the uppermost electrode may have sidewalls aligned with one outer wall of the uppermost insulating pattern disposed on the uppermost electrode.

According to another embodiment, a three-dimensional semiconductor memory device includes an electrode structure including electrodes and insulating patterns alternately and repeatedly stacked on a substrate, each electrode including a metal pattern and a barrier conductive pattern; A vertical active pattern penetrating the electrode structure; And an electrode-dielectric film interposed between the sidewalls of the vertical active pattern and the electrodes. The uppermost metal pattern included in the uppermost electrode among the electrodes has a first outer wall and a second outer wall facing each other, and the uppermost barrier conductive pattern included in the uppermost electrode includes a bottom surface, an upper surface, and the first layer of the uppermost metal pattern. 1 may be in contact with the outer wall. A portion of the uppermost barrier conductive pattern in contact with the first outer wall of the uppermost metal pattern may have sidewalls aligned with one outer wall of the uppermost insulating pattern disposed on the uppermost electrode.

Provided are a method of manufacturing a three-dimensional semiconductor memory device for solving the above technical problems. The method includes alternately and repeatedly stacking sacrificial films and insulating films on a substrate; Successively patterning at least the top insulating film and the top sacrificial film to form a cutting region; Forming a non-sacrificial film in contact with the entirety of both inner walls of the cutting region; Forming vertical active patterns penetrating the insulating layers and the sacrificial layers; Successively patterning the insulating layers and the sacrificial layers to form a mold pattern including insulating patterns, sacrificial patterns, and a non-sacrificial layer in the cutting region; Removing the sacrificial patterns to form empty regions; Forming electrodes in the empty areas, respectively; And forming an electrode-dielectric film between sidewalls of the vertical active pattern and the electrodes.

According to the above-mentioned three-dimensional semiconductor memory element, the first outer wall of the top electrode can be covered by an extension of the electrode-dielectric film. As a result, the first outer wall of the uppermost electrode may be protected from an etching process or the like. As a result, the etching loss of the top electrode may be minimized to prevent the resistance of the top electrode from increasing. As a result, a three-dimensional semiconductor memory device having excellent reliability and optimized for high integration can be realized.

1A is a plan view showing a three-dimensional semiconductor memory device according to an embodiment of the present invention.
1B is a cross-sectional view taken along the line II ′ of FIG. 1A;
1C is a cross-sectional view taken along II-II 'of FIG. 1A;
FIG. 1D is an enlarged view of a portion K1 of FIG. 1B. FIG.
1E is an enlarged view of a portion K2 of FIG. 1B.
FIG. 2A is a cross-sectional view taken along the line II ′ of FIG. 1A to illustrate one modification of the three-dimensional semiconductor memory device according to the embodiment of the present invention; FIG.
FIG. 2B is an enlarged view of a portion K3 of FIG. 2A;
FIG. 3A is a cross-sectional view taken along the line II ′ of FIG. 1A to illustrate another modification of the three-dimensional semiconductor memory device according to the embodiment of the present invention; FIG.
3B is an enlarged view of a portion K4 of FIG. 3A.
4 is a cross-sectional view taken along the line II ′ of FIG. 1A in order to explain another modification of the three-dimensional semiconductor memory device according to the embodiment of the present invention;
Fig. 5A is a plan view showing another modification of the three-dimensional semiconductor memory device according to the embodiment of the present invention.
FIG. 5B is a sectional view taken along the line II ′ of FIG. 5A;
6 is a cross-sectional view showing still another modification of the three-dimensional semiconductor memory device according to the embodiment of the present invention.
Fig. 7A is a sectional view showing still another modification of the three-dimensional semiconductor memory device according to the embodiment of the present invention.
FIG. 7B is an enlarged view of a portion K5 of FIG. 7A.
8A to 12A are plan views illustrating a method of manufacturing a 3D semiconductor memory device according to an embodiment of the present invention.
8B-12B are cross sectional views taken along the line II ′ of FIGS. 8A-12A, respectively.
Fig. 13 is a sectional view for explaining a modification of the method of manufacturing the three-dimensional semiconductor memory device according to the embodiment of the present invention.
14A and 15A are plan views illustrating another modification of the method of manufacturing the three-dimensional semiconductor memory device according to the embodiment of the present invention.
14B and 15B are cross sectional views taken along the line II ′ of FIGS. 14A and 15A, respectively.
Fig. 16 is a sectional view for explaining another modification of the method for manufacturing the three-dimensional semiconductor memory device according to the embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate or a third film between them. In addition, in the drawings, sizes, thicknesses, etc. of components are exaggerated for clarity. It should also be understood that although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., It should not be. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. The expression 'and / or' is used herein to include at least one of the components listed before and after. Portions denoted by like reference numerals denote like elements throughout the specification.

1A is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the present invention, FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. 1A, and FIG. 1C is a cross-sectional view taken along the line II-II ′ of FIG. 1A. to be. FIG. 1D is an enlarged view of a portion K1 of FIG. 1B, and FIG. 1E is an enlarged view of a portion K2 of FIG. 1B.

1A, 1B, and 1C, an electrode structure may be disposed on a semiconductor substrate 100 (hereinafter, referred to as a substrate). The electrode structure may include electrodes GSE1, GSE2, CE, SSE2, and SSE1 and alternating patterns 505a, 505nUa, and 505Ua that are alternately and repeatedly stacked. A plurality of the electrode structures may be disposed on the substrate 100. As shown in FIG. 1A, the electrode structures may extend side by side in a first direction, and the electrode structures may be spaced apart from each other in a second direction perpendicular to the first direction. The first direction and the second direction may correspond to the y-axis direction and the x-axis direction of FIG. 1A, respectively. An isolation pattern 575 may be disposed between the adjacent electrode structures. That is, a pair of device isolation patterns 575 may be disposed on both sides of each electrode structure. The device isolation patterns 575 may also extend side by side in the first direction in a plan view. The device isolation pattern 575 may include an oxide, nitride, and / or oxynitride.

The electrodes GSE1, GSE2, CE, SSE2, and SSE1 in each electrode structure may include a plurality of cell electrodes CE that are sequentially stacked. In addition, the electrodes GSE, GSE2, CE, SSE2, and SSE1 in each electrode structure may include at least one layer interposed between the lowermost cell electrode and the substrate 100 among the cell electrodes CE. The at least one floor may include ground selection electrodes GSE1 and GSE2. According to an embodiment, a first ground selection electrode GSE1 may be disposed between the lowest cell electrode and the substrate 100, and a second ground selection electrode GSE2 may be selected between the lowest cell electrode and the first ground selection. It may be interposed between the electrodes GSE1. However, the present invention is not limited thereto. One layer of ground selection electrode or three or more layers of ground selection electrodes may be interposed between the lowermost cell electrode and the substrate 100. In each of the electrode structures, the first ground select electrode GSE1 may be one, and the second ground select electrode GSE2 may also be one. Similarly, in each electrode structure, each cell electrode CE disposed on each of the floors may be one. For example, in each of the electrode structures, the lowest cell electrode may be one, and in each of the electrode structures, there may also be one of the highest cell electrodes of the cell electrodes CE.

The electrodes GSE1, GSE2, CE, SSE1, and SSE2 in each electrode structure may include a plurality of first string select electrodes SSE1. The plurality of first string select electrodes SSE1 are positioned at the same level from an upper surface of the substrate 100. The plurality of first string select electrodes SSE1 are laterally spaced apart. The plurality of first string select electrodes SSE1 may extend in parallel in the first direction. The plurality of first string select electrodes SSE1 may be controlled independently of each other. In each of the electrode structures, the plurality of first string selection electrodes SSE1 may be disposed over one of the topmost cell electrodes. Therefore, in each of the electrode structures, the plurality of first string selection electrodes SSE1 may be disposed on one first ground selection electrode GSE1. The cell electrodes CE that are sequentially stacked may be interposed between the plurality of first string select electrodes SSE1 and the first ground select electrode GSE1.

Each electrode structure may include at least one layer of string selection electrode SSE1. That is, each of the electrode structures may include a single layer of string selection electrodes SSE1 or a plurality of layers of string selection electrodes SSE2 and SSE1 that are sequentially stacked and spaced apart from each other. For example, a second string select electrode SSE2 may be disposed between each of the first string select electrodes SSE1 and the uppermost cell electrode. The second string select electrodes SSE2 disposed under the first string select electrodes SSE1 may be located at the same level from the upper surface of the substrate 100. In addition, the second string select electrodes SSE2 are laterally spaced apart. The second string select electrodes SSE2 may be controlled independently of each other.

The first ground selection electrode GSE1 corresponds to a lowermost electrode among the electrodes GSE1, GSE2, CE, SSE2, and SSE1 stacked in each electrode structure, and the first string selection electrode SSE1 corresponds to each electrode. It corresponds to the highest electrode among the stacked electrodes GSE1, GSE2, CE, SSE2, and SSE1 in the structure. The second string selection electrode SSE2 corresponds to a next uppermost electrode among the electrodes GSE1, GSE2, CE, SSE2, and SSE1 stacked in the electrode structure.

The insulating patterns 505a, 505nUa, and 505Ua of each electrode structure may include a top insulating pattern 505Ua disposed on the first string select electrode SSE1, the first and second string select electrodes SSE1, The next higher insulating pattern 505nUa between the SSE2 and the insulating patterns 505a may be insulated from the cell electrodes CE and the ground selection electrodes GSE1 and GSE2.

The topmost insulating patterns 505Ua may be provided in plurality, and the plurality of topmost insulating patterns 505Ua may be disposed on the plurality of first string selection electrodes SSE1, respectively. The plurality of topmost insulating patterns 505Ua may be spaced apart from each other. The plurality of topmost insulating patterns 505Ua may be positioned at the same level from an upper surface of the substrate 100. In addition, a plurality of the next higher insulation patterns 505 nUa may be provided. Each of the next higher insulating patterns 505nUa may be disposed between each of the second string select electrodes SSE2 and the first string select electrodes SSE1 that are sequentially stacked. The plurality of next higher insulating patterns 505nUa may also be positioned at the same level from the top surface of the substrate 100 and may be spaced apart from each other.

In each of the electrode structures, a cutting region 540 may be defined between the uppermost insulating patterns 505Ua. The cutting region 540 extends downward, and may be defined between the first string select electrodes SSE1, between the next higher insulating patterns 505nUa, and between the second string select electrodes SSE2. have. The cutting area 540 may have a groove shape extending in the first direction in a plan view. A non-sacrificial pattern 550a may be disposed in the cutting area 540. In example embodiments, the non-sacrificial pattern 550a may be in contact with one outer sidewall of the uppermost and next higher insulating patterns 505Ua and 505nUa that form one inner sidewall of the cutting area 540.

In example embodiments, the first string selection electrode SSE1 may be disposed in a topmost empty region 560U surrounded by the topmost insulating pattern 505Ua, the next higher insulating pattern 505nUa, and the non-sacrificial pattern 550a. . The second string selection electrode SSE2 is in the next higher blank area 560nU surrounded by the next higher insulating pattern 505nUa, the insulating pattern 505a directly below the second upper insulating pattern 505nUa, and the non-sacrificial pattern 550a. Can be arranged. One side of the top and next uppermost empty regions 560U and 560nU may be closed by the non-sacrificial pattern 550a. The cell electrodes CE and the ground select electrodes GSE1 and GSE2 may be disposed in the empty regions 560 defined between the insulating patterns 505a positioned below the next higher insulating pattern 505nUa. have.

The electrodes GSE1, GSE2, CE, SSE2, and SSE1 include a conductive material. For example, the electrodes GSE1, GSE2, CE, SSE2, and SSE1 may be formed of a doped semiconductor (ex, doped silicon, etc.), a metal (ex, tungsten, copper, aluminum, etc.), a conductive metal nitride (ex, nitride, etc.). Titanium, tantalum nitride, tungsten nitride, etc.), conductive metal-semiconductor compounds (ex, metal silicides, etc.), transition metals (ex, titanium, tantalum, etc.), and the like. The insulating patterns 505a, 505nUa and 505Ua may include an oxide (eg, a high density plasma oxide and / or a high temperature oxide). The non-sacrificial pattern 550a may include an insulating material. The high temperature oxide may be an oxide formed at a process temperature higher than about 600 ° C. For example, the non-sacrificial pattern 550a may include an oxide and / or an undoped semiconductor (ex, undoped silicon, etc.). However, the present invention is not limited thereto. The non-sacrificial pattern 550a may include another insulating material.

In example embodiments, a buffer dielectric pattern 503a may be interposed between the first string select electrode SSE1 and the substrate 100. The buffer dielectric pattern 503a may be thinner than the insulating patterns 505a, 505nUa, and 505Ua. The buffer dielectric pattern 103a may include an oxide or the like.

Vertical active patterns 520 may vertically penetrate the electrode structure. Each vertical active pattern 520 continuously penetrates the first string selection electrode SSE1 and the electrodes SSE2, CE, GSE1, and GSE2 stacked under each of the first string selection electrode SSE1. can do. The vertical active pattern 520 may be in the form of a hollow pipe or macaroni. In this case, the filling dielectric pattern 525 may fill a space surrounded by the vertical active pattern 520. Landing pads 530 may be disposed on the vertical active pattern 520 and the filling dielectric pattern 525. The landing pad 530 may be in contact with the vertical active pattern 520.

The vertical active pattern 520 may be in contact with the substrate 100. The substrate 100 may be doped with a dopant of a first conductivity type. For example, the substrate 100 may include a doped well region of a first conductivity type. The vertical active pattern 520 may be in contact with the well region. The vertical active pattern 520 may include the same semiconductor material as the substrate 100. For example, when the substrate 100 is a silicon substrate, the vertical active pattern 520 may include silicon. The vertical active pattern 520 may be in a single crystal state or a polycrystalline state. The vertical active pattern 520 may be doped or undoped with the first conductive dopant. The landing pad 530 may include the same semiconductor material as the vertical active pattern 520. A drain region doped with a dopant of a second conductivity type may be formed in at least the landing pad 530. The filling dielectric pattern 525 may include an oxide, nitride, and / or oxynitride.

The plurality of vertical active patterns 520 may pass through the first string selection electrode SSE1 and the electrodes SSE2, CE, GSE1, and GSE2 stacked below. In a plan view, the vertical active patterns 520 passing through each of the first string selection electrodes SSE1 may be arranged in a zigzag shape in the first direction. However, the present invention is not limited thereto. The vertical active patterns 520 passing through each of the first string selection electrodes SSE1 may be arranged in the first direction to form one column.

An electrode-dielectric film 570 may be interposed between the sidewall of the vertical active pattern 520 and the electrodes GSE1, GSE2, CE, SSE2, and SSE1. In an embodiment, at least a portion of the electrode-dielectric film 570 may extend to cover the top and bottom surfaces of the electrodes GSE1, GSE2, CE, SSE2, and SSE1. In this case, at least a portion of the electrode-dielectric film 570 between the vertical active pattern 520 and the first string selection electrode SSE1 is further extended to form a lower surface and an upper surface of the first string selection electrode SSE1. And one outer wall. According to an embodiment, as shown in FIG. 1B, the entirety of the electrode-dielectric film 570 between the vertical active pattern 520 and each of the electrodes GSE1, GSE2, CE, SSE2, and SSE1 may extend. .

The string selection electrodes SSE1 and SSE2 will be described in more detail with reference to FIG. 1D.

1B and 1D, the first string select electrode SSE1 may include a first outer wall 10a and a second outer wall 10b facing each other. In this case, the electrode-dielectric film 570 between the vertical active pattern 520 and the first string selection electrode SSE1 extends to form a bottom surface, an upper surface, and the first surface of the first string selection electrode SSE1. The outer wall 10a may be covered. An extended portion of the electrode-dielectric film 570 positioned between the vertical active pattern 520 and the first string selection electrode SSE1 is defined as a first extension portion. The first extension part may contact the bottom surface, the top surface and the first outer wall 10a of the first string selection electrode SSE1. The first extension part may include first plate parts covering lower and upper surfaces of the first string select electrode SSE1, and a first wall portion covering the first outer wall 10a. have. The first wall portion may include a first sidewall 31 adjacent to the non-sacrificial pattern 550a and a second sidewall adjacent to the first outer wall 10a. In example embodiments, the first sidewall 31 of the first wall portion may be in contact with the non-sacrificial pattern 550a.

The first extension part may not cover the second outer wall 10b of the first string select electrode SSE1. According to an embodiment, the first outer wall 10a of the first string selection electrode SSE1 may be adjacent to the first non-sacrificial pattern 550a, and the second of the first string selection electrode SSE1 may be in contact with each other. The outer wall 10b may be in contact with the device isolation pattern 575. The first string selection electrode SSE1 may include an inner wall 10n adjacent to a sidewall of the vertical active pattern 520. An inner wall 10n of the first string selection electrode SSE1 may have a hole shape surrounding a sidewall of the vertical active pattern 520.

The uppermost insulating pattern 505Ua may include a first outer wall 15a and a second outer wall 15b facing each other. The first outer wall 15a of the uppermost insulating pattern 505Ua may be in contact with the non-sacrificial pattern 550a. The second outer wall 15b of the uppermost insulating pattern 505Ua may be in contact with the device isolation pattern 575. The first outer wall 15a of the uppermost insulating pattern 505Ua may be aligned with the first sidewall 31 of the first wall portion covering the first outer wall 10a of the first string selection electrode SSE1. . According to an embodiment, the first outer wall 15a of the topmost insulating pattern 505Ua may be substantially coplanar with the first sidewall 31 of the first wall portion.

Similarly, the second string select electrode SSE2 may include a first outer wall 20a and a second outer wall 20b facing each other. The first outer wall 20a of the second string select electrode SSE2 may be adjacent to the non-sacrificial pattern 550a, and the second outer wall 20b of the second string select electrode SSE2 may be separated from the device. May be adjacent to pattern 575. An electrode-dielectric film 570 between the vertical active pattern 520 and the second string select electrode SSE2 extends to form a bottom surface, an upper surface, and a first outer wall 20a of the second string select electrode SSE2. ) Can be covered. A portion in which the electrode-dielectric film 570 extends between the vertical active pattern 520 and the second string select electrode SSE2 is defined as a second extension part. The second extension part may contact the bottom surface, the top surface and the first outer wall 20a of the second string select electrode SSE2. The second extension part may include second plate parts covering lower and upper surfaces of the second string select electrode SSE2, and a second wall part covering the first outer wall 20a. The second wall portion of the second extension part may include a first sidewall 32 adjacent to the non-sacrificial pattern 550a and a second sidewall adjacent to the first outer wall 20a of the second string select electrode SSE2. Can be. The first sidewall 32 of the second wall portion may contact the non-sacrificial pattern 550a. The second outer wall 20b of the second string select electrode SSE2 may not be covered by the second extension part. The second outer wall 20b of the second string select electrode SSE2 may be in contact with the device isolation pattern 575. The second string selection electrode SSE2 may also include an inner wall 20n adjacent to the sidewall of the vertical active pattern 520. The inner wall 20n of the second string select electrode SSE2 may have a hole shape surrounding a sidewall of the vertical active pattern 520.

The next higher insulating pattern 505nUa may also include a first outer wall 25a in contact with the non-sacrificial pattern 550a and a second outer wall 25b adjacent to the device isolation pattern 575. The first outer wall 25a of the next higher insulating pattern 505nUa may be aligned with the first sidewall 32 of the second wall portion. The first sidewall 32 of the second wall portion may be substantially coplanar with the first outer wall 25a of the next higher insulating pattern 505nUa.

According to one embodiment, the first outer wall 15a of the topmost insulating pattern 505Ua may include a first sidewall 31 of the first wall portion, a first outer wall 25a of the next higher insulating pattern 505nUa, and It may be substantially coplanar with the first side wall 32 of the second wall portion.

Subsequently, referring to FIG. 1B, each of the cell electrodes CE may also include a first outer wall 40a and a second outer wall 40b that face each other, and each of the ground selection electrodes GSE1 and GSE2 may also be disposed. The first outer wall 45a and the second outer wall 45b may be opposite to each other. Unlike the string selection electrodes SSE1 and SSE2, the first and second outer walls 40a and 40b of each cell electrode CE may have device isolation patterns 575 disposed on both sides of the electrode structure. Each can be contacted. In addition, the first and second outer walls 45a and 45b of the ground selection electrodes GSE1 and GSE2 may also be in contact with the device isolation patterns 575 disposed on both sides of the electrode structure. Each cell electrode CE includes inner walls that respectively surround sidewalls of the vertical active patterns 520 that pass through the plurality of first string selection electrodes SSE1 included in each electrode structure. can do. In addition, the ground selection electrodes GSE1 and GSE2 may also include inner walls that respectively surround sidewalls of the vertical active patterns 520 that pass through the plurality of first string selection electrodes SSE2, respectively. Can be.

The electrode-dielectric film 570 will be described in more detail with reference to FIG. 1E.

1B and 1E, the electrode-dielectric film 570 may include a tunnel dielectric film TDL, a charge storage layer SL, and a blocking dielectric film BDL. The tunnel dielectric layer TDL is adjacent to the vertical active pattern 520, and the blocking dielectric layer BDL is adjacent to the electrodes GSE1, GSE2, CE, SSE2, and SSE1. The charge storage layer SL is interposed between the tunnel dielectric layer TDL and the blocking dielectric layer BDL. The tunnel dielectric layer TDL may include an oxide layer and / or an oxynitride layer. The charge storage layer SL may include a dielectric layer having traps capable of storing charge. For example, the charge storage layer TDL may include a nitride layer and / or a metal oxide layer (eg, a hafnium oxide layer). The blocking dielectric layer BDL may include a high dielectric layer (eg, a metal oxide layer such as a hafnium oxide layer and / or an aluminum oxide layer) having a higher dielectric constant than the tunnel dielectric layer TDL. In addition, the blocking dielectric layer BDL may further include a barrier dielectric layer (eg, an oxide layer, etc.) having an energy band gap larger than the energy band gap of the high dielectric layer. The barrier dielectric layer may be interposed between the high dielectric layer and the charge storage layer SL.

1A to 1E, an extension of the electrode-dielectric film 570 covering the top and bottom surfaces of each of the electrodes GSE1, GSE2, CE, SSE2, and SSE1 may extend in the tunnel. Extension portions of the dielectric layer TDL, the charge storage layer SL, and the blocking dielectric layer BDL may be included. In addition, the tunnel dielectric layer TDL, the charge storage layer SL, and the blocking dielectric layer may also be formed in the first and second wall portions covering the first outer walls 10a and 20a of the string selection electrodes SSE1 and SSE2. Extensions of the BDL).

1A, 1B, and 1C, a common source region CS may be disposed in the substrate 100 between the electrode structures. The common source region CS may be doped with a dopant of the second conductivity type. That is, the common source region CS may be doped with a type of dopant different from that of the well region. Each common source region CS may be disposed under each device isolation pattern 575.

As illustrated in FIGS. 1A and 1C, each of the electrodes GSE1, GSE2, CE, SSE2, and SSE1 stacked in the electrode structure may have an electrode pad EP. The electrode pads EP of the stacked electrodes GSE1, GSE2, CE, SSE2, and SSE1 may be implemented in a stepped structure. The electrode pads EP of the stacked electrodes GSE1, GSE2, CE, SSE2, and SSE1 may have a downhill staircase structure in the first direction. Operating voltages may be provided to the electrodes GSE1, GSE2, CE, SSE2, and SSE1 through the electrode pads EP. For example, an operating voltage may be provided to the electrodes GSE, GSE1, CE, SSE2, and SSE1 through conductive plugs (not shown) connected to the electrode pads EP.

One vertical cell string may be implemented in each of the vertical active patterns 520. The vertical cell string may include cell transistors connected in series, at least one ground select transistor connected in series to one end of the series connected cell transistors, and at least one string connected in series to the other end of the series connected cell transistors. It may include a selection transistor. When the vertical cell string includes a plurality of the ground select transistors, the ground select transistors in the vertical cell string may be connected in series. Similarly, when the vertical cell string includes a plurality of string select transistors, string select transistors in the vertical cell string may also be connected in series.

Each cell transistor may be defined at an intersection point of the vertical active pattern 520 and the cell electrode CE. The ground select transistors may be defined at intersections of the vertical active pattern 520 and the ground select electrodes GSE1 and GSE2, respectively. The string select transistors may be defined at intersections of the vertical active pattern 520 and the string select electrodes SSE1 and SSE2, respectively. An electrode-dielectric film 570 between each cell electrode CE and the vertical active pattern 520 may correspond to an information storage film of the cell transistor. The electrode-dielectric film 570 between each of the string selection electrodes SSE1 and SSE2 and the vertical active pattern 520 may correspond to a gate dielectric layer of the string selection transistor, and each of the ground selection electrodes GSE1 and GSE2. And the electrode-dielectric layer 570 between the vertical active patterns 520 may correspond to the gate dielectric layer of the ground selection transistor. The ground, cell and string select transistors in the vertical cell string may be stacked in turn, and the ground, cell and string select transistors in the vertical cell string may be vertically defined on sidewalls of the vertical active patterns 520. Each of the channel regions may be included. In operation of a 3D semiconductor memory device, inversion layers are formed next to the insulating patterns 505a, 505nUa and 505Ua by the fringe field of each of the electrodes GSE1, GSE2, CE, SSE2 and SSE1. A portion of the sidewall of the vertical active pattern 520 positioned at may be generated. The inversion layers may correspond to sources / drains of the ground, cell, and string select transistors.

1A, 1B, and 1C, a capping dielectric pattern 535a may be disposed on the topmost insulating patterns 505a. In addition, the capping dielectric pattern 535a may be disposed on the electrode pads EP in each electrode structure. Both outer walls of the capping dielectric pattern 535a may be in contact with device isolation patterns 575 disposed on both sides of the electrode structure. The cutting region 540 may extend upward to penetrate the capping dielectric pattern 535a. As illustrated in FIG. 1A, the electrode pads EP of the second string selection electrodes SSE2 may be disposed on both sides of the cutting region 540, and may be spaced apart from each other. End portions of the cutting region 540 may overlap electrode pads EP of the cell electrodes CE or electrode pads of the ground selection electrodes GSE1 and GSE2. The non-sacrificial pattern 550a may also extend upward to fill the cutting area 540. An upper surface of the non-sacrificial pattern 550a may be substantially coplanar with an upper surface of the capping dielectric pattern 535a. The capping dielectric pattern 535a may include an oxide (eg, a high density plasma oxide and / or a high temperature oxide).

A plurality of wires 590 may be disposed on the capping dielectric pattern 535a. The wires 590 may extend side by side in the second direction. Each wire 590 may be electrically connected to upper ends of the plurality of vertical active patterns 520 arranged along the second direction to form one row. The wiring 590 may be electrically connected to an upper end of the vertical active pattern 520 via the contact plug 580 and / or the landing pad 530 passing through the capping dielectric pattern 535a. The wiring 590 may be electrically connected to at least the drain formed in the landing pad 530. The wires 590 may correspond to bit lines. The wires 590 may be formed of a metal (ex, tungsten, copper, aluminum, etc.), a conductive metal nitride (ex, titanium nitride, tantalum nitride, tungsten nitride, etc.), or a transition metal (ex, titanium, tantalum, etc.). It may include at least one. The contact plugs 580 may be made of metal (ex, tungsten, copper, aluminum, etc.), conductive metal nitride (ex, titanium nitride, tantalum nitride, tungsten nitride, etc.), or transition metal (ex, titanium, tantalum, etc.). It may include at least one.

According to the three-dimensional semiconductor memory element described above, the first outer walls 10a and 20a of the string selection electrodes SSE1 and SSE2 are covered by the electrode-dielectric film 570. As a result, the first outer walls 10a and 20a of the string selection electrodes SSE1 and SSE2 may be protected from an etching process or the like. As a result, the string selection electrodes SSE1 and SSE2 may have excellent electrical characteristics. As a result, a three-dimensional semiconductor memory device having excellent reliability and optimized for high integration can be realized.

Next, modifications of the three-dimensional semiconductor memory device according to the embodiment of the present invention will be described with reference to the drawings.

FIG. 2A is a cross-sectional view taken along the line II ′ of FIG. 1A in order to describe a modification of the three-dimensional semiconductor memory device according to the embodiment of the present invention, and FIG. 2B is an enlarged view of a portion K3 of FIG. 2A.

2A and 2B, the electrode-dielectric film 570a between the sidewall of the vertical active pattern 520 and each electrode GSE1, GSE2, CE, SSE2, and SSE1 may be formed of a first portion 565a and a second portion. It may include portion 565b. The first portion 565a of the electrode-dielectric film 570a may extend vertically and be interposed between the sidewall of the vertical active pattern 520 and the insulating patterns 505a, 505nUa, and 505Ua. . The second portion 565b of the electrode-dielectric film 570a may extend to cover lower and upper surfaces of the electrodes GSE1, GSE2, CE, SSE2, and SSE1. As shown in FIG. 2B, the second portion 565b of the electrode-dielectric film 570a between the sidewall of the vertical active pattern 520 and the inner wall 10n of the first string select electrode SSE1 is extended. The lower surface, the upper surface, and the first outer wall 10a of the first string selection electrode SSE1 may be covered. A portion of the extension of the second portion 565a covering the first outer wall 10a of the first string selection electrode SSE1 may be a sidewall aligned with the first outer wall 15a of the uppermost insulating pattern 505Ua. It may have (31a). The sidewall 31a may be substantially coplanar with the first outer wall 15a of the uppermost insulating pattern 505Ua.

The second portion 565b of the electrode-dielectric film 570a between the sidewall of the vertical active pattern 520 and the inner wall 20n of the second string select electrode SSE2 extends to extend the second string select electrode. The lower surface, the upper surface and the first outer wall 10a of the SSE2 may be covered. A portion of the extension of the second portion 565a covering the first outer wall 20a of the second string select electrode SSE2 is one sidewall aligned with the first outer wall 25a of the next higher insulating pattern 505nUa. It may have (32a). The sidewall 32a may be substantially coplanar with the first outer wall 25a of the next higher insulating pattern 505nUa.

The first portion 565a of the electrode-dielectric film 570a may include at least a portion of the tunnel dielectric film TDL described with reference to FIG. 1E. The second portion 565b of the electrode-dielectric film 570a may include at least a portion of the blocking dielectric film BDL described with reference to FIG. 1E. In this case, any one of the first portion 565a and the second portion 565b includes the charge storage layer SL described with reference to FIG. 1E. For example, the first portion 565a may include the tunnel dielectric layer TDL, the charge storage layer SL, and the barrier dielectric layer of the blocking dielectric layer BDL. It may include a high dielectric film of the blocking dielectric film (BDL). However, the present invention is not limited thereto. The first portion 565a and the second portion 565b of the electrode-dielectric film 570a may be configured in other forms.

3A is a cross-sectional view taken along the line II ′ of FIG. 1A in order to explain another modified example of the three-dimensional semiconductor memory device according to the embodiment of the present invention, and FIG. 3B is an enlarged view of a portion K4 of FIG. 3A.

Referring to FIGS. 3A and 3B, both the sidewall of the vertical active pattern 520 and the electrode-dielectric film 570 ′ between each electrode GSE1k, GSE2k, CEk, SSE2k and SSE1k extend vertically to extend the vertical. The sidewalls of the active pattern 520 and the insulating patterns 505a, 505nUa, and 505Ua may be interposed. In this case, each of the electrodes GSE1k, GSE2k, CEk, SSE2k, and SSE1k may include a metal pattern 80, 80nU or 80U and a barrier conductive pattern 85, 85nU or 85U.

In each of the electrodes GSE1k, GSE2k, CEk, SSE2k, and SSE1k, the barrier conductive patterns 85, 85nU, or 85U may contact the bottom and top surfaces of the metal patterns 80, 80nU, or 80U. The metal pattern 80U and the barrier conductive pattern 85U included in the first string selection electrode SSE1k are defined as the top metal pattern 80U and the top barrier conductive pattern 85U, respectively. As shown in FIG. 3B, the uppermost metal pattern 80U may include a first outer wall 50a and a second outer wall 50b facing each other. First and second outer walls 50a and 50b of the uppermost metal pattern 80U may be adjacent to the non-sacrificial pattern 550a and the device isolation pattern 575, respectively. The uppermost barrier conductive pattern 85U may contact the first outer wall 50a of the uppermost metal pattern 80U. A portion of the uppermost barrier conductive pattern 85U in contact with the first outer wall 50a of the uppermost metal pattern 80U may include a first sidewall 55 adjacent to the non-sacrificial pattern 550a and the uppermost metal pattern. And a second sidewall in contact with the first outer wall 50a of 80U. The first sidewall 55 of the portion of the uppermost barrier conductive pattern 85U may be aligned with the first outer wall 15a of the uppermost insulating pattern 505Ua. The first sidewall 55 of the portion of the uppermost barrier conductive pattern 85U may be substantially coplanar with the first outer wall 15a of the uppermost insulating pattern 505a. The second outer wall 50b of the uppermost metal pattern 80U may not be covered by the uppermost barrier conductive pattern 85U. The second outer wall 50b of the uppermost metal pattern 80U may contact the device isolation pattern 575. The uppermost metal pattern 80U may include an inner wall 50n having a hole shape surrounding a sidewall of the vertical active pattern 520. The uppermost barrier conductive pattern 85U may also contact the inner side wall 50n of the uppermost metal pattern 80U.

Similarly, the metal pattern 80nU and the barrier conductive pattern 85nU included in the second string select electrode SSE2k are defined as the next higher metal pattern 80nU and the next higher barrier conductive pattern 85nU. The next higher metal pattern 80nU may also include a first outer wall 60a and a second outer wall 60b facing each other. The next higher barrier conductive pattern 85nU may contact the first outer wall 60a of the next upper metal pattern 80nU. A portion of the next higher barrier conductive pattern 85nU in contact with the first outer wall 60a of the next higher metal pattern 80nU may include a first sidewall 56 adjacent to the non-sacrificial pattern 550a and the next upper metal pattern. It may include a second side wall in contact with the first outer wall (60a) of (80nU). The first sidewall 56 of the portion of the next higher barrier conductive pattern 85nU may be aligned with the first outer wall 25a of the next higher insulating pattern 505nUa. The first sidewall 56 of the portion of the next higher barrier conductive pattern 85nU may be substantially coplanar with the first outer wall 25a of the next higher insulating pattern 505nUa. The second outer wall 60b of the next higher metal pattern 80nU may not be covered by the next upper barrier conductive pattern 85nU. The second outer wall 60b of the next higher metal pattern 80nU may contact the device isolation pattern 575. The next higher metal pattern 80nU may also include a hole-shaped inner wall 60n surrounding the sidewall of the vertical active pattern 520. The next higher barrier conductive pattern 85nU may also contact the inner wall 60n of the next upper metal pattern 80nU.

Unlike the string selection electrodes SSE1k and SSE2k, as illustrated in FIG. 3A, both outer sidewalls of each of the metal patterns 80 of the cell electrodes CEk and the ground selection electrodes GSE1k and GSE2k, Each of the cell electrodes CEk and the ground selection electrodes GSE1k and GSE2k may not be covered by the barrier conductive pattern 85. For example, both outer walls of each of the metal patterns 80 of the cell electrodes CEk and the ground selection electrodes GSE1k and GSE2k may be in contact with device isolation patterns 575 disposed on both sides of the electrode structure. have.

The metal patterns 80, 80nU, and 80U may include tungsten, copper, aluminum, or the like. The barrier conductive patterns 85, 85nU, and 85U may include conductive metal nitrides (eg, titanium nitride, tantalum nitride, tungsten nitride, etc.) and / or transition metals (ex, titanium, tantalum, etc.).

FIG. 4 is a cross-sectional view taken along the line II ′ of FIG. 1A to explain another modified example of the three-dimensional semiconductor memory device according to the embodiment of the present invention.

Referring to FIG. 4, the non-sacrificial pattern 550a ′ may fill the cutting region 540. The non-sacrificial pattern 550a ′ may extend to be disposed on an upper surface of the capping dielectric pattern 535a. In this case, the non-sacrificial pattern 550a 'may include sidewalls aligned with both sidewalls of the capping dielectric pattern 535a. In this case, the contact plug 580 ′ continuously penetrates through the portion of the non-sacrificial pattern 550a ′ positioned on the capping dielectric pattern 535a and the capping dielectric pattern 535a to prevent the landing pad 530. ) Can be connected. An upper surface of the device isolation pattern 575 may be substantially coplanar with an upper surface of the non-sacrificial pattern 550a '.

FIG. 5A is a plan view showing another modified example of the three-dimensional semiconductor memory device according to the embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along the line II ′ of FIG. 5A.

5A and 5B, in plan view, the ends of the top surfaces of the non-sacrificial patterns 550b disposed in the cutting region 540a are the ends of the top surfaces of the first string select electrodes SSE1 and the above. It may be aligned in the first direction. In this case, as disclosed in FIG. 5B, the top surface of the non-sacrificial pattern 550b may be substantially coplanar with the top surfaces of the topmost insulating patterns 505Ua. The capping dielectric pattern 535a ′ may be disposed on the topmost insulating patterns 505Ua and the non-sacrificial pattern 550b. That is, the cutting region 540a may be disposed under the capping dielectric pattern 535a '.

6 is a cross-sectional view showing still another modification of the three-dimensional semiconductor memory device according to the embodiment of the present invention.

Referring to FIG. 6, the cutting region 540 ′ may further extend downward. The non-sacrificial pattern 550a may fill the cutting region 540 ′. Each electrode structure may include a plurality of topmost cell electrodes CEs by the cutting region 540 ′ and the non-sacrificial pattern 550a. The plurality of top cell electrodes CEs may be positioned at the same level from the top surface of the substrate 100. The cutting region 540 ′ and the non-sacrificial pattern 550a may be disposed between the plurality of top cell electrodes CEs. That is, the plurality of top cell electrodes CEs may be separated by the cutting region 540 'and the non-sacrificial pattern 550a.

According to the present modified example, each of the topmost cell electrodes CEs may include a first outer wall 41a adjacent to the non-sacrificial pattern 550a and a second outer wall 41b adjacent to the device isolation pattern 575. Can be. In this case, the electrode-dielectric film 570 positioned between the sidewall of the vertical active pattern 520 and the top cell electrode CEs may extend to cover the first outer wall 41a of the top cell electrode CEs. have. The second outer wall 41b of the uppermost cell electrode CEs may not be covered by an extension of the electrode-dielectric film. For example, the second outer wall 41b of the uppermost cell electrode CEs may be in contact with the device isolation pattern 575. According to the present modification, the top cell electrodes CEs are separated from each other by the cutting region 540 '. However, the present invention is not limited thereto. The cutting region 540 ′ may extend further below the top cell electrodes CEs. Thus, at least one of the cell electrodes CE disposed under the top cell electrodes CEs may be separated into a plurality of segments. In addition, the cutting region 540 ′ is further extended such that each of the cell electrodes CE and the ground select electrodes GSE1 and GSE2 below the top cell electrodes CEs is divided into a plurality of segments. May be

FIG. 7A is a cross-sectional view illustrating still another modified example of the three-dimensional semiconductor memory device according to the embodiment of the present invention, and FIG. 7B is an enlarged view of a portion K5 of FIG. 7A.

Referring to FIGS. 7A and 7B, the topmost empty area 560U ′ may extend laterally toward the non-sacrificial pattern 550a. Accordingly, the width of the first string selection electrode SSE1 in the uppermost empty region 560U 'may be increased. That is, the horizontal distance between the first outer wall 10a ′ and the second outer wall 10b of the first string selection electrode SSE1 may be increased. Accordingly, the first sidewall 31 ′ of the first wall portion of the first extension part covering the first outer wall 10a ′ of the first string select electrode SSE1 may be the first outer wall 15a of the uppermost insulating pattern 505Ua. May be offset from For example, the first sidewall 31 ′ of the first wall portion may protrude laterally than the first outer wall 15a of the uppermost insulating pattern 505Ua. As described above with reference to FIGS. 1A and 1D, the first extension means an extended portion of the electrode-dielectric film interposed between the sidewall of the vertical active pattern 520 and the first string select electrode SSE1. do.

Similarly, the next higher blank area 560nU 'may also extend laterally toward the non-sacrificial pattern 550a. As a result, the width of the second string selection electrode SSE2 in the next higher blank area 560nU 'may be increased. The first sidewall 32 'of the second wall portion of the second extension portion covering the first outer wall 20a' of the second string select electrode SSE2 is next to the first outer wall 25a of the next higher insulating pattern 505nUa. Can protrude.

In example embodiments, the non-sacrificial pattern 550a may include a dielectric material having an etching selectivity with respect to the insulating patterns 505a, 505nUa and 505Ua. In example embodiments, an etch rate of the non-sacrificial pattern 550a may be greater than an etch rate of the insulating patterns 505a, 505nUa and 505Ua. For example, the insulating patterns 505a, 505nUa, and 505Ua may include high density plasma oxide and / or high temperature oxide, and the non-sacrificial pattern 550a may include low temperature oxide and / or PE-CVD oxide (ie, PE). Oxides formed by CVD), and the like. The low temperature oxide may be an oxide formed at a process temperature of about room temperature to about 600 ℃. However, the present invention is not limited thereto. The non-sacrificial pattern 550a and the insulating patterns 550a, 505nUa, and 505Ua may be formed of other dielectric materials.

The top and next top empty regions 560U 'and 560nU' according to the present modification can be applied to the three-dimensional semiconductor memory device disclosed in FIGS. 3A and 3B. In this case, the widths of the first and second string select electrodes SSE1k and SSE2k of FIGS. 3A and 3B may be increased. For example, in FIGS. 3A and 3B, the first sidewalls 55, 56 of the portions of the top and second top barrier conductive patterns 85U and 85nU are the first outer walls of the top and next top insulating patterns 505Ua and 505nUa. It may be offset from the (15a, 25a). First sidewalls 55 and 56 of portions of the top and second top barrier conductive patterns 85U and 85nU may face the first and second top insulating patterns 505Ua and 505nUa toward the non-sacrificial pattern 550a. It may protrude laterally than the outer walls 15a and 25a.

Next, a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings.

8A to 12A are plan views illustrating a method of manufacturing a 3D semiconductor memory device according to an exemplary embodiment of the present invention, and FIGS. 8B to 12B are cross-sectional views taken along line II ′ of FIGS. 8A to 12A, respectively. .

8A and 8B, a buffer dielectric layer 503 may be formed on the substrate 100 doped with a first conductivity type dopant. A well region doped with a dopant of a first conductivity type may be formed in the substrate 100. Sacrificial layers 510, 510nU and 510U and insulating layers 505, 505nU and 505U may be alternately and repeatedly stacked on the buffer dielectric layer 503. The top insulating layer 505U may be disposed on the top sacrificial layer 510U. A next higher insulating layer 505nU may be disposed between the highest sacrificial layer 510U and the next higher sacrificial layer 510nU. The sacrificial layers 510, 510nU, and 510U may be formed of a material having an etch selectivity with respect to the insulating layers 505, 505nU, and 505U. For example, each of the insulating films 505, 505 nU, and 505U may be formed of an oxide film (eg, a high density plasma oxide film and / or a high temperature oxide film, etc.), and each of the sacrificial films 510, 510 nU, and 510U may be formed. It can be formed as a nitride film.

The insulating layers 505, 505nU and 505U and the sacrificial layers 510, 510nU and 510U may be patterned to form sacrificial pads 510P of the sacrificial layers 510, 510nU and 510U. For example, a mask pattern defining a sacrificial pad 510P of the lowest sacrificial layer is formed among the sacrificial layers 510, 510nU, and 510U, and the insulating layers 505, 505nU, and 505U are formed using the mask pattern as an etching mask. And the sacrificial layers 510, 510nU, and 510U may be etched. As a result, the sacrificial pad 510P of the lowest sacrificial layer may be formed. Subsequently, the mask pattern may be recessed to reduce the width of the mask pattern. The sacrificial layers 510, 510nU and 510U and the insulating layers 505, 505nU and 505U on the lowest sacrificial layer may be etched using the recessed mask pattern as an etching mask. As a result, the sacrificial pad 510P of the sacrificial layer 510 stacked second from the substrate 100 may be formed, and the sacrificial pad 510P of the lowest sacrificial layer may be exposed. The sacrificial pads 110P having a stepped structure may be repeatedly formed by repeatedly performing the recess process of the mask pattern and the etching process of the insulating layers 505, 505 nU and 505U and the sacrificial layers 510, 510 nU and 510U. Can be formed.

Holes 515 may be formed through the insulating layers 505, 505 nU and 505U, the sacrificial layers 510, 510 nU and 510U, and the buffer dielectric layer 503. A vertical active pattern 520, a charging dielectric pattern 525, and a landing pad 530 may be formed in each hole 515. Subsequently, a capping dielectric layer 535 may be formed to cover the entire surface of the substrate 100. The capping dielectric layer 535 may include a dielectric material having an etch selectivity with respect to the sacrificial layers 510, 510nU, and 510U. For example, the capping dielectric layer 535 may be formed of an oxide layer or the like.

9A and 9B, the capping dielectric layer 535, at least a top insulating layer 505U, and at least a top sacrificial layer 510U may be successively patterned to form a cutting region 540. In example embodiments, the cutting region 540 may sequentially pattern the capping dielectric layer 535, the top insulating layer 505U, the top sacrificial layer 510, the next top insulating layer 505nU, and the next top sacrificial layer 510nU. It can be formed by doing. As illustrated in FIG. 9A, the cutting region 540 may separate the sacrificial pads 510P of the top and next top sacrificial layers 510U and 510nU. In plan view, the end of the cutting region 540 may overlap any one of the sacrificial pads 510P of the sacrificial layers replaced with the cell electrodes or the string selection electrodes.

The non-sacrificial film 550 in contact with the inner surface of the cutting region 540 may be formed on the entire surface of the substrate 100. The non-sacrificial layer 550 may fill the cutting region 540. The non-sacrificial layer 550 may be in contact with all of the inner sidewalls of the cutting region 540. A portion of the non-sacrificial layer 550 in contact with at least both inner walls of the cutting region 540 may include an insulating material having an etch selectivity with respect to the sacrificial layers 510, 510 nU, and 510U. have. According to one embodiment, at least a portion of the non-sacrificial layer 550 in contact with both inner walls of the cutting region 540 is less than 10% of the etching rate of the sacrificial layers 510, 510nU, and 510U. It may include an insulating material having a small etching rate. For example, when the sacrificial films 510, 510nU, and 510U are formed of nitride films, the non-sacrificial film 550 is formed of an oxide film and / or an undoped semiconductor film (eg, an undoped silicon film, etc.). Can be.

10A and 10B, the non-sacrificial layer 550 may be planarized until the capping dielectric layer 535 is exposed to form a non-sacrificial pattern 550a. Thus, the top surface of the non-sacrificial pattern 550a may be substantially coplanar with the top surface of the capping dielectric layer 535.

Subsequently, trenches 555 may be formed by successively patterning the capping dielectric layer 535, the insulating layers 505, 505 nU and 505U, and the sacrificial layers 510, 510 nU and 510U. The trenches 555 may extend side by side in the first direction in a plan view. Mold patterns may be formed by the trenches 555. Each mold pattern may be formed between a pair of adjacent trenches 555. In addition, the cutting region 540 is disposed between the adjacent pair of trenches 555. The mold patterns may be completely separated by the trenches 555. Each mold pattern may include sacrificial patterns 510a, 510nUa and 510Ua and insulating patterns 505a, 505nUa and 505Ua that are alternately and repeatedly stacked. In addition, each mold pattern may further include the cutting region 540 and the non-sacrificial pattern 550a. Thus, each mold pattern may include a plurality of topmost insulating patterns 505Ua separated by the cutting region 540. In addition, each mold pattern may include a plurality of top sacrificial patterns 510Ua separated by the cutting area 540. Similarly, each mold pattern may include a plurality of next higher insulating patterns 505 nUa and next second sacrificial patterns 510 nUa. In the area under the cutting area 540 of each mold pattern, one sacrificial pattern 510a may be disposed at each level.

Since the mold patterns are completely separated by the trenches 555, the sacrificial pads 510P of the sacrificial patterns 510a, 510nUa, and 510Ua of each mold pattern may be sacrificial pads of the sacrificial patterns of a neighboring mold pattern. Can be separated from. Each mold pattern may further include a capping dielectric pattern 535a. The capping dielectric pattern 535a may cover top insulating patterns 505Ua and sacrificial pads 510P in each mold pattern.

When the trenches 555 are formed, the buffer dielectric layer 503 may also be etched to form a buffer dielectric pattern 503a. Alternatively, at least a portion of the buffer dielectric layer 503 may remain under the trench 555.

11A and 11B, empty areas 560, 560nU, and 560U may be formed by removing the sacrificial patterns 510a, 510nUa, and 510Ua exposed to the trenches 555. Topmost empty regions 560U and next upper empty regions 560nU disposed on both sides of the non-sacrificial pattern 550a may be formed. Due to the non-sacrificial pattern 550a, one side of the topmost empty area 560U may be in a closed state. By the trench 555, the other side of the non-sacrificial pattern 550a may be in an opened state. Similarly, one side of the next higher blank area 560nU adjacent to the non-sacrificial pattern 550a may be closed, and the other side of the next higher blank area 560nU adjacent to the trench 555 may be open. have. Both sides of each of the blank areas 560 below the cutting area 540 may be in an open state.

12A and 12B, an electrode-dielectric film 570 may be conformally formed on the substrate 100 having the empty regions 560, 560nU, and 560U. The electrode-dielectric film 570 may be formed to have a substantially uniform thickness on inner surfaces of the empty regions 560, 560nU, and 560U.

Subsequently, a conductive film may be formed on the substrate 100 having the electrode-dielectric film 570 to fill the empty regions 560, 560 nU, and 560U. Electrodes GSE1, GSE2, CE, SSE2, and SSE1 may be formed in the empty regions 560, 560nU, and 560U by removing conductive layers outside the empty regions 560, 560nU, and 560U. have. As a result, the electrode structure described with reference to FIGS. 1A to 1E can be formed. After forming the electrodes GSE1, GSE2, CE, SSE2, and SSE1, the electrode-dielectric film 570 outside the empty regions 560, 560nU, and 560U may be removed.

The common source region CS may be formed by implanting dopant ions of the second conductivity type into the substrate 100 under each trench 555. The common source region CS may be formed after forming the electrodes GSE1, GSE2, CE, SSE2, and SSE1. Alternatively, the common source region CS may be formed before forming the empty regions 560, 560nU, and 560U.

Subsequently, device isolation patterns (575 of FIGS. 1A to 1E) may be formed to fill the trenches 555, respectively. Subsequently, the contact plugs 580 and the wirings 590 of FIGS. 1A to 1C may be formed. As a result, the three-dimensional semiconductor memory device disclosed in FIGS. 1A to 1E can be implemented.

According to the method of manufacturing the 3D semiconductor memory device described above, after the cutting region 540 is formed and the non-sacrificial layer 550 is formed, the trenches 555 are formed to form the sacrificial patterns 510a, 510nUa and 510Ua are formed, and the empty regions 560, 560nU and 560U are formed. That is, the topmost empty regions 560U and the next higher empty regions 560nU separated by the non-sacrificial pattern 550a are formed. As a result, the first string select electrodes SSE1 and the second string select electrodes SSE2 separated from each other in the respective electrode structures may include the cell electrodes CE and the ground select electrodes GSE1 and GSE2. And may be formed substantially simultaneously.

As a result, the first outer walls of the first and second string select electrodes SSE1 and SSE2 adjacent to the non-sacrificial pattern 550a are protected from an etching process. The resistance of the string select electrodes SSE1 and SSE2 may be reduced by minimizing the loss due to the etching process of the first and second string select electrodes SSE1 and SSE2. As a result, a three-dimensional semiconductor memory device having excellent reliability and optimized for high integration can be realized.

13 is a cross-sectional view for explaining a modification of the method of manufacturing the three-dimensional semiconductor memory device according to the embodiment of the present invention.

Before forming the vertical active pattern 520 illustrated in FIGS. 8A and 8B, a first portion 565a of the electrode-dielectric film may be formed on the inner wall of each hole 515. Thereafter, the methods described with reference to FIGS. 9A through 11A and 9B through 11B may be performed. As a result, as shown in FIG. 13, empty regions 560, 560nU, and 560U may be formed. The empty regions 560, 560nU, and 560U of FIG. 13 may expose the first portion 565a of the electrode-dielectric film formed on the sidewall of the vertical active pattern 520. Subsequently, a second portion (565b of FIGS. 2A and 2B) of an electrode-dielectric film is formed on an inner surface of the empty regions 560, 560nU, and 560U, and the empty regions 560, 560nU, and 560U are respectively formed. Filling electrodes GSE1, GSE2, CE, SSE2, and SSE1 may be formed. Thereby, the electrode structure disclosed in FIGS. 2A and 2B can be formed.

Meanwhile, before forming the vertical active pattern 520 of FIGS. 8A and 8B, the electrode-dielectric film 570 ′ of FIGS. 3A and 3B may be formed on the inner wall of each hole 515. . Subsequently, the manufacturing methods described with reference to FIGS. 9A through 11A and 9B through 11B may be performed. In this case, the empty regions 560, 560nU, and 560U may expose the electrode-dielectric film 570 ′ formed on the sidewall of the vertical active pattern 520. After the barrier conductive film is conformally formed in the empty regions 560, 560nU and 560U, a metal film may be formed to fill the empty regions 560, 560nU and 560U. Subsequently, the barrier conductive layer and the metal layer outside the empty regions 560, 560nU, and 560U may be removed to form the electrodes GSE1k, GSE2k, CEk, SSE2k, and SSE1k of FIGS. 3A and 3B. As a result, the electrode structure described with reference to FIGS. 3A and 3B can be formed.

In the forming methods described with reference to FIGS. 9A, 9B, 10A, and 10B, the non-sacrificial film 550 may not be planarized. Thereafter, by performing the forming methods described with reference to FIGS. 11A, 11B, 12A, and 12B, the three-dimensional semiconductor memory device disclosed in FIG. 4 can be implemented.

According to the manufacturing method described with reference to FIGS. 8A to 12A and 8B to 12B, after the sacrificial pads 510P are formed, the cutting region 540 and the non-sacrificial film 550 may be formed. . Alternatively, the sacrificial pads 510P may be formed after the cutting region 540 and the non-sacrificial layer 550 are formed. This will be described with reference to the drawings.

14A and 15A are plan views illustrating another modified example of a method of manufacturing a 3D semiconductor memory device according to an exemplary embodiment of the present invention, and FIGS. 14B and 15B illustrate II ′ of FIGS. 14A and 15A, respectively. Are cross-sectional views taken along.

14A and 14B, before forming the sacrificial pads, the top insulating layer 505U, the top sacrificial layer 510U, the next top insulating layer 505nU, and the next top sacrificial layer 510nU are successively patterned to form a cutting region ( 540 may be formed. A non-sacrificial film in contact with the inner surface of the cutting region 540 may be formed, and the non-sacrificial film may be patterned to form a non-sacrificial pattern 550a.

15A and 15B, after the non-sacrificial pattern 550a is formed, the insulating layers 505U, 505nU and 505 and the sacrificial layers 510U, 510nU and 510 are patterned to form sacrificial pads ( 510P). At this time, the end portion of the non-sacrificial pattern 550a may be etched together in a plan view. Thus, as shown in FIG. 15B, the end portion of the etched non-sacrificial pattern 550b may have a stepped structure. As shown in FIG. 15A, an end of the top surface of the etched non-sacrificial pattern 550b may be aligned with the end of the top sacrificial layer 510U having the sacrificial pad 510P. Subsequent subsequent processes may be performed in the same manner as described with reference to FIGS. 10A to 12A and 10B to 12B. As a result, the 3D semiconductor memory device described with reference to FIGS. 5A and 5B may be implemented.

Meanwhile, at the time of forming the cutting region 540 illustrated in FIGS. 9A and 9B, at least one sacrificial layer 510 positioned under the bottom surface of the cutting region 540 may be further etched. As a result, the cutting region may penetrate through the top and second sacrificial layers 510U and 510nU and at least one sacrificial layer 510 positioned below the next top sacrificial layer 510nU. Thereafter, the non-sacrificial film 550 may be formed, and the methods described with reference to FIGS. 10A to 12A and 10B to 12B may be performed. As a result, a three-dimensional semiconductor memory device including the cutting region 540 'disclosed in FIG. 6 may be implemented.

16 is a cross-sectional view for illustrating another modification of the method of manufacturing the 3D semiconductor memory device according to the embodiment of the present invention.

When removing the sacrificial patterns 510a, 510nUa, and 510Ua disclosed in FIGS. 10A and 10B, portions of the non-sacrificial pattern 550a next to the top and next sacrificial patterns 510Ua and 510nUa may be recessed. Can be. As a result, the highest empty region 560U ', the next higher empty region 560nU', and the empty regions 560 may be formed. In this case, the non-sacrificial pattern 550a may include a dielectric material having an etch selectivity with respect to the sacrificial patterns 510a, 510nUa, and 510Ua. In addition, the non-sacrificial pattern 550a may include a dielectric material having an etch selectivity with respect to the insulating patterns 505a, 505nUa, and 505Ua.

In example embodiments, in the process of removing the sacrificial patterns 510a, 510nUa, and 510Ua, the etch rates of the sacrificial patterns 510a, 510nUa, and 510Ua may be greatest, and the insulating patterns 505a may be used. In this case, the etch rate of the non-sacrificial pattern 550a is smaller than that of the sacrificial patterns 510a, 510nUa, and 510Ua and the insulating patterns 505a. , 505nUa, 505Ua). For example, the sacrificial patterns 510a, 510nUa, and 510Ua may be formed of nitride, and the insulating patterns 505a, 505nUa, and 505Ua may be formed of high density plasma oxide and / or high temperature oxide. Pattern 550a may be formed of low temperature oxide and / or PE-CVD oxide. The low temperature oxide may be an oxide formed at a process temperature of about room temperature to about 600 ℃.

Thereafter, the methods described with reference to FIGS. 12A and 12B may be performed. As a result, the 3D semiconductor memory device described with reference to FIGS. 7A and 7B may be implemented.

As mentioned above, although embodiments of the present invention have been described with reference to the accompanying drawings, the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. It is therefore to be understood that the above-described embodiments are illustrative and non-restrictive in every respect.

Claims (10)

An electrode structure comprising electrodes and insulating patterns alternately and repeatedly stacked on a substrate, wherein an uppermost electrode of the electrodes has a first outer wall and a second outer wall facing each other;
A vertical active pattern penetrating the electrode structure; And
An electrode-dielectric film interposed between the sidewalls of the vertical active pattern and the respective electrodes, wherein at least a portion of the electrode-dielectric film between the top electrode and the vertical active pattern extends to form a bottom surface of the top electrode; Covering the upper surface and the first outer wall,
And a wall portion of the extension portion of the electrode-dielectric film covering the first outer wall of the uppermost electrode has sidewalls aligned with one outer wall of the uppermost insulating pattern disposed on the uppermost electrode. The method according to claim 1,
And the outer side wall of the uppermost insulating pattern is coplanar with the side wall of the wall portion of the extension portion of the electrode-dielectric film. The method according to claim 1,
An extension of said at least a portion of said electrode-dielectric film does not cover said second outer wall of said uppermost electrode. The method according to claim 1,
Further comprising a pair of device isolation patterns respectively disposed on both sides of the electrode structure,
The second outer wall of the uppermost electrode is in contact with any one of the pair of device isolation patterns,
And outer sidewalls of the lowest electrode among the electrodes are in contact with the pair of device isolation patterns, respectively. The method according to claim 1,
The electrode structure comprises one lowermost electrode,
The top electrode is provided in plurality on the bottom electrode, wherein the plurality of top electrodes are laterally spaced apart and located at the same level from the top surface of the substrate,
And a plurality of vertical active patterns, wherein each vertical active pattern penetrates the top electrode and the electrodes stacked below the top electrode. The method according to claim 1,
The electrode-dielectric film includes a tunnel dielectric film, a charge storage layer, and a blocking dielectric film,
An extension of the electrode-dielectric film covering the first outer wall of the top electrode includes at least a portion of the blocking dielectric film. An electrode structure comprising electrodes and insulating patterns alternately and repeatedly stacked on a substrate, each electrode comprising a metal pattern and a barrier conductive pattern;
A vertical active pattern penetrating the electrode structure; And
An electrode-dielectric film interposed between the sidewalls of the vertical active pattern and the electrodes,
The uppermost metal pattern included in the uppermost electrode among the electrodes has a first outer wall and a second outer wall facing each other, and the uppermost barrier conductive pattern included in the uppermost electrode includes a bottom surface, an upper surface, and the first layer of the uppermost metal pattern. 1 is in contact with the outer wall,
And a portion of the uppermost barrier conductive pattern in contact with the first outer wall of the uppermost metal pattern has sidewalls aligned with one outer wall of the uppermost insulating pattern disposed on the uppermost electrode. The method of claim 7,
And the outer wall of the uppermost insulating pattern is coplanar with the sidewall of the portion of the uppermost barrier conductive pattern in contact with the first outer wall of the uppermost metal pattern. The method of claim 7,
And the second outer wall of the uppermost metal pattern is not in contact with the uppermost barrier conductive pattern. Alternately and repeatedly stacking sacrificial films and insulating films on the substrate;
Successively patterning at least the top insulating film and the top sacrificial film to form a cutting region;
Forming a non-sacrificial film in contact with the entirety of both inner walls of the cutting region;
Forming vertical active patterns penetrating the insulating layers and the sacrificial layers;
Successively patterning the insulating layers and the sacrificial layers to form a mold pattern including insulating patterns, sacrificial patterns, and a non-sacrificial layer in the cutting region;
Removing the sacrificial patterns to form empty regions;
Forming electrodes in the empty areas, respectively; And
Forming an electrode-dielectric film between the sidewalls of the vertical active pattern and the respective electrodes.

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