KR20120110601A - Liquid crystal display device and method of driving the same - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a driving method thereof are provided to effectively implement a narrow bezel by reducing the number of components comprising a common voltage supply unit. CONSTITUTION: A plurality of common wirings is corresponded to a plurality of gate wirings. The common wiring is extended parallel to the gate wiring. A timing controller generates a gate control signal. The gate control signal controls the gate wiring and the common wiring. A gate driving unit successively selects the common wiring. The gate driving unit outputs an AC common voltage as a common voltage. A common voltage supply unit(420) includes first to sixth transistors(T1-T6) and first and second capacitors(C1,C2).

Description

Liquid crystal display device and method of driving the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Recently, liquid crystal displays (LCDs), plasma display panels (PDPs), organic fields Various flat panel displays (FPDs) such as organic light emitting diodes (OLEDs) are being used.

As shown in FIG. 1, the liquid crystal display device 1 includes a liquid crystal panel 2, a timing controller 3 as a driving circuit part, a gate driver 4, a data driver 5, and a common voltage supply part. And (6).

In the liquid crystal panel 2, a plurality of data wirings DL and a plurality of gate wirings GL1, GL2, ... cross each other to define a plurality of pixels P, and also a plurality of common wirings CL1, CL2,... ) Extends in parallel with the plurality of gate wirings GL1, GL2, ....

Although not illustrated, the thin film transistor is formed at the intersection of each of the plurality of gate lines GL1, GL2,..., And the plurality of data lines DL.

The timing controller 3 generates a gate control signal GS for controlling the gate driver 4 and a data control signal DS for controlling the data driver 5.

In addition, a common voltage control signal CS for controlling the common voltage supply unit 6 is generated separately from the gate control signal GS and transferred to the common voltage supply unit 6.

It demonstrates with reference to FIG. 2 is a waveform diagram of voltages applied to the first and second gate lines GL1 and GL2 and the first and second common lines CL1 and CL2.

As shown in FIG. 2, the first and second gate lines GL1 and GL2 are sequentially selected to apply a high level gate voltage Vgh for turning on the thin film transistor. In other words, a high level gate voltage Vgh is applied during one horizontal period 1H during one frame 1F period, and a low level gate voltage Vgl for turning off the thin film transistor is applied during the other period.

In this case, the first and second common lines CL1 and CL2 must maintain a constant voltage for one frame regardless of the period during which the high level gate voltage is applied to the corresponding gate lines GL1 and GL2. Specifically, for example, the common voltage of positive polarity (+) is maintained for one frame on the first common wiring, and the common voltage of negative polarity (-) is maintained for one frame on the second common wiring.

This is because the polarity of the common voltages applied to the first and second common lines CL1 and CL2 must be inverted for the line inversion driving method and maintained until the data of the next frame is output.

That is, for the line inversion scheme, the first and second common lines CL1 and CL2 may be used for one frame regardless of the period during which the high level gate voltage is applied to the first and second gate lines GL1 and GL2. Maintain polarity of common voltage.

Therefore, in order to control the common voltage supply unit 6 separately from the gate control signal GS, a separate control signal CS must be generated.

Accordingly, the number of components for generating the common voltage control signal CS is increased, thereby increasing the production cost. As illustrated in FIG. 3, the space required by the increase of the components in design is required. It is difficult to implement a narrow bezel.

In addition, as an integrated chip (IC) supporting the common voltage inversion is required, a control signal separate from the clock controlling the gate driver 4 may be required.

In addition, since the polarity of the common voltage must be inverted every one horizontal period from the positive polarity (+) to the negative polarity (−) for the line inversion driving, there is a problem in that the current consumption due to the polarity inversion of the common voltage increases.

There is a problem to provide a liquid crystal display and a driving method thereof for driving the common voltage supply in response to a gate control signal without a separate control signal for controlling the common voltage supply.

In addition, the narrow bezel can be efficiently achieved by reducing the number of components for constructing the common voltage supply unit. For the line inversion method, a voltage applied by an alternating current without using polarity inversion of the common voltage is used. There is a problem to provide a liquid crystal display device and a driving method thereof which can be reduced.

In order to achieve the above object, the present invention, a plurality of gate wiring; A plurality of common wirings corresponding to and extending in parallel to the plurality of gate wirings; A timing controller configured to generate gate control signals for controlling the plurality of gate lines and the plurality of common lines; A gate driver configured to sequentially select the plurality of common wires in response to the gate control signal, and output an AC common voltage having a high potential voltage and a low potential voltage alternately in the selected common line every one horizontal period as a common voltage; It provides a liquid crystal display device comprising.

The gate driver outputs a ground voltage as the common voltage to the plurality of common lines until the next frame is scanned.

The gate driver may sequentially select the plurality of gate wirings in response to the gate control signal, and output a gate voltage to the selected gate wirings, and the plurality of common wirings in response to the gate control signal. Sequentially selecting and outputting the common voltage to the selected common wiring.

The common voltage supply unit includes a buffer unit sequentially outputting the AC common voltage to the plurality of common wires corresponding to the gate high voltage, and a bootstrapping unit boosting the gate high voltage.

The common voltage supply unit includes first to sixth transistors, first and second capacitors, a gate start pulse, a gate low voltage, a gate shift clock, a first signal transmitted from the gate voltage supply unit, and the AC common voltage and the And a terminal for receiving a ground voltage and a terminal for outputting the common voltage, wherein the terminal for receiving the gate start pulse is connected to a gate electrode and a drain electrode of the first transistor, and a gate electrode of the fourth transistor. The terminal receiving the gate shift clock is connected to the drain electrode of the third transistor, and the terminal receiving the first signal is connected to the gate electrodes of the second and sixth transistors, and transmits the gate low voltage. The receiving terminal is a source electrode of the second and fourth transistors and a second electrode of the second capacitor The terminal for receiving the AC common voltage is connected to the drain electrode of the fifth transistor, The terminal for receiving the ground voltage is connected to the source electrode of the sixth transistor, and the terminal for outputting the common voltage A source electrode of the fifth transistor and a drain electrode of the sixth transistor, wherein the source electrode of the first transistor is a drain electrode of the second transistor, a gate electrode of the third transistor, and a first of the first capacitor; The source electrode of the third transistor is connected to the drain electrode of the fourth transistor and the second electrode of the first capacitor.

A liquid crystal display device driving method for outputting a common voltage to a plurality of gate lines and a plurality of common lines corresponding to and extending in parallel with the plurality of gate lines, the method comprising: generating a gate control signal; Sequentially selecting the plurality of common wires in response to the gate control signal; A method of driving a liquid crystal display device comprising the step of outputting, as the common voltage, an AC common voltage having alternating high potential voltage and low potential voltage every one horizontal period on the selected common wiring.

The ground voltage is output as the common voltage to the plurality of common wires until the next frame is scanned.

And sequentially selecting the plurality of gate wirings in response to the gate control signal, and outputting a gate high voltage to the selected gate wirings.

The step of outputting the AC common voltage as the common voltage may include boosting the gate high voltage; And sequentially outputting the AC common voltage to the plurality of common wires in response to the output of the boosted gate high voltage.

Since the common voltage supply unit is driven in response to the gate control signal, it is not necessary to generate a separate control signal for controlling the common voltage supply unit. Accordingly, the number of parts for configuring the common voltage supply unit can be reduced, thereby reducing the production cost and efficiently achieving the narrow bezel.

In addition, for the line inversion driving method, a voltage applied to an alternating current without an inversion of the polarity of the common voltage is used, thereby providing an effect of reducing power consumption.

1 is a schematic cross-sectional view showing a conventional liquid crystal display device.
2 is a waveform diagram of a common voltage applied to drive a line inversion scheme in a conventional liquid crystal display.
3 is a cross-sectional view of a conventional common voltage supply unit.
4 is a schematic cross-sectional view of a liquid crystal display device according to an exemplary embodiment of the present invention.
5 is a cross-sectional view schematically showing a gate driver according to an embodiment of the present invention.
6A and 6B illustrate polarities of data appearing on a liquid crystal panel during line inversion driving.
7 is a waveform diagram of a data voltage and a common voltage applied during line inversion driving.
8 is a waveform diagram illustrating, as an example, a voltage applied to first and second gate wirings and first and second common wirings according to an embodiment of the present invention;
9 is an internal circuit diagram of a gate voltage supply unit according to an embodiment of the present invention.
10 is an internal circuit diagram of a common voltage supply unit according to an embodiment of the present invention.
11A is a waveform diagram illustrating, as an example, a voltage applied to a first gate line and a first common line according to an embodiment of the present invention;
11B is a waveform diagram illustrating, as an example, a voltage applied to a second gate line and a second common line according to an embodiment of the present invention.
12 is a schematic view showing a current flow of a buffer unit of a common voltage supply unit according to an exemplary embodiment of the present invention.
13 is a schematic view showing a current flow of a bootstrapping section of a common voltage supply unit according to an embodiment of the present invention;
14 is a cross-sectional view of a common voltage supply unit according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

4 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown, the liquid crystal display device 100 according to the embodiment of the present invention includes a liquid crystal panel 200, a driving circuit unit 1000, and a backlight 800.

In the liquid crystal panel 200, a plurality of gate wirings GL1 to GLn extend in a first direction, for example, in a row direction. The plurality of data wirings DL1 to DLm extend in the second direction, for example, the column direction, which intersects the first direction. As described above, the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm that cross each other define a plurality of pixels P arranged in a matrix form.

Each pixel P includes a thin film transistor T, a liquid crystal capacitor Clc, and a storage capacitor Cst.

The thin film transistor T is formed at the intersection of each of the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. The pixel electrode (not shown) is connected to the thin film transistor T. Meanwhile, a common electrode (not shown) is formed to correspond to the pixel electrode. When a data voltage is applied to the pixel electrode and a common voltage is applied to the common electrode, an electric field is formed therebetween to drive the liquid crystal. The pixel electrode, the common electrode, and the liquid crystal positioned between these electrodes constitute a liquid crystal capacitor Clc. Meanwhile, a storage capacitor Cst is further configured in each pixel P, which stores a data voltage applied to the pixel electrode until the next frame.

Each pixel P may be configured of, for example, R, G, and B subpixels representing red, green, and blue. In other words, the neighboring R, G, and B subpixels constitute the pixel P which is a unit of video display.

In addition, the plurality of common wirings CL1 to CLn extend in parallel with the plurality of gate wirings GL1 to GLn. The plurality of common wires CL1 to CLn are commonly connected to a common electrode (not shown) and a storage capacitor Cst constituting the liquid crystal capacitor Clc.

The backlight 800 serves to supply light to the liquid crystal panel 200. As a light source of the backlight 800, a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode (LED), or the like may be used.

The driving circuit unit 1000 includes a timing controller 300, a gate driver 400, a data driver 500, a gamma voltage supply unit 600, a power generator 700, and an AC voltage supply unit 710. It may include.

Here, the timing controller 300 includes image data RGB, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal CLK, and a data enable signal from an external system such as a TV system or a video card. The control signal TCS such as (DE) is input. Although not shown, such signals may be input through an interface configured in the timing controller 300.

The timing controller 300 uses the input control signal TCS to output a gate control signal GCS for controlling the gate driver 400 and a data control signal DCS for controlling the data driver 500. Create

The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like.

The data control signal (DCS) includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), and a polarity signal (POL). It may include.

The gate start pulse (GSP) informs the start line of the screen, that is, the first line, in one vertical period, and the gate shift clock (GSC) is a thin film formed on the pixel (P) of the liquid crystal panel 200. Specifies the time when the transistor T is turned on. In addition, the gate output enable signal GOE controls the output of the gate driver 400.

The source start pulse SSP informs the start point of the data, that is, the first pixel P, in one horizontal period, and the source sampling clock SSC is based on the rising and falling edges. To latch the data. In addition, the source output enable signal SOE serves to control the output of the data driver 500, and the polarity signal POL controls the data voltage of the liquid crystal panel 200 to be positive (+) or negative ( This signal indicates the polarity to drive with-).

In addition, the timing controller 300 receives image data RGB from an external system, arranges the image data RGB, and transmits the image data RGB to the data driver 500.

The gamma voltage supply unit 600 generates a gamma voltage Vgamma by dividing the high potential voltage and the low potential voltage generated from the power generator 700, and supplies the gamma voltage Vgamma to the data driver 500.

The data driver 500 supplies the data voltages to the plurality of data wirings DL1 to DLm in response to the data control signal DCS and the image data RGB supplied from the timing controller 300. That is, the data voltage corresponding to the image data RGB is generated using the gamma voltage Vgamma, and the generated data voltage is supplied to the corresponding data wirings DL1 to DLm.

The power generator 700 generates various driving voltages necessary for driving the liquid crystal display 100. For example, the power supply voltage supplied to the timing controller 300, the data driver 500, and the gate driver 400, the gate high voltage Vgh and the gate low voltage Vgl supplied to the gate driver 400, and the like. Will generate

The AC voltage supply unit 710 generates an AC common voltage Vcom_AC and a ground voltage GV supplied to the gate driver 400. Here, the AC common voltage Vcom_AC alternately has a high potential voltage and a low potential voltage every constant period, for example, every one horizontal period 1H.

First, the gate driver 400 may include a gate voltage supplier 410 and a common voltage supplier 420.

Here, the gate voltage supply unit 410 of the gate driver 400 sequentially scans the plurality of gate wirings GL1 to GLn in response to the gate control signal GCS supplied from the timing controller 300. do. For example, a plurality of gate lines GL1 to GLn are sequentially selected during each frame, and the gate high voltage is turned on for the thin film transistor T to be turned on for the selected gate lines GL1 to GLn. On the other hand, the gate low voltage Vgl is supplied to turn off the thin film transistor T to the gate lines GL1 to GLn until the next frame is scanned. The thin film transistor T is maintained in a turn off state.

Hereinafter, for convenience of description, the thin film transistor T will be described with an example of being turned on by the gate high voltage Vgh and turned off by the gate low voltage Vgl.

The common voltage supply unit 420 of the gate driver 400 sequentially applies a common voltage to the plurality of common lines CL1 to CLn in synchronization with driving of the gate voltage supply unit 410.

Specifically, the common voltage supply unit 420 sequentially scans the plurality of common lines CL1 to CLn in response to the gate control signal GCS supplied from the timing controller 300. For example, the plurality of common lines CL1 to CLn are sequentially selected during each frame, and the AC common voltage Vcom_AC is output to the selected common lines CL1 to CLn. By the AC common voltage Vcom_AC, a common voltage of a high potential voltage or a low potential voltage is applied to a common electrode (not shown) positioned in the row line.

After the AC common voltage Vcom_AC is applied, the ground voltage GV is output to the common lines CL1 to CLn until the next frame is scanned.

Accordingly, the common voltage supply unit 420 supplies the common voltages to the plurality of common lines CL1 to CLn in response to the gate control signal GCS, and thus a separate control signal for controlling the common voltage supply unit 420. The common voltage may be applied to the plurality of common lines CL1 to CLn.

Hereinafter, referring to FIG. 5, the connection relationship of the configuration of the gate driver 400 will be described.

FIG. 5 is a diagram illustrating an example of a configuration of a gate driver 400 according to an exemplary embodiment of the present invention. The first gate line GL1 and the first common line CL1 are shown together as an example.

As shown in FIG. 5, the common voltage supply unit 420 is connected to the gate voltage supply unit 410.

The common voltage supply unit 420 is driven in synchronization with the gate voltage supply unit 410. For example, the common voltage supply unit 420 may drive a signal for driving the gate wiring GL1 from the gate voltage supply unit 410, for example, a gate start pulse GSP, This is to receive the gate low voltage (Vgl). The signal received from the gate voltage supply unit 410 will be described in more detail later.

In this case, the first common line CL1 is connected to the common voltage supply unit 420.

The first gate line GL1 is connected to the gate voltage supply unit 410. In this case, the gate voltage branch part 410 is branched from the wiring connecting the common voltage supply part 420 and extends in parallel with the first common line CL1. That is, the first gate line GL1 receives an electrical signal from the gate voltage supply unit 410 but does not receive an electrical signal from the common voltage supply unit 420.

Hereinafter, the driving method of the liquid crystal display device 100 according to the exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 6A to 7.

6A and 6B illustrate an example of data polarity displayed on the liquid crystal panel 200 when the liquid crystal panel 200 is driven by the line inversion driving method, and FIG. 7 is the data polarity of FIGS. 6A and 6B. Are waveform diagrams for data voltages and common voltages corresponding to the waveforms.

First, a line inversion driving method will be described with reference to FIGS. 6A and 6B.

The inversion driving method is a method of inverting the polarities of the data voltage and the common voltage in a predetermined unit to prevent deterioration of the internal liquid crystal generated when the liquid crystal panel 200 is driven and to improve display quality of the image. Say. The inversion driving method is classified into a frame inversion method, a column inversion method, a dot inversion method, and the like according to the unit of polarity inversion.

As shown in Figs. 6A and 6B, in the inversion driving method, positive data and negative data are alternately displayed every row line, and the data polarity is inverted every frame. .

In detail, when positive data is output in the first row line of the first frame (FIG. 6A), negative data is output in the second row line.

In the second frame (Fig. 6B), data in which the data polarity applied to the first frame (Fig. 4A) is inverted is output.

At this time, for the line inversion driving method, as illustrated in FIG. 7, the data voltage Vdata and the common voltage Vcom having polarities reversed from each other are applied every one horizontal period 1H. In addition, the polarities of the data voltage Vdata and the common voltage Vcom are inverted every one horizontal period 1H and output to the liquid crystal panel 200.

Specifically, for example, when the gate high voltage Vgh is applied to the first gate line GL1 in the first horizontal period H1, the pixel (P in FIG. 4) positioned in the corresponding row line is applied. The negative data voltage Vdata is transmitted based on the common voltage Vcom. At this time, the common voltage Vcom applied to the first common wiring CL1 of FIG. 4 has a positive polarity (+).

During the second horizontal period H2, when the gate high voltage Vgh is applied to the second gate line GL2 of FIG. 4, the common voltage Vcom is applied to the pixel (P of FIG. 4) positioned in the row line. As a reference, the positive data voltage Vdata is transmitted. At this time, the common voltage Vcom applied to the second common wiring CL2 of FIG. 4 has a negative polarity (−).

That is, for line inversion driving, not only the data voltage Vdata but also the common voltage Vcom transmitted to the plurality of common wirings (CL1 to CLn in FIG. 4) inverts polarity every one horizontal period 1H.

By inverting the polarity of the common voltage Vcom as well as the polarity of the data voltage Vdata, the power consumption can be reduced more than inverting only the polarity of the data voltage Vdata based on the common voltage Vcom. have. In addition, there is an effect of improving the afterimage of the display image generated by applying the fixed common voltage Vcom.

Here, as described above, the common voltage supply unit 420 according to the embodiment of the present invention is sequentially common to a plurality of common wirings (CL1 to CLn in FIG. 4) in response to the gate control signal (GCS in FIG. 4). Apply the voltage Vcom.

In addition, the common voltage supply unit 420 drives the polarity of the common voltage Vcom for a predetermined period, for example, one horizontal period (1H) in order to drive the liquid crystal panel (200 in FIG. 4) to, for example, a line inversion. Inverted for each circuit and supplied to a plurality of common wirings (CL1 to CLn in FIG. 4).

That is, the common voltage supply unit 420 may be connected to the AC common voltage Vcom_AC and the ground voltage GV received from the power generator 700 and the gate control signal GCS from the timing controller 300. The common voltage Vcom is output by alternately applying high potential voltages or low potential voltages to the wirings CL1 to CLn. Accordingly, the effect of the line inversion driving method can be obtained without reversing the polarity of the common voltage Vcom.

Hereinafter, with reference to FIG. 8, it demonstrates in detail.

8 is a diagram illustrating a waveform diagram of gate voltages and common voltages applied to the first and second gate wirings and the first and second common wirings according to an exemplary embodiment of the present invention.

First, as shown in FIG. 8, the common voltage supply unit 420 of FIG. 4 receives an AC common voltage Vcom_AC alternately having a high potential voltage HV and a low potential voltage LV at regular intervals.

The AC common voltage Vcom_AC alternately has a high potential voltage HV and a low potential voltage LV in one horizontal period 1H, for example.

In addition, the AC common voltage Vcom_AC may be synchronized with, for example, a gate shift clock (not shown). Specifically, the rising or falling edge portion of the AC common voltage Vcom_AC may correspond to the rising or falling (or falling or rising) edge of the gate shift clock (not shown). Accordingly, when the gate voltage is sequentially applied to the plurality of gate wirings (GL1 to GLn in FIG. 4), the high potential voltage HV and the low potential voltage at regular intervals are applied to the corresponding common wiring (CL1 to CLn in FIG. 4). (LV) can be applied alternately.

In addition, the common voltage supply unit 420 of FIG. 4 receives a ground voltage GV having a constant value. The ground voltage GV may have a value of, for example, 0V.

For convenience of explanation, the waveform diagrams of the gate voltages Vgh and Vgl and the common voltage Vcom will be described by taking an NMOS transistor as an example.

First, the first gate line GL1 and the second gate line GL2 are sequentially selected, and the gate high voltage Vgh is sequentially applied. Accordingly, the thin film transistors (T in FIG. 4) of the pixels (P in FIG. 4) corresponding to the first gate line GL1 and the second gate line GL2 are sequentially turned on.

In addition, after the gate high voltage Vgh is transmitted to the first gate wiring GL1, that is, after one horizontal period 1H, the gate low voltage Vgl is transmitted until the next frame is scanned. Accordingly, the thin film transistor (T in FIG. 4) corresponding to the first gate line GL1 is turned off.

Similarly, after the gate high voltage Vgh is transmitted to the second gate line GL2, that is, after two horizontal periods 2H, the gate low voltage Vgl is transmitted until the next frame scan. Accordingly, the thin film transistor (T in FIG. 4) corresponding to the second gate line GL2 is turned off.

At this time, when the gate high voltage Vgh is sequentially applied to the first gate line GL1 and the second gate line GL2, the first common line CL1 and the second common line CL2 are synchronized with the gate high voltage Vgh. AC common voltage Vcom_AC is sequentially applied.

In addition, when the gate low voltage Vgl is applied to the first gate line GL1 and the second gate line GL2, the ground voltage GV is applied to the first common line CL1 and the second common line CL2. Is applied. That is, the ground voltage GV is output to the first common line CL1 and the second common line CL2 until the next frame is scanned.

That is, the first common line CL1 and the second common line CL2 are sequentially selected in synchronization with a scan signal that sequentially selects the first gate line GL1 and the second gate line GL2, and alternating current is common. Output the voltage Vcom_AC.

Specifically, for example, when the first gate wiring GL1 is selected in response to the gate control signal GCS of FIG. 4, the first common wiring CL1 is also selected. That is, the first common line CL1 is also selected by the scan signal for selecting the first gate line GL1. At this time, the gate high voltage Vgh is applied to the first gate line GL1, and the high potential voltage HV among the AC common voltage Vcom_AC value is output to the first common line CL1 as the common voltage Vcom. .

Similarly, when the second gate wiring GL2 is selected in response to the gate control signal (GCS in FIG. 4), the second common wiring CL2 is also selected. That is, the second common wiring CL2 is also selected by the scan signal for selecting the second gate wiring GL2. At this time, the gate high voltage Vgh is applied to the second gate line GL2, and the low potential voltage LV is output as the common voltage Vcom among the AC common voltage Vcom_AC value to the second common line CL2. do.

Accordingly, the common voltage Vcom applied to the first and second common wirings CL1 and CL2 is alternated from the high potential voltage HV to the low potential voltage LV every one horizontal period 1H. Inversion operation is possible. For example, the high potential voltage HV may correspond to the common voltage Vcom of the positive polarity (+), and the low potential voltage LV may correspond to the common voltage Vcom of the negative polarity (−). Accordingly, the driving device may be driven in a line inversion method without reversing the polarity of the common voltage Vcom.

Meanwhile, when the gate low voltage Vgl is applied to the first gate line GL1, the ground voltage GV is output to the first common line CL1. Accordingly, the common voltage Vcom of the first common wiring CL1 becomes a value of the ground voltage GV, for example, 0V, from the high potential voltage HV. The ground voltage GV is output to the first common line CL1 until the next frame is scanned.

Similarly, when the gate low voltage Vgl is applied to the second gate line GL2, the ground voltage GV is output to the second common line CL2. Accordingly, the common voltage Vcom of the second common wiring CL2 becomes the ground voltage GV value from the low potential voltage LV. The ground voltage GV is output to the second common line CL2 until the next frame scan.

Here, even if the common voltage Vcom applied to the first and second common lines CL1 and CL2 for one frame is changed from the AC common voltage Vcom_AC to the ground voltage GV, image display is not affected.

The common voltage Vcom applied to the first and second common lines CL1 and CL2 may be changed from the AC common voltage Vcom_AC to the ground voltage GV by the data voltage Vdata and the common voltage of the pixel electrode. This is because the difference value of Vcom) remains constant.

In detail, when a data voltage (Vdata of FIG. 5) is applied to the pixel electrode and a common voltage Vcom is applied to the common electrode, an electric field is formed therebetween to drive the liquid crystal to realize grayscale. In other words, the arrangement state of the liquid crystals is varied by an electric field formed by the voltage difference between the data voltage Vdata of the pixel electrode and the common voltage Vcom of the common electrode, thereby displaying an image by adjusting the light transmittance.

When the thin film transistor (T in FIG. 3) is turned on, the liquid crystal capacitor Clc and the storage capacitor Cst charge the difference voltage between the data voltage Vdata of the pixel electrode and the common voltage Vcom of the common electrode. Subsequently, when the thin film transistor (T in FIG. 4) is turned off, the pixel electrode is in a floating state, and the liquid crystal capacitor Clc and the storage capacitor Cst hold the charged voltage. In this case, when the common voltage Vcom of the first and second common lines CL1 and CL2 is reduced or increased to the ground voltage GV, the data voltage Vdata of the floating pixel electrode is decreased or increased. .

Accordingly, the difference voltage between the common voltage Vcom of the common electrode and the data voltage Vdata of the pixel electrode is kept constant for one frame. Therefore, since the gray scale is implemented by the difference voltage between the common voltage Vcom and the data voltage Vdata, the difference voltage between the common voltage Vcom and the data voltage Vdata is kept constant so that the image display is not affected. do.

9 and 10, the internal circuit diagram of the gate driver 400 according to an embodiment of the present invention will be described in more detail.

9 is an internal circuit diagram of a gate voltage supply unit 410 according to an embodiment of the present invention, and FIG. 10 is an internal circuit diagram of a common voltage supply unit 420 according to an embodiment of the present invention.

First, as shown in FIG. 9, the gate voltage supply unit 410 may include first to thirteenth gate transistors GT1 to GT13 and first to third gate capacitors GC1 to GC3.

A terminal receiving the gate start pulse GSP to the gate electrode and the drain electrode of the first gate transistor GT1 and a terminal receiving the gate high voltage Vgh to the gate electrode of the second gate transistor GT1. The gate electrode of the third gate transistor GT3 is connected to a terminal receiving an initialization signal, that is, a reset signal Reset, and the third, fourth, seven, nine, eleven, and thirteen gate transistors GT3. , The source electrodes of GT4, GT7, GT9, GT11, and GT13 are connected to terminals receiving the gate low voltage (Vgl).

A drain electrode of the fifth gate transistor GT5 and a gate electrode of the sixth gate transistor GT6 and the eighth gate transistor GT8 are connected to a terminal receiving the gate shift clock GSC.

Here, the gate start pulse GSP and the gate shift clock GSC, the gate low voltage Vgl, and the first signal generated from the gate voltage supply unit 410 (not shown in detail) are described later. The common voltage supply unit 420 is transferred.

Hereinafter, an internal circuit diagram of the common voltage supply unit 420 according to the embodiment of the present invention will be described in more detail with reference to FIG. 10.

As shown in FIG. 10, the common voltage supply unit 420 may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2.

Here, the first to fourth transistors T1 to T4 and the first and second capacitors C1 and C2 form a bootstrapping unit 421 for boosting the gate voltage, and the fifth and sixth transistors include the gate voltage. In response to this, the buffer unit 422 for outputting the common voltage Vcom is configured.

In this case, the first to sixth transistors T1 to T6 will be described using an NMOS transistor as an example.

First, the connection relationship of each structure is demonstrated.

The gate electrode of the first transistor T1 is connected to the gate electrode of the fourth transistor T4 and is connected to a terminal to which the gate high voltage Vgh is applied.

The drain electrode and the gate electrode of the first transistor T1 are connected to the terminal receiving the gate start pulse GSP, and the source electrode of the first transistor T1 is the gate of the third and fifth transistors T3 and T5. The electrode is connected to the first electrode of the first capacitor C1 and the drain electrode of the second transistor T2.

The gate electrode of the second transistor T2 is connected to the gate electrode of the sixth transistor T6, and although not shown, is turned on in response to the first signal received from the gate voltage supply unit 410.

Here, the first signal transmitted from the gator voltage supply unit 410 may be, for example, a signal for turning on the sixth transistor and the second transistor in addition to the two clock periods during which the voltage of the Q node Q is boosted.

The source electrode of the second transistor T2 is connected to the terminal to which the gate low voltage Vgl is applied, the source electrode of the fourth transistor T4, and the second electrode of the second capacitor C2.

The drain electrode of the third transistor T3 is connected to a terminal receiving the gate shift clock GSC signal, and the source electrode of the third transistor T3 is the drain electrode of the fourth transistor T4 and the first capacitor C1. Is connected to the second electrode.

The source electrode of the fourth transistor T4 is connected to the terminal receiving the gate low voltage Vgl and the second electrode of the second capacitor C2.

The drain electrode of the fifth transistor T5 is connected to a terminal receiving the AC common voltage Vcom_AC, and the source electrode of the fifth transistor T5 is connected to the drain electrode of the sixth transistor T6 and the common voltage Vcom. Connected to the output terminal.

The drain electrode of the sixth transistor T6 is connected to the output terminal of the common voltage Vcom, and the source electrode of the sixth transistor T6 is connected to the terminal which outputs the ground voltage GV.

The second electrode of the first capacitor and the first electrode of the second capacitor are connected.

Hereinafter, the common voltage supply unit 420 according to the embodiment of the present invention will be described in more detail with reference to FIGS. 11A and 11B.

11A and 11B illustrate waveform diagrams of voltages applied to first and second gate wirings and first and second common wirings according to an exemplary embodiment of the present invention.

First, as described above, in the embodiment of the present invention, a plurality of common wirings (CL1 to CLn in FIG. 4) are sequentially selected in response to a gate control signal (GCS in FIG. 4), and the selected common wiring (FIG. 4). AC common voltage (Vcom_AC in FIG. 4) is output to CL1 to CLn.

That is, the corresponding common wirings (CL1 to CLn in FIG. 4) are selected by the gate voltage for turning on, for example, the gate shift clock GSC, and the AC common voltage (Vcom_AC in FIG. 4) is applied. In addition, when the gate voltage of the turn-off, for example, the gate low voltage Vgl is transmitted until the scan of the next frame, the ground voltage (GV in FIG. 4) is output to the common wiring (CL1 to CLn in FIG. 4).

Specifically, for example, referring to FIG. 11A, when the first gate wiring GL1 is selected, the first common wiring CL1 has a high potential voltage HV in the common voltage Vcom in the AC common voltage Vcom_AC. Is output as. That is, when the gate high voltage Vgh is applied to the first gate line GL1, the high potential voltage HV is output to the first common line CL1.

When a turn-off voltage, for example, a gate low voltage Vgl is applied to the first gate line GL1, the ground voltage GV is output to the first common line CL1.

The voltage of the Q node Q is a voltage obtained by boosting the scan signal through bootstrapping for two clock periods in order to stably output the scan signal to the first common wiring CL1.

Specifically, for example, a clock before a clock in which the first gate line GL1 and the first common line CL1 are selected, and a clock in which the first gate line GL1 and the first common line CL1 are selected. The scan signal is boosted twice, for example, and charged to the Q node Q.

During the first clock, a value of about 10V, the gate high voltage (Vgh), is charged to the Q node (Q) and, through bootstrapping, is charged to the Q node (Q) at about 20V at the second clock, thereby providing a Q node ( The voltage of Q) is used as a scan signal for selecting the first common wiring CL1.

As a result, by stably outputting the scan signal for selecting the first common wiring CL1, the AC common voltage Vcom_AC can be efficiently output to the first common wiring CL1.

Hereinafter, with reference to FIG. 11B, for example, when the second gate line GL2 is selected, the second common line CL2 may have the low potential voltage LV in the common voltage V in the AC common voltage Vcom_AC. Vcom). That is, when the gate high voltage Vgh is applied to the second gate line GL2, the low potential voltage LV is output to the second common line CL2.

In addition, when a turn-off voltage, for example, a gate low voltage Vgl is applied to the second gate line GL2, the ground voltage GV is output to the second common line CL2.

As described above, the voltage of the Q node Q is a scan signal, for example, a gate high voltage Vgh, for two clock periods in order to stably output a scan signal for selecting the second common wiring CL2. Is the voltage boosted by bootstrapping.

Specifically, for example, a clock before a clock in which the second gate wiring GL2 and the second common wiring CL2 are selected, and a clock in which the second gate wiring GL2 and the second common wiring CL2 are selected. The gate high voltage Vgh is boosted for example twice.

During the first clock, a value of about 10V, the gate high voltage (Vgh), is charged to the Q node (Q) and, through bootstrapping, is charged to the Q node (Q) at about 20V at the second clock, thereby providing a Q node ( The voltage of Q) is used as a scan signal for selecting the second common wiring CL2.

As a result, by stably outputting the scan signal for selecting the first common line CL1, the AC common voltage Vcom_AC can be efficiently output to the second common line CL2.

That is, in the embodiment of the present invention, the first common wiring CL1 and the second common wiring CL2 are selected, for example, in synchronization with the gate high voltage Vgh, and the common wiring corresponding to the AC common voltage Vcom_AC. Output to (CL1 and CL2).

Hereinafter, the driving of the buffer unit 422 and the bootstrapping unit 421 will be described in more detail with reference to FIGS. 12 and 13.

12 is a diagram illustrating a current flow of the buffer unit 422, and FIG. 13 is a diagram illustrating a current flow of the bootstrapping unit 421.

First, the buffer unit 422 outputs the common voltage Vcom to the selected common wirings (CL1 to CLn in FIG. 4) in response to the gate voltage.

Specifically, during two clocks in which the gate high voltage Vgh is boosted, the fifth transistor T5 is turned on, and the current at this time is connected to the terminal receiving the AC common voltage Vcom_AC and the fifth transistor T5. It passes to the output terminal of the common voltage Vcom (first direction). Here, when the gate high voltage Vgh is output, the AC common voltage Vcom_AC is output as the common voltage Vcom on the corresponding common wiring (CL1 to CLn in FIG. 4). At this time, the sixth transistor T6 is turned off.

On the other hand, the sixth transistor T6 is turned on during the period in which the gate high voltage Vgh is not boosted, that is, during a period other than 2 clocks, and the current direction is the ground voltage GV from the output terminal of the common voltage Vcom. Flows to the terminal for outputting (second direction). Accordingly, the ground voltage GV is output as the common voltage Vcom. At this time, the fifth transistor T5 is turned off.

That is, during the two clocks in which the gate high voltage Vgh is boosted, the fifth transistor T5 is turned on, and the AC common voltage Vcom_AC is output to the output terminal of the common voltage Vcom. T6 is turned on so that the ground voltage GV is output as the common voltage Vcom.

The bootstrapping unit 421 bootstraps the scan signal to increase the voltage of the scan signal and transmit the voltage to the buffer unit 422. That is, in order to stably output the scan signal to the buffer unit 422, the voltage of the scan signal is boosted through bootstrapping.

For example, the AC common voltage Vcom is sequentially applied to the first and second common wirings CL1 and CL2 in synchronization with the gate high voltage Vgh, so that the bootstrapping unit 421 may use the gate high voltage. (Vgh) is boosted and transferred to the buffer unit 422 as a scan signal.

Specifically, for example, the bootstrapping section 421 is driven during two clocks in which the AC common voltage Vcom_AC is output to the common voltage Vcom output terminal to boost the scan signal, and is not driven in other periods. That is, the voltage charged to the Q node Q for two clocks is boosted by, for example, twice.

Here, during the first clock, the first transistor T1, the third transistor T3, and the fourth transistor T4 are turned on, and the second transistor T2 is turned off.

Accordingly, the direction of the current flow is charged to the first capacitor C1 through the first transistor T1 as in the first direction, and at this time, the voltage of the Q node Q is charged to about 10 V (Fig. 11).

During the second clock, only the third transistor T3 is turned on and the remaining transistors T1, T2, and T4 are turned off. Accordingly, in the direction of current flow, a voltage of 10 V is charged to the second capacitor C2 through the third transistor T3 as in the second direction. At this time, since the first capacitor C1 is in a floating state, the voltage of the second capacitor C2 is increased to 10V, thereby increasing the voltage of the Q node Q to 20V. That is, the second electrode of the first capacitor C1 is further increased by 10V due to the influence of the second capacitor C2, and accordingly, the voltage of the first electrode of the first capacitor C1 is further increased by 10V. The voltage of Q) is boosted to 20V.

Accordingly, the scan signal, for example, the gate high voltage Vgh can be stably output to the plurality of common wirings (CL1 to CLn in FIG. 4).

For convenience of explanation, the NMOS transistor has been described as an example, but it is apparent to those skilled in the art that a PMOS transistor can be used.

As described above, in the embodiment of the present invention, a plurality of common wirings (CL1 to CLn in FIG. 4) in response to the gate control signal (GCS in FIG. 4) without a separate control signal for controlling the common voltage supply unit 420. ) May be sequentially selected and the line inversion method may be driven by outputting the common voltage Vcom.

Therefore, the bootstrapping unit 421 and the buffer unit 422 may be additionally configured in the gate driver 400 to implement a function of supplying a common voltage.

Accordingly, in the related art, if a space of 0.9 mm is required in the horizontal direction to design the common voltage driver as shown in FIG. 3, in the present invention, the common voltage supply unit 420 may be designed in a space of 0.51 mm as shown in FIG. 14. have. Since the gate control signal (GCS of FIG. 4) is used as the control signal of the common voltage supply unit 420, the bootstrap unit 421 and the buffer unit 422 are additionally configured to supply the common voltage to the general gate driver. Because it can. This design can increase productivity and reduce production costs, and is effective for narrow bezel implementation.

In addition, in order to drive the line inversion method of the common voltage Vcom, the polarity of the common voltage Vcom is not inverted, but the line inversion driving effect is achieved using the AC common voltage Vcom_AC. There is an effect of reducing the power consumption generated.

The embodiments of the present invention described above are examples of the present invention, and modifications can be made freely within the scope of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and their equivalents.

100: liquid crystal display device 200: liquid crystal panel
400: gate driver 410: gate voltage supply unit 420: common voltage supply unit
Vcom_AC: AC common voltage GV: Ground voltage
HV: High potential voltage of AC common voltage LV: Low potential voltage of AC common voltage
Vgh: Gate high voltage Vgl: Gate low voltage

Claims (9)

A plurality of gate wirings;
A plurality of common wirings corresponding to and extending in parallel to the plurality of gate wirings;
A timing controller configured to generate gate control signals for controlling the plurality of gate lines and the plurality of common lines;
A gate driver configured to sequentially select the plurality of common wires in response to the gate control signal, and output an AC common voltage having a high potential voltage and a low potential voltage alternately in the selected common line every one horizontal period as a common voltage; Containing
LCD display device.
The method of claim 1,
The gate driver outputs a ground voltage as the common voltage to the plurality of common lines until the next frame scan.
LCD display device.
The method of claim 2,
The gate driver,
A gate voltage supply unit sequentially selecting the plurality of gate wirings in response to the gate control signal, and outputting a gate voltage to the selected gate wirings;
And a common voltage supply unit configured to sequentially select the plurality of common wires in response to the gate control signal, and output the common voltage to the selected common wires.
LCD display device.
The method of claim 3, wherein
The common voltage supply unit,
A buffer unit sequentially outputting the AC common voltage to the plurality of common wires in response to the gate high voltage;
A bootstrapping unit boosts the gate high voltage.
LCD display device.
The method of claim 4, wherein
The common voltage supply unit includes first to sixth transistors, first and second capacitors, a gate start pulse, a gate low voltage, a gate shift clock, a first signal transmitted from the gate voltage supply unit, and the AC common voltage and the A terminal for receiving a ground voltage and a terminal for outputting the common voltage,
The terminal receiving the gate start pulse is connected to the gate electrode and the drain electrode of the first transistor, the gate electrode of the fourth transistor,
The terminal receiving the gate shift clock is connected to the drain electrode of the third transistor,
A terminal receiving the first signal is connected to gate electrodes of the second and sixth transistors,
A terminal receiving the gate low voltage is connected to source electrodes of the second and fourth transistors and a second electrode of the second capacitor,
The terminal receiving the AC common voltage is connected to the drain electrode of the fifth transistor,
The terminal receiving the ground voltage is connected to the source electrode of the sixth transistor,
The terminal for outputting the common voltage is connected to the source electrode of the fifth transistor and the drain electrode of the sixth transistor,
A source electrode of the first transistor is connected to a drain electrode of the second transistor, a gate electrode of the third transistor, and a first electrode of the first capacitor,
The source electrode of the third transistor is connected to the drain electrode of the fourth transistor and the second electrode of the first capacitor.
LCD display device.
A liquid crystal display device driving method for outputting a common voltage to a plurality of gate wirings and a plurality of common wirings corresponding to and extending in parallel with the plurality of gate wirings,
Generating a gate control signal;
Sequentially selecting the plurality of common wires in response to the gate control signal;
Outputting an AC common voltage having the high potential voltage and the low potential voltage alternately in the selected common wiring every one horizontal period as the common voltage;
Liquid crystal display driving method.
The method according to claim 6,
Outputting a ground voltage to the plurality of common wires as the common voltage until the next frame is scanned
Liquid crystal display driving method.
The method of claim 7, wherein
And sequentially selecting the plurality of gate wirings in response to the gate control signal, and outputting a gate high voltage to the selected gate wirings.
Liquid crystal display driving method.
The method of claim 8,
The step of outputting the AC common voltage as the common voltage,
Boosting the gate high voltage;
And outputting the AC common voltage sequentially to the plurality of common wires in response to the output of the boosted gate high voltage.
Liquid crystal display driving method.

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