KR20120105771A - Resistance ram device using graphene and method for operating the same - Google Patents

Abstract

PURPOSE: A resistive random access memory device and an operation method thereof using graphene are provided to have uniform electrical characteristics by using oxidation-reduction reaction between a graphene layer and an oxide layer. CONSTITUTION: A resistive random access memory device includes a lower electrode(10), an oxide layer(20) and a graphene layer(30). The lower electrode is made of a metal group including platinum, ruthenium, aluminum, iridium, tungsten and copper or graphene. The thickness of the oxidation layer is 20nm to 60nm. A graphene oxide layer is formed between the interface of the oxide layer and the graphene layer due to graphene-oxygen combination then a resistance is changed.

Description

Resistance RAM device using Graphene and method for operating the same

The present invention relates to a resistance change memory device using graphene and a method of operating the same, and more particularly, to a nonvolatile resistance change memory device using a graphene layer as an upper electrode, and an oxidation occurring at an interface between the graphene layer and an oxide layer. The present invention relates to a method of operating a device of a resistance change memory using a characteristic in which the resistance of the device changes due to the reduction / reduction reaction.

The resistance change memory device, which is one of the nonvolatile memory devices, is a device that uses a material capable of switching at least two different resistance states by rapidly changing resistance according to an applied bias. Recently, due to the simplicity of the structure, low power consumption, fast switching time, and ease of manufacturing process, it is attracting attention as the next generation nonvolatile memory device.

The resistance change memory device has a metal-insulator-metal (MIM) structure in which an insulating film is interposed between metal electrodes, and is switched using a resistance change appearing in the insulating film.

In the case of the conductive filament model, which is one of the switching mechanisms, the current flows well through the insulating film by first applying a voltage to the resistance change memory device of the MIM structure to induce soft-breakdown of the insulating film at a specific voltage. It is made into Low Resistance State (LRS), which is called forming process. The resistance change memory that has undergone the forming process may create a high resistance state and a low resistance state through a reset process and a set process, respectively, according to a change in the applied voltage. The memory device is operated.

In the case of a resistive change memory device that follows the switching mechanism of the conductive filament model, the on / off resistance ratio is large and operates at a high speed. However, in most cases, a forming process is required. This is an obstacle to its practical use.

In order to solve this problem, a technology for a resistance change memory device that can operate without a forming process is disclosed in Korean Patent No. 10-0722853.

However, this is due to the method of stacking the insulating film by repeating the heat treatment a plurality of times, there is a problem that the manufacturing process is complicated and the cost increases.

Graphene is a new two-dimensional carbon material discovered in 2004. It is a honeycomb two-dimensional thin film formed of a layer of carbon atoms. Research on the graphene has been actively conducted in the academic world to date, and various research results regarding the electrical properties of graphene have been recently published. Graphene has been in the spotlight in the semiconductor and display fields due to its high optical transparency, excellent elasticity and flexibility, and low sheet resistance, and research on manufacturing new devices using such devices, including solar cells, transistors, and light emitting devices, is being conducted.

Accordingly, a first object of the present invention is to provide a resistance change memory device using graphene having a large on / off resistance ratio and excellent high temperature retention characteristics by utilizing a graphene layer as an upper electrode.

In addition, the second object of the present invention is to change the resistance of the device by the oxidation / reduction reaction occurring at the interface of the graphene layer and the oxide layer by operating the resistance change memory device using graphene that can switch the device without a separate forming process To provide a way.

The present invention for achieving the above first object, comprising a lower electrode, an oxide layer positioned on the lower electrode and an upper electrode positioned on the oxide layer, wherein the upper electrode is formed of a graphene layer It features.

In addition, the present invention for achieving the second object, providing a memory device characterized in that it comprises a lower electrode, an oxide layer formed on the lower electrode, a graphene layer formed on the oxide layer, the Programming a memory device to a high resistance state by generating a graphene oxide at an interface between the lower portion of the graphene layer and the oxide layer by applying a positive voltage to the graphene layer and applying a negative voltage to the graphene layer Reducing the graphene oxide to program the memory device to a low resistance state.

The resistance change memory device using graphene according to the present invention has uniform electrical characteristics even when the area of the device is reduced by using an oxidation / reduction reaction between the graphene layer and the oxide layer, and the high temperature retention characteristic is high. Excellent effect.

In addition, the operation method of the resistance change memory device using the graphene has the effect that the operation of the device can be easily and easily without a separate forming process by using the resistance change of the device by the reaction.

1 is a diagram illustrating a resistance change memory device in which a graphene layer is formed as an upper electrode.
2A and 2B are cross-sectional views illustrating a method of operating a resistance change memory device using graphene according to the present invention.
3A is a graph illustrating current-voltage characteristics of a resistance change memory device using graphene according to the present invention.
3B is a graph showing current-voltage characteristics of a resistance change memory device using Pt as an upper electrode as a comparative example.
4 is a graph showing a change in current value according to a switching cycle of a resistance change memory device using graphene according to the present invention.
5 is a graph showing a change in current value over time of a resistance change memory device using graphene according to the present invention.
6 is a graph illustrating a change in resistance state according to an area change of a resistance change memory device using graphene according to the present invention.
FIG. 7A is a Raman spectrum showing characteristics of a graphene layer in a pristine state before applying a voltage. FIG.
FIG. 7B is a Raman spectrum comparing characteristics of a graphene layer in a low resistance state (LRS) and a high resistance state (HRS).
FIG. 7C shows the position of the G peak in the initial state (pristine), the low resistance state (LRS), and the high resistance state (HRS) before applying voltage, and the intensity ratio (I (D) / I ( It is a graph comparing G)).

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a diagram illustrating a resistance change memory device in which a graphene layer is formed as an upper electrode.

Referring to FIG. 1, the resistance change memory device using graphene according to the present invention includes a lower electrode 10, an oxide layer 20 sequentially formed on the lower electrode 10, and a graphene layer 30 as an upper electrode. It has a structure that includes.

The structure is formed on a substrate (not shown). The substrate may be any one that is applied to a conventional semiconductor memory device, and may be a silicon substrate or a combination of a specific film quality and a substrate in which silicon oxide is formed on the silicon substrate.

The lower electrode 10 formed on the substrate is preferably selected from a metal series or graphene including Pt, Ru, Al, Ir, W, Cu.

In addition, the oxide layer 20 formed on the lower electrode 10 may be selected from various materials exhibiting resistance switching characteristics. In particular, it is preferable to select a material that is easily reactive and easily oxidized in relation to the material forming the upper electrode.

For example, the oxide layer 20 may be a binary metal oxide based or perovskite film. The binary metal oxide series may include TiO ₂ , NiO, HfO ₂ , SiO ₂ , ZrO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , and perovskite film SrTiO _3, may include the Nb-doped SrTiO _3, Cr-doped _{SrTiO 3, BaTiO 3, LaMnO 3} , SrMnO 3, PrTiO 3. It may also include Pr _{1 - x} Ca _x MnO ₃ (0 ≦ _x ≦ 1) and La _{1 - x} Ca _x MnO ₃ (0 ≦ _x ≦ 1).

At this time, the thickness of the oxide layer 20 is preferably 20nm to 60nm, the thickness of less than 20nm problem occurs that the operating voltage is unstable, on the contrary, if the thickness exceeds 60nm due to excessive increase in the operating voltage Problems of increased power consumption and poor operation may occur.

The oxide layer 20 may be formed using sputtering, pulsed laser deposition (PLD), molecular beam epitaxy deposition (MBE), chemical vapor deposition (CVD), or the like.

The graphene layer 30 formed on the oxide layer 20 constitutes an upper electrode. The graphene layer 30 may be formed on the oxide layer 20 in various ways. For example, the graphene layer 30 may be etched using a polydimethylsiloxane (PDMS) or polymethylmethacrylate (PMMA) as a support to etch the graphene-grown catalyst layer. Can be formed.

The graphene layer 30 is preferably formed in a plurality of layers for the reaction at the interface with the oxide layer 20. Since graphene is composed of carbon only, various chemical functional groups such as carboxyl and hydroxyls can be introduced through oxidation / reduction reactions with oxygen group elements, thereby changing the structural and electrical properties. Have That is, graphene oxide produced by oxidizing graphene by oxygen has high insulation due to oxygen-induced defects and disorders.

For example, the lower portion of the graphene layer 30 is oxidized by the movement of oxygen ions included in the oxide layer 20 which leads the resistance change, and the oxidized graphene layer 30 maintains a high resistance state. That is, the graphene oxide layer 30a is formed at the interface between the graphene layer 30 and the oxide layer 20 serving as the upper electrode by the combination of graphene and oxygen, whereby a resistance change occurs.

 [Manufacturing Example]

After forming a Pt film as a lower electrode on the SiO ₂ / Si substrate, a PCMO layer having a thickness of 60 nm was formed on the Pt film. The PCMO layer is one of materials used for excellent resistance switching characteristics due to oxidation / reduction reaction with a reactive metal such as Al and Ti in PCMO. The PCMO layer was deposited using RF sputtering at a temperature of 450 ℃. Thereafter, a graphene layer was formed on the PCMO layer. The graphene layer was manufactured by CVD using a nickel layer as a catalyst layer.

Subsequently, the graphene layer prepared above is immersed in an FeCl ₃ solution and etched in a sequentially stacked PCMO / Pt / SiO ₂ / Si structure to separate a nickel layer, which is a catalyst layer, and the PCMO / Pt / SiO ₂ / Si is sequentially stacked. Transferred onto a PCMO layer of a structure. After that, a photoresist was applied to the upper electrode region as an etching mask, and then patterned by oxygen plasma etching to manufacture the resistance change memory device of the present invention.

2A and 2B are cross-sectional views illustrating a method of operating a resistance change memory device using graphene according to the present invention.

Referring to FIG. 2A, when a ground voltage is applied to the lower electrode 10 and a positive voltage is applied to the graphene layer 30 that is the upper electrode, oxygen ions O ² of the oxide layer 20 are applied. ^- ) Moves to the graphene layer (30). Accordingly, the graphene is oxidized at the interface between the graphene layer 30 and the oxide layer 20 to form the graphene oxide layer 30a, thereby increasing the overall resistance of the device, thereby increasing a high resistance state (HRS). That is, it is in a reset state.

Referring to FIG. 2B, when a ground voltage is applied to the lower electrode 10 and a negative voltage (−) is applied to the graphene layer 30, which is an upper electrode, oxygen ions O ^{2 −} may form the graphene layer. It is separated from the graphene oxide layer 30a formed at the interface between the 30 and the oxide layer 20. Accordingly, the graphene oxide layer 30a is reduced and disappears again, and the device is in a low resistance state (LRS), that is, a set state.

3A is a graph illustrating current-voltage characteristics of a resistance change memory device using graphene according to the present invention.

In order to prevent an electrical breakdown, the voltage applied was limited in the range of -5V to 5V, and the voltage was changed in the direction (1) → (2) → (3) → (4).

Referring to FIG. 3A, when a positive voltage is applied to the graphene layer, which is an upper electrode, oxygen ions (O ^{2 −} ) of the oxide layer move to an interface with the graphene layer to form a graphene oxide layer. It becomes a high resistance state. Thereafter, when the voltage applied to the graphene layer, which is the upper electrode, decreases, the current decreases along the direction (2).

On the other hand, when a negative voltage is applied to the graphene layer, which is an upper electrode, oxygen ions (O ^2- ) move from the interface between the graphene layer and the oxide layer to the oxide layer, whereby the graphene oxide layer is returned to the graphene layer. Reduced. Therefore, the current increases along the direction (3), and the device is in a low resistance state. Thereafter, when the voltage applied to the upper electrode decreases, the current decreases along the direction (4). That is, resistance switching characteristics in which the resistance of the device changes in accordance with the applied voltage appears.

3B is a graph showing a current-voltage characteristic of a resistance change memory device using a Pt film as an upper electrode in order to confirm the effect of the upper electrode on the resistance switching characteristic as a comparative example.

Referring to FIG. 3B, unlike the case of FIG. 3A in which the upper electrode is formed of the graphene layer, the resistance does not change depending on the applied voltage in the range of the applied voltage of -5V to 5V.

This is because the forming process, which causes a soft-breakdown of the oxide layer to bring the current through the oxide layer into a low resistance state, does not reach a voltage at which it can occur. In addition, unlike the graphene layer, in the case of Pt which is an inactive metal, the reaction with oxygen ions (O ^{2 −} ) hardly occurs. Therefore, when Pt is the upper electrode, the resistance change characteristic does not appear according to the voltage, and a non-linear current-voltage curve, which is a characteristic of the PCMO thin film itself, is displayed.

Accordingly, it can be seen from the comparative example that the resistance change memory device using the graphene according to the present invention has a resistance switching characteristic even without a forming process.

4 is a graph showing current values in a high resistance state HRS and a low resistance state LRS according to a switching cycle of a resistance change memory device using graphene according to the present invention. As the measurement conditions, a set voltage of -6V and a reset voltage of 6V were applied at intervals of a pulse width of 10 s. The read voltage at this time is 1V.

Referring to FIG. 4, when the switching operation is repeated up to 1000 times, it can be seen that the current values of the high resistance state HRS and the low resistance state LRS are maintained substantially constant. Through this, the resistive memory device using the graphene according to the present invention can be seen that the excellent pulse endurance (pulse endurance).

5 is a graph showing a change in current value over time of a resistance change memory device using graphene according to the present invention. The measurement conditions were a temperature of 85 ° C. and a read voltage of 1V.

Referring to FIG. 5, current values in the low resistance state (LRS) and the high resistance state (HRS) of the resistance change memory device using graphene according to the present invention are almost constant from 85 ° C. to 10000 seconds at a relatively high temperature. Can be maintained. Accordingly, it can be seen that the difference between the resistance values of the low resistance state LRS and the high resistance state HRS is constant, and has a large resistance ratio, which is excellent in retention characteristics even at high temperatures.

6 is a graph illustrating a change in resistance state according to an area change of a resistance change memory device using graphene according to the present invention.

Referring to FIG. 6, as the device area increases, both the resistance of the low resistance state LRS and the resistance of the high resistance state HRS decrease. Compared to the case of the resistive change memory device having the switching mechanism of the conductive filament model, since the conducting filament paths are locally formed to cause the resistive change, the resistance decrease according to the device area in the low resistance state is reduced. Small enough to be ignored This shows that the oxidation / reduction reaction occurring from the interface between the graphene layer and the oxide layer is not local but occurs uniformly in all areas. This means that it is possible to ensure uniform electrical characteristics regardless of the area of the device.

7A, 7B, and 7C are Raman spectra showing characteristics of graphene before and after resistance switching characteristics occur.

FIG. 7A is a Raman spectrum showing characteristics of a graphene layer in a pristine state before applying a voltage. FIG. The incident light used an Ar laser of 514 nm.

Referring to FIG. 7A, it can be seen that the D peak is lower than the G peak, through which the defect and disorder of the graphene layer are small. In addition, the sheet resistance of the graphene layer in the initial state has a value of about 700 Ω / □ when measured through the Van der Pauw method, one of the specific resistance measurement method, it can be used as an upper electrode.

FIG. 7B is a Raman spectrum comparing characteristics of the graphene layer in the low resistance state (LHS) and the high resistance state (HRS).

Referring to Figure 7b, 1350cm in the high resistance state (HRS) ^- can confirm the D 'peak appearing at the ^1-D high peak and the G peak right at 1620cm ^1. Through this, it can be seen that the graphene layer is deformed by the electric field in the high resistance state (HRS).

On the contrary, in the low resistance state (LRS), low D peaks and D 'peaks can be confirmed, and it can be seen that defects and disorders are reduced through this.

In addition, it can be seen that the G peak of the high resistance state (HRS) appears in a higher frequency region than the G peak of the low resistance state (LRS). It is solved because it was formed.

FIG. 7C shows the position of the G peak in the initial state (pristine), the low resistance state (LRS), and the high resistance state (HRS) before applying voltage, and the intensity ratio (I (D) / I ( It is a graph comparing G)).

And Referring to Figure 7c, the voltage applied to the initial state, the position of the G peak in the low resistance state (LRS) and the high resistance state (HRS) before each ^{1579.5cm -1, 1580.6cm -1, 1587.7cm -1} , D It can be seen that I (D) / I (G), which is the ratio between the peak and the G peak, is 0.10, 0.13, and 1.55, respectively. Through this, it can be seen that the memory device using the graphene according to the present invention exhibits a resistance switching characteristic and thus may function as a resistance change memory device.

10: lower electrode
20: oxide layer
30: graphene layer
30a: graphene oxide layer

Claims (12)

Lower electrode;
An oxide layer on the lower electrode; And
It is configured to include an upper electrode located on the oxide layer,
The upper electrode is a resistance change memory device using a graphene, characterized in that formed of a graphene layer. The method of claim 1,
The graphene layer is a resistance change memory device using a graphene, characterized in that the resistance change occurs by bonding with oxygen ions moved from the oxide layer. The method of claim 2,
And a graphene oxide layer is formed at the interface between the graphene layer and the oxide layer by coupling the oxide layer with the oxygen ions. The method of claim 1,
The lower electrode is a resistance change memory device using a graphene, characterized in that selected from metal-based or graphene containing Pt, Ru, Al, Ir, W, Cu. The method of claim 1,
The thickness of the oxide layer is a resistance change memory device using graphene, characterized in that 20nm to 60nm. The method of claim 1,
The oxide layer is a resistance change memory device using a graphene, characterized in that at least one selected from binary metal oxide series or perovskite film. The method according to claim 6,
The binary metal oxide series includes graphene comprising TiO ₂ , NiO, HfO ₂ , SiO ₂ , ZrO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , and Nb ₂ O ₅ . Resistance change memory device used. The method according to claim 6,
The perovskite film SrTiO _3, yes resistance change memory device using a pin, it characterized in that the Nb comprises a doped SrTiO _3, Cr-doped _{SrTiO 3, BaTiO 3, LaMnO 3} , SrMnO 3, PrTiO 3. The method according to claim 6,
The perovskite film includes Pr _{1 - x} Ca _x MnO ₃ (0≤x≤1) and La _{1 - x} Ca _x MnO ₃ (0≤x≤1). Memory elements. The method of claim 1,
The upper electrode is a resistance change memory device using a graphene, characterized in that the layer of several layers of graphene. Providing a memory device comprising a lower electrode, an oxide layer formed on the lower electrode, and a graphene layer formed on the oxide layer;
Programming the memory device to a high resistance state by applying a positive voltage to the graphene layer to generate graphene oxide at an interface between the lower portion of the graphene layer and the oxide layer; And
And applying a negative voltage to the graphene layer to reduce the graphene oxide to program the memory device into a low resistance state. The method of claim 11,
The method of operating the resistance change memory device using graphene, wherein the programming of the low resistance state does not go through a forming process.

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