KR20120103164A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20120103164A
KR20120103164A KR1020110021265A KR20110021265A KR20120103164A KR 20120103164 A KR20120103164 A KR 20120103164A KR 1020110021265 A KR1020110021265 A KR 1020110021265A KR 20110021265 A KR20110021265 A KR 20110021265A KR 20120103164 A KR20120103164 A KR 20120103164A
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KR
South Korea
Prior art keywords
gate
conductive line
semiconductor device
diode
mos
Prior art date
Application number
KR1020110021265A
Other languages
Korean (ko)
Inventor
김용호
Original Assignee
에스케이하이닉스 주식회사
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Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110021265A priority Critical patent/KR20120103164A/en
Publication of KR20120103164A publication Critical patent/KR20120103164A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A semiconductor device is provided to efficiently use an area of the semiconductor device by placing a diode for preventing PID(Plasma Induced Damage) in a surplus space of a gate of an MOS capacitor. CONSTITUTION: Plural drains, channels, and sources are alternately formed in a first direction in an MOS active area(21). Plural gate areas(22) are formed by being extended in a second direction while being overlapped with the area in which channels are formed. Plural diode active areas(23) are formed between plural extended areas of the gate areas. Each first conductive line connects one or more gates with one or more diode actives.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a MOS capacitor having a plasma induced damage (PID) prevention diode inserted therein.

In recent years, as the semiconductor device has been highly integrated, as design rules become smaller and smaller, the spacing between patterns formed on the wafer surface continues to decrease, and the aspect ratio increases. Accordingly, problems that have not occurred or were not important in the process of manufacturing a semiconductor device have appeared.

Among them, PID is generated while the process of using plasma, for example, the deposition or etching process using plasma, is performed to deteriorate the characteristics of the device.

PID is a damage that occurs when a charge trapped on a wafer by plasma ions is discharged in a process using plasma.

Such PID is affected by many causes such as ions and ultra-ultraviolet radiation formed by plasma, and in particular, charging of wafers by ions is known as a main cause.

In particular, in the case of a MOS capacitor, the larger the area of the metal wiring connected to the gate, the larger the PID phenomenon. According to the prior art, in order to provide an artificial path through which ions can escape to prevent such a PID. Although the PID protection diode is formed, there is a problem that the layout area is greatly increased by separately forming the PID protection diode.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a MOS capacitor with a diode inserted for PID prevention suitable for integration.

In order to achieve the above object, the present invention provides a semiconductor device, comprising: a MOS active region in which a plurality of drains, channels, and sources are alternately formed in a first direction; A plurality of gate regions extending in a second direction while overlapping with regions where the plurality of channels are formed; And a plurality of diode active regions formed between the extended regions of the plurality of gate regions.

According to the present invention, it is possible to provide a MOS capacitor inserted with a PID protection diode suitable for integration. In particular, since the PID protection diode is disposed in the surplus space between the gates of the MOS capacitors, a layout area for a separate PID protection diode is not required and the area of the semiconductor device can be efficiently utilized. As a result, integration of semiconductor elements can be achieved.

1 is a layout of a MOS capacitor according to an embodiment of the present invention
2A to 2C are views for explaining an upper conductive line according to an embodiment of the present invention.

In the following, the most preferred embodiment of the present invention is described. In the drawings, the thickness and spacing are expressed for convenience of description and may be exaggerated compared to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. In adding reference numerals to the components of each drawing, it should be noted that the same components as possible have the same number, even if displayed on different drawings.

1 is a layout of a MOS capacitor according to an embodiment of the present invention.

Referring to FIG. 1, an isolation layer 24 is formed in a semiconductor substrate to define a MOS active 21. Here, the MOS active 21 is a region in which a plurality of MOS transistors are formed to form a MOS capacitor, and one MOS transistor is a region in which a drain is formed (hereinafter referred to as a drain D) and a region in which a channel is formed ( Hereinafter, it is divided into a channel, G) and a region in which a source is formed (hereinafter, referred to as a source, S). The neighboring MOS transistors may be arranged to share the source S or the drain D. For example, three gates 22A, 22B, and 22C are illustrated in the drawing, and three MOS transistors may be configured for each gate 22A, 22B, and 22C.

The drain D and the source S are doped with impurities of a polarity opposite to that of the semiconductor substrate. For example, when the semiconductor substrate is P-type, N-type impurities are doped. The drains D and the sources S have the same structure, but are relatively distinguished according to positions disposed in the MOS transistors. For example, in the drawing, the drain D may be the source S of the gate 22A based on the gate 22B. Therefore, in the following description, the source S and the drain D may be used interchangeably unless otherwise specified.

The channel G is a region where the gate 22 is to be formed. At this time, a gate dielectric material (not shown) is disposed between the gate 22 and the channel G of the MOS active 21, and the gate 22 becomes an upper electrode of the MOS capacitor, and the source S and the drain ( D) may be connected to each other to become a lower electrode of the MOS capacitor.

The arrangement example of the gate 22 is formed in the channel G, and is slightly extended in the direction in which the source S and the drain D are not formed. That is, it is formed by being slightly expanded in a direction perpendicular to the direction in which the drain D, the channel G, and the source S are formed.

In addition, a first contact 25 for connecting to an upper conductive line (not shown) is formed in an extended region of the gate 22.

The PID diode active 23 is disposed in the space between the plurality of gate 22 extension regions, for example, between the expansion region of the gate 22A and the expansion region of the gate 22B. In addition, the diode active 23 may be disposed in an area adjacent to the extension region of the gate 22 and the source S or the drain D.

At this time, the diode active 23 is formed by strongly doping N-type impurities when the semiconductor substrate is formed of a P-type. In this case, the semiconductor substrate becomes an anode and the diode active 23 becomes a cathode to form a passage for releasing ions accumulated by the plasma. A second contact 26 is formed in the diode active 23, and is connected to the gate 22 through an upper conductive line to be described later through the second contact 26.

Meanwhile, a third contact 27 is formed in the source S or the drain D for electrical connection with the upper conductive line, which will be described later.

And the well guard 23 is arrange | positioned surrounding the MOS active 21. The well guard 23 is connected to a source S and a drain D. When the MOS transistor is an NMOS, a ground voltage is applied to the well guard 23, or the MOS transistor is connected to a PMOS. PMOS), a power supply voltage is applied to the well guard 23.

2A to 2C are diagrams for explaining an upper conductive line according to an embodiment of the present invention. FIG. 2A is a layout view of a first conductive line, FIG. 2B is a layout view of a second conductive line, and FIG. 2C is a second view. It is a layout which shows the 1st conductive line and the 2nd conductive line together.

Here, the first and second conductive lines 31 and 32 may be metal wirings and are formed on the same layer.

Referring to FIG. 2A, the first conductive line 31 is disposed on the structure including the MOS active 21.

The first conductive line 31 is a conductive line for electrically connecting the gate 22 and the diode active 23. Specifically, the first conductive line 31 is electrically connected through the first contact 25 of the gate 22 and the second contact 26 of the diode active 23.

In addition, the first conductive line 31 may be further connected to a first external voltage terminal (not shown). Here, the first external voltage terminal (not shown) is a power supply voltage when the MOS capacitor is an NMOS transistor. Or, when the MOS capacitor is a PMOS transistor, the ground voltage is obtained.

PID, which may occur at gate 22, is released through diode active 23 so that gate 22 can be protected.

There may be many arrangement examples of the first conductive line 31, but one embodiment of the present invention introduces three arrangement examples. However, the present invention is not limited thereto.

In a first example, the first conductive line 31A may be arranged in a bar shape. More specifically, the first contact 25 disposed in the extended region of the gate 22 and the second contact 26 of the diode active 23 adjacent to the first contact 25 may be electrically connected to each other. have.

In a second example, the first conductive line 31C may be arranged in the shape of a concave portion of unevenness. At this time, the first conductive line 31C connects the first contact 26 disposed in one extension area of the gate 22 and the first contact 26 disposed in the other extension area of the gate 22. And extend from the first contact 26 to the second contact 26 of the adjacent diode active 23.

In a third example, the first conductive line 31B extends further in the direction of the neighboring gate 22 in the first conductive line arrangement example of the second example, so that the first conductive line 31B is electrically connected to the first contact 25 of the neighboring gate 22. Can be arranged to connect. In this case, the upper electrodes of the plurality of MOS capacitors may be connected to each other by the first conductive line 31B. As a more specific example, the first conductive line 31B disposed in the gate 22B connects the first contact 25 of the extended region of the gate 22B, and the second contact of the neighboring diode active 23 ( 26 and the first contact 25 of the neighboring gate 22C.

Referring to FIG. 2B, the second conductive line 32 disposed on the same layer as the first conductive line 31 is spaced apart from the first conductive line 31 while the source S and the drain D are interconnected. To be connected. The second conductive line 32 may be arranged to be deformed according to the shape of the first conductive line 31. For example, in the drawing, the second conductive line 32 may have a convex shape of irregularities. Introduce the deployed example.

In this case, the second conductive line 32 is formed to extend in the direction of the well guard 28 so as not to contact the first conductive line 31 while overlapping the gate 22.

The second conductive line 32 is connected to the source S or the drain D through the third contact 27, and the second conductive line 32 is the well guard 28 and the fourth contact 30. It is electrically connected through. As a result, the second conductive line 32 may electrically connect the source S, the drain D, and the well guard 28 so that the MOS transistor becomes the lower electrode of the MOS capacitor.

Referring to FIG. 2C, the first conductive line 31 and the second conductive line 32 are spaced apart from each other and disposed to cover the gate 22 as much as possible. This is for a stable power supply by securing a large number of contacts while the first conductive line 31 or the second conductive line 32 is connected to the power supply voltage. However, when the area of the first conductive line 31 and the second conductive line 32 is large in this way, there is a probability that ions by plasma are accumulated in the first conductive line 31 or the second conductive line 32. According to the MOS capacitor layout according to an embodiment of the present invention, the diode active 23 is disposed and connected to the first conductive line 31 to prevent damage to the gate 22 due to PID. have.

In particular, an example of disposing a diode active 23 according to an embodiment of the present invention is provided between an extension region of the gate 22 (or adjacent to a source S or a drain D of an outer portion of the extension region of the gate 22). Area), which is an area in which an existing device isolation layer is formed, and thus does not require a separate area for diode layout for preventing PID.

Thus, according to the MOS capacitor layout according to an embodiment of the present invention, it is possible to provide a layout of the PID protection MOS capacitor suitable for integration.

The present invention is not limited to the above-described embodiments, but can be implemented in various forms, and the above-described embodiments make the disclosure of the present invention complete so that those skilled in the art can fully understand the scope of the invention. It is provided to give. Therefore, it should be noted that the scope of the present invention should be understood by the claims of the present application.

21: MOS Active 22: Gate 23: Diode Active
24 device isolation layer 25 first contact 26 second contact
27: third contact 28: well guard
30: fourth contact 31: first conductive line 32: second conductive line

Claims (6)

A MOS active region in which a plurality of drains, channels, and sources are alternately formed in a first direction;
A plurality of gate regions extending in a second direction while overlapping with regions where the plurality of channels are formed; And
A plurality of diode active regions formed between the extended regions of the plurality of gate regions;
Semiconductor device.
The method of claim 1,
The diode active region is
Further formed in the region adjacent to the drain or the source region of the outer region of the extended region of the outermost gate of the plurality of gates
Semiconductor device.
3. The method according to claim 2 or 3,
Further comprising a plurality of first conductive lines,
Each of the plurality of first conductive lines
Connecting one or more of the gates and one or more of the diode actives
Semiconductor device
The method of claim 3, wherein
Further comprising a plurality of second conductive lines,
Each of the plurality of second conductive lines
Connecting at least one said source with at least one said drain
Semiconductor device.
The method of claim 1,
The first direction and the second direction is perpendicular to each other
Semiconductor device.
The method of claim 4, wherein
And a well guard surrounding the MOS active and the gate electrode.
The plurality of second conductive lines are connected to the well guard
Semiconductor device.
KR1020110021265A 2011-03-10 2011-03-10 Semiconductor device KR20120103164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110021265A KR20120103164A (en) 2011-03-10 2011-03-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110021265A KR20120103164A (en) 2011-03-10 2011-03-10 Semiconductor device

Publications (1)

Publication Number Publication Date
KR20120103164A true KR20120103164A (en) 2012-09-19

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KR1020110021265A KR20120103164A (en) 2011-03-10 2011-03-10 Semiconductor device

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