JP2015216194A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having excellent characteristics and a structure suitable for high integration.SOLUTION: A semiconductor device comprises: a semiconductor substrate 10 including a first conductivity type region (N type region) 11 and a second conductivity type region (P well) 12; a signal line 30 provided on the substrate; a semiconductor element (P type MOST) 20 formed on the first conductivity type region; first wiring 41 connecting the semiconductor element and the signal line; and second wiring 42 connecting the first wiring and the second conductivity type region.

Description

  The present disclosure relates to a semiconductor device and a manufacturing method thereof.

  In recent years, the density of semiconductor devices has been increased. Normally, in the manufacturing process of a semiconductor device, for example, dry etching or chemical vapor deposition (CVD) in a plasma excitation gas is performed in forming a wiring or a via connected to a gate electrode of a transistor. Therefore, a positive charge or a negative charge is charged on the gate electrode, and the characteristics of the transistor are changed. As a result, the circuit may behave unintentionally. This phenomenon is called plasma damage or PID (Plasma Induced Damage).

  Patent Document 1 discloses a method of avoiding plasma damage by using the power supply and the wiring capacitance of GND by connecting the gate electrode of the protected element to the power supply and GND.

JP 2001-60687 A

  However, in Patent Document 1, since the diode remains connected to the circuit in the product, it is a source of leakage current and parasitic capacitance. For this reason, the circuit area may be affected depending on the size of the diode.

  The present disclosure has been made in view of such problems, and an object thereof is to provide a semiconductor device having excellent characteristics and a structure suitable for high integration. It is another object of the present invention to provide a semiconductor device manufacturing method capable of manufacturing such a semiconductor device without being damaged by charging.

  A semiconductor device according to an embodiment of the present disclosure is formed in a substrate including a first conductivity type region and a second conductivity type region, a signal line provided on the substrate, and a first conductivity type region of the substrate. A semiconductor device, a first wiring connecting the semiconductor device and a signal line, and a second wiring connecting the first wiring and the second conductivity type region.

  Another semiconductor device according to an embodiment of the present disclosure includes a semiconductor element and a signal line provided over a substrate, a first wiring that connects the semiconductor element and the signal line, and one end connected to the first wiring. The other end is exposed to the end portion or is covered with an insulating material.

  In the semiconductor device as one embodiment of the present disclosure, the second wiring (or the second wiring and the second conductivity type region connected thereto) branched from the first wiring connecting the semiconductor element and the signal line is provided. I prepared. For this reason, hydrogen from the outside or as an impurity contained in itself is occluded in the second wiring or (second wiring and second conductivity type region).

  A method of manufacturing a semiconductor device according to an embodiment of the present disclosure includes: forming a protection element and a semiconductor element on a substrate; a first wiring having one end connected to the semiconductor element on the substrate; Forming a second wiring connecting the wiring and the protective element, forming a signal line connected to the other end of the first wiring, and removing the protective element after forming the signal line; Is included.

  According to another method of manufacturing a semiconductor device as an embodiment of the present disclosure, an impurity is implanted into a first conductivity type substrate, so that a lower first conductivity type semiconductor layer and an upper first conductivity type semiconductor layer are interposed. The lower second conductive semiconductor layer is formed, and an impurity is further added to a predetermined region of the upper first conductive semiconductor layer so that the lower second conductive semiconductor layer is connected to the upper first conductive layer. Forming an upper second conductive type semiconductor layer penetrating the conductive type semiconductor layer in the thickness direction; forming a semiconductor element on the upper first conductive type semiconductor layer; and a first end connected to the semiconductor element. Forming a wiring and a second wiring connecting the first wiring and the upper second conductive type semiconductor layer, forming a signal line connected to the other end of the first wiring, After forming the line, the lower first conductive type semiconductor layer and Parts is obtained by such and removing the second conductive semiconductor layer.

  In the method for manufacturing a semiconductor device according to an embodiment of the present disclosure, after forming the second wiring that connects the first wiring connected to the semiconductor element and the protection element (or the upper second conductivity type semiconductor layer), A signal line was formed. For this reason, when the signal line is formed, damage such as plasma damage to the semiconductor element is avoided. Furthermore, since the protective element (or the lower first conductive type semiconductor layer and the lower second conductive type semiconductor layer) is removed after the formation of the signal line, generation of leakage current and parasitic capacitance is avoided. This is also advantageous for reducing the occupied area.

  According to the semiconductor device as one embodiment of the present disclosure, since the second wiring connected to the first wiring that connects the semiconductor element and the signal line is provided, it is provided from the outside or inside itself. Hydrogen as an impurity contained can be occluded in the second conductivity type region or the second wiring. Therefore, entry of hydrogen into the semiconductor element can be suppressed, and deterioration of the semiconductor element characteristics due to generation of positive charges in the semiconductor element can be avoided.

  According to the method for manufacturing a semiconductor device as one embodiment of the present disclosure, damage to the semiconductor element in the manufacturing process can be avoided by using the protection element. In addition, since the protective element or the like that may cause a leakage current or a parasitic capacitance is finally removed, the occupation area can be reduced while improving the reliability. Therefore, a semiconductor device having excellent characteristics and a structure suitable for high integration can be manufactured.

  Note that the effects of the present disclosure are not limited to those described above, and may be any of the effects described below.

2A and 2B are a plan view and a cross-sectional view illustrating a configuration example of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a circuit diagram corresponding to a configuration example of the semiconductor device illustrated in FIG. 1. FIG. 3 is a cross-sectional view illustrating a step in the method for manufacturing the semiconductor device illustrated in FIG. 1. It is sectional drawing showing the 1 process following FIG. 3A. It is sectional drawing showing the 1 process following FIG. 3B. It is sectional drawing showing the 1 process following FIG. 3C. It is sectional drawing showing the 1 process following FIG. 3D. It is sectional drawing showing the 1 process following FIG. 3E. FIG. 2 is a first circuit diagram for explaining an operation effect of the semiconductor device shown in FIG. 1. FIG. 2 is a first circuit diagram for explaining an operation effect of the semiconductor device shown in FIG. 1. It is sectional drawing showing the 1st modification of the semiconductor device which concerns on 1st Embodiment of this indication. FIG. 6 is a cross-sectional view illustrating a step in a method for manufacturing a semiconductor device as a first modification illustrated in FIG. 5. It is sectional drawing showing the 1 process following FIG. 6A. It is sectional drawing showing the 2nd modification of the semiconductor device which concerns on 1st Embodiment of this indication. It is sectional drawing showing the 3rd modification of the semiconductor device which concerns on 1st Embodiment of this indication. It is sectional drawing showing the structural example of the semiconductor device which concerns on 2nd Embodiment of this indication. FIG. 10 is an explanatory diagram illustrating a step in the method of manufacturing the semiconductor device illustrated in FIG. It is explanatory drawing showing the 1 process following FIG. 10A. It is sectional drawing showing the structural example of the semiconductor device as a 1st reference example. It is sectional drawing showing the structural example of the semiconductor device as a 2nd reference example. It is sectional drawing showing the structural example of the semiconductor device as a 3rd reference example.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.
1. First Embodiment (Semiconductor device in which protective element and semiconductor element (P-type MOST) are stacked, and method for manufacturing the same)
2. Modification 1 (example in which a plurality of semiconductor elements are formed on one protective element)
3. Modification 2 (example using N-type MOST as a semiconductor element)
4). Modification 3 (example combining Modification 1 and Modification 2)
5. Second embodiment (an example in which a protection element and a semiconductor element are formed in the same layer)

<First Embodiment>
[Configuration of Semiconductor Device 1]
FIG. 1 illustrates a planar configuration and a cross-sectional configuration of a semiconductor device 1 according to the first embodiment of the present disclosure. FIG. 2 shows a circuit configuration of the semiconductor device 1. In FIG. 1, the signal line 30, the first wiring 41, and the second wiring 42 are not shown in the diagram showing the planar configuration (all will be described later).

  The semiconductor device 1 includes, for example, a semiconductor substrate 10, a P-type MOST (Metal Oxide Semiconductor Transistor) 20 as a semiconductor element, and a signal line 30 provided on the semiconductor substrate 10.

  The semiconductor substrate 10 includes an N type region 11 made of, for example, an N type silicon substrate, and a P well (P type region) 12. The P well 12 extends from the front surface 10 </ b> A of the semiconductor substrate 10 to the back surface 10 </ b> B of the semiconductor substrate 10.

  The P-type MOST 20 is formed in the N-type region 11 of the semiconductor substrate 10. The P-type MOST 20 has a gate 21 and a pair of source / drain 22 provided on both sides thereof. A P + diffusion layer 13 is formed in the vicinity of the surface 10A of the P well 12. The gate 21 of the P-type MOST 20 is connected to the signal line 30 by the first wiring 41. The intermediate point 41 </ b> A of the first wiring 41 and the P + diffusion layer 13 are connected by the second wiring 42.

[Operation and Effect of Semiconductor Device 1]
The semiconductor device 1 includes a second wiring 42 branched from an intermediate point 41A of the first wiring 41 that connects the P-type MOST 20 and the signal line 30, and a P + diffusion layer 13 and a P well 12 connected thereto. did. For this reason, hydrogen from the outside or as an impurity contained in itself is occluded in the second wiring 42, the P + diffusion layer 13 and the P well 12.

  That is, according to the semiconductor device 1, the entry of hydrogen into the P-type MOST 20 can be suppressed, and the deterioration of the semiconductor element characteristics accompanying the generation of positive charges inside the P-type MOST 20 can be avoided. As a result, high reliability can be ensured.

[Method of Manufacturing Semiconductor Device 1]
The semiconductor device 1 is manufactured by a manufacturing method including the following steps (1) to (4).
(1) The diode 50 and the P-type MOST 20 as protective elements are formed on the semiconductor substrate 10.
(2) Forming on the semiconductor substrate 10 a first wiring 41 having one end connected to the gate 21 of the P-type MOST 20 and a second wiring 42 connecting the first wiring 41 and the diode 50.
(3) The signal line 30 connected to the other end of the first wiring 41 is formed.
(4) After forming the signal line 30, the diode 50 is removed.
Specifically, for example, it can be produced as follows.

  3A to 3F are cross-sectional views showing a part of the manufacturing method of the semiconductor device 1 in the order of steps. First, for example, an N-type silicon substrate 11Z is prepared (FIG. 3A). Next, as indicated by arrows, for example, trivalent ions (hereinafter referred to as impurity element ions) are implanted into the silicon substrate 11Z from the surface 11ZA of the silicon substrate 11Z (FIG. 3B). Thereby, a stacked structure of the lower N-type semiconductor layer 11L, the lower P-well 12L, and the upper N-type semiconductor layer 11U is formed. Among these, the two-layer structure of the lower N-type semiconductor layer 11L and the lower P well 12L forms the diode 50.

  Next, impurity element ions are selectively implanted into a portion of the upper N-type semiconductor layer 11U that occupies a predetermined region other than a region where the P-type MOST 20 is to be formed later. Thereby, the first upper P well 12U1 is formed (FIG. 3C).

  Further, a second upper P well 12U2 is formed by selectively implanting impurity element ions into a portion of the upper N-type semiconductor layer 11U that covers the first upper P well 12U1 (FIG. 3D). Thereby, an upper P well 12U penetrating the upper N-type semiconductor layer 11U is formed on the lower P well 12L. Here, the position in the depth direction where the impurity element ions are implanted may be adjusted by increasing or decreasing the energy when implanting the impurity element ions. For example, it is better to weaken the implantation energy of impurity element ions when forming the first upper P well 12U1 than when forming the lower P well 12L. Similarly, when the second upper P well 12U2 is formed rather than the first upper P well 12U1, the impurity element ion implantation energy is preferably weakened.

  Thereafter, as shown in FIG. 3E, a P-type MOST 20 is formed at a predetermined position of the upper N-type semiconductor layer 11U, and a P + diffusion layer 13 is formed in the vicinity of the surface 10A of the upper P-well 12U. Further, after forming the first wiring 41 and the second wiring 42, a circuit including the signal line 30 is formed. Finally, as shown in FIG. 3F, the diode 50 is removed by a polishing process or the like.

  Thus, the semiconductor device 1 is completed.

[Operational Effects of Manufacturing Method of Semiconductor Device 1]
As described above, in the method of manufacturing the semiconductor device 1, the diode 50 is formed, the first wiring 41 and the second wiring 42 that connects the P-type MOST 20 and the diode 50 are formed, and then the signal line 30 and the like are formed. It was made to form (refer FIG. 4A). For this reason, when forming the signal line 30 and the like, the diode 50 functions as a protection circuit even if, for example, dry etching or chemical vapor deposition (CVD) in plasma excitation gas is performed, and plasma damage to the P-type MOST 20 is caused. Etc. are avoided. Furthermore, since the diode 50 is removed after the formation of the signal line 30 and the like (see FIG. 4B), generation of leakage current and parasitic capacitance is avoided, and it is advantageous in reducing the occupied area.

  However, as shown in FIG. 11A, for example, in the semiconductor device 101 in which the P + diffusion layer 113 is provided in the vicinity of the surface of the N-type region 111, the PN diode 150 functions as a protective element. Plasma damage may not be avoided. In recent years, in flash memory and image sensors, LSI stacking using TSV (Through Silicon Via) processed deeper than normal vias has progressed, and there is a possibility of greater plasma damage. is there. In an ESD protection circuit or the like connected to an input / output with the outside, TSV may be frequently used for circuit design. In such a case, plasma damage to the P-type MOST 20 may not be avoided unless a large protection diode is installed.

  In order to cope with the generation of a large charge, for example, a method of arranging a large area PN diode 150 as a protective element by providing a large area P + diffusion layer 113A as in the semiconductor device 102 shown in FIG. 11B can be considered. Further, for example, as in the semiconductor device 103 shown in FIG. 11C, a measure may be considered in which NP diodes 151A and 151B each including an N + diffusion layer 114 and a P well 112 are arranged in series as protective elements. However, these cases are disadvantageous in terms of standby leakage current, parasitic capacitance, or circuit area.

  On the other hand, according to the manufacturing method of the semiconductor device 1 of the present disclosure, damage to the P-type MOST 20 in the manufacturing process can be avoided by using the diode 50 as a protection element. In addition, since the diode 50 that may be a source of leakage current and parasitic capacitance is finally removed, there is no adverse effect on the operation of the P-type MOST 20. That is, reliability can be improved. In addition, since the diode 50 used as the protective element is finally removed, there is no occurrence of standby leakage current or parasitic capacitance. Even when the diode 50 having a sufficiently large area is formed to cope with the occurrence of large plasma damage, the size of the semiconductor device 1 as the final product is not increased. Therefore, according to the manufacturing method of the semiconductor device 1, the semiconductor device 1 having excellent characteristics and a structure suitable for high integration can be manufactured.

<First Modification>
FIG. 5 illustrates a cross-sectional configuration of a semiconductor device 1 </ b> A as a first modification of the semiconductor device 1. In the semiconductor device 1A, a plurality of P-type MOSTs 20 (20A, 20B), a plurality of P wells 12 (12A, 12B) and a P + diffusion layer 13 (13A, 13B) corresponding to them are provided on the semiconductor substrate 10. did. Further, a plurality of signal lines 30 (30A, 30B), a plurality of first wirings 41 (41A, 41B), and a plurality of second wirings 42 (42A, 42B) corresponding to the plurality of P-type MOSTs 20 (20A, 20B). 42B).

  In manufacturing the semiconductor device 1A, for example, as shown in FIG. 6A, a common diode 50 is formed for a plurality of P-type MOSTs 20, and a plurality of first wirings 41 and a plurality of second wirings are formed. After the wiring 42 is formed, a plurality of signal lines 30 are formed. After that, as shown in FIG. 6B, the unnecessary diode 50 is removed by polishing or the like, whereby the semiconductor device 1A having a plurality of P-type MOSTs 20 that are individually electrically separated is obtained. Also in this modification, the common diode 50 can protect against a plurality of P-type MOSTs 20 from plasma damage.

<Second Modification>
FIG. 7 illustrates a cross-sectional configuration of a semiconductor device 1 </ b> B as a second modification of the semiconductor device 1. In the semiconductor device 1 described above, the case where the P-type MOST 20 is provided as the semiconductor element has been described, but the present technology is not limited to this. The present technology is also applied to a case where an N-type MOST 60 having a gate 61 and a pair of source / drain 62 provided on both sides thereof is provided as a semiconductor element as in the semiconductor device 1B shown in FIG. Is done.

<Third Modification>
FIG. 8 illustrates a cross-sectional configuration of a semiconductor device 1 </ b> C as a third modification of the semiconductor device 1. In the semiconductor device 1A as the first modification described above, the case where a plurality of P-type MOSTs 20 are provided as semiconductor elements has been described, but the present technology is not limited to this. The present technology is also applied to a case where a P-type MOST 20 and an N-type MOST 60 are provided as semiconductor elements on the same semiconductor substrate as in the semiconductor device 1C illustrated in FIG.

<Second Embodiment>
[Configuration of Semiconductor Device 2]
FIG. 9 illustrates a configuration of the semiconductor device 2 according to the second embodiment of the present disclosure. The semiconductor device 2 includes a P-type MOST 20 and a signal line 30 provided on the semiconductor substrate 10, a first wiring 41 that connects the P-type MOST 20 and the signal line 30, and one end connected to the first wiring 41. And a second wiring 42 having the other end exposed at the end. Note that the other end of the second wiring 42 may be covered with an insulating material.

[Method of Manufacturing Semiconductor Device 2]
10A and 10B show a part of the manufacturing method of the semiconductor device 2 in the order of steps. In the method for manufacturing the semiconductor device 2, the protection element and the semiconductor element are formed in the same layer. Specifically, first, a P-type MOST 20 as a semiconductor element is formed in the element formation region R1 of the semiconductor substrate 10, and a protective element is provided in a peripheral region (scribe region) R2 located around the element formation region R1. The diode 50 is formed (FIG. 10A). Further, after forming the first wiring 41 and the second wiring 42, a circuit including the signal line 30 is formed. Finally, the semiconductor substrate 10 is diced to separate the peripheral region R2 from the element formation region R1 (FIG. 10B). During dicing, the other end of the second wiring 42 is exposed on the cut surface, but the other end of the second wiring 42 may be covered with an insulating material as necessary. Thus, the semiconductor device 2 is completed.

[Operational Effects of Semiconductor Device 2 and its Manufacturing Method]
Such a semiconductor device 2 can also exhibit functions similar to those of the semiconductor device 1 of the first embodiment. That is, the semiconductor device 2 includes the second wiring 42 branched from the intermediate point 41A of the first wiring 41 that connects the P-type MOST 20 and the signal line 30, and the diode 50 connected thereto. For this reason, hydrogen as an impurity from the outside or contained in itself is occluded in the second wiring 42. Therefore, according to the semiconductor device 2, it is possible to suppress the entry of hydrogen into the P-type MOST 20, and to avoid the deterioration of the semiconductor element characteristics due to the generation of positive charges inside the P-type MOST 20.

  Furthermore, unlike the semiconductor device 1 in the first embodiment, the semiconductor device 2 does not include a region in which the P + diffusion layer 13 and the P well 12 are formed. Therefore, the structure is more suitable for higher integration than the semiconductor device 1.

  Moreover, according to the manufacturing method of the semiconductor device 2, damage to the P-type MOST 20 in the manufacturing process can be avoided by using the diode 50 as a protective element. In addition, since the diode 50 that may be a source of leakage current and parasitic capacitance is finally removed, there is no adverse effect on the operation of the P-type MOST 20. That is, reliability can be improved. In addition, since the diode 50 used as the protective element is finally removed, there is no occurrence of standby leakage current or parasitic capacitance. Further, even when the diode 50 having a sufficiently large area is formed in order to cope with the occurrence of large plasma damage, the size of the semiconductor device 2 as the final product is not increased. Therefore, the semiconductor device 2 having excellent characteristics and a structure suitable for high integration can be manufactured.

  The present technology has been described above with some embodiments and modifications. However, the present technology is not limited to the above-described embodiments and the like, and various modifications can be made. For example, in the above-described embodiments and the like, an example in which one or two semiconductor elements are provided on the same semiconductor substrate has been described. However, in the present technology, three or more semiconductor elements are provided on the same semiconductor substrate. You can also. In addition, the semiconductor device of the present technique may further include other components other than the components described in the above embodiments and the like.

  In the second embodiment, the P-type MOST is exemplified as the semiconductor element. However, the semiconductor element can be replaced with an N-type MOST. Alternatively, P-type MOST and N-type MOST may be mixed.

In addition, the effect described in this specification is an illustration to the last, and is not limited to the description, There may exist another effect. Moreover, this technique can take the following structures.
(1)
A substrate including a first conductivity type region and a second conductivity type region;
A signal line provided on the substrate;
A semiconductor element formed in the first conductivity type region;
A first wiring connecting the semiconductor element and the signal line;
A semiconductor device comprising: the first wiring and a second wiring connecting the second conductivity type region.
(2)
The semiconductor device according to (1), wherein the second conductivity type region extends from a front surface of the substrate to a back surface of the substrate.
(3)
The semiconductor device according to (1) or (2), wherein the semiconductor element is a MOS (Metal Oxide Semiconductor) transistor.
(4)
The semiconductor device according to any one of (1) to (3), wherein the first conductivity type region is a p-type region, and the second conductivity type region is an n-type region.
(5)
A semiconductor element and a signal line provided on the substrate;
A first wiring connecting the semiconductor element and the signal line;
And a second wiring having one end connected to the first wiring and the other end exposed at the end or covered with an insulating material.
(6)
Forming a protective element and a semiconductor element on a substrate;
Forming a first wiring having one end connected to the semiconductor element and a second wiring connecting the first wiring and the protection element on the substrate;
Forming a signal line connected to the other end of the first wiring;
Removing the protective element after forming the signal line. A method for manufacturing a semiconductor device.
(7)
The semiconductor device manufacturing method according to (6), wherein a diode including a stacked structure of a first conductive semiconductor layer and a second conductive semiconductor layer is formed as the protective element.
(8)
A first conductivity type semiconductor substrate is used as the substrate,
By implanting impurity element ions into the first conductive semiconductor substrate using an ion implantation method, the first conductive semiconductor layer is separated into a lower first conductive semiconductor layer and an upper first conductive semiconductor layer. The method for manufacturing a semiconductor device according to (7), wherein the second conductive semiconductor layer is formed.
(9)
By further implanting impurity element ions into a partial region of the upper first conductive type semiconductor layer covering the second conductive type semiconductor layer using an ion implantation method, the second conductive type semiconductor layer is formed on the second conductive type semiconductor layer. The method for manufacturing a semiconductor device according to (8), wherein an additional second conductivity type semiconductor layer penetrating the upper first conductivity type semiconductor layer is formed.
(10)
The method for manufacturing a semiconductor device according to any one of (7) to (9), wherein the stacked structure is removed by a polishing process.
(11)
A method of manufacturing a semiconductor device according to any one of (6) to (10), wherein a MOS (Metal Oxide Semiconductor) transistor is formed as the semiconductor element.
(12)
Forming a lower second conductive semiconductor layer sandwiched between the lower first conductive semiconductor layer and the upper first conductive semiconductor layer by implanting impurities into the first conductive type substrate;
By further adding the impurity to a predetermined region of the lower first conductive semiconductor layer, the upper first conductive semiconductor layer is connected to the lower second conductive semiconductor layer and penetrates the upper first conductive semiconductor layer in the thickness direction. Forming a two-conductivity type semiconductor layer;
Forming a semiconductor element in the upper first conductivity type semiconductor layer;
Forming a first wiring having one end connected to the semiconductor element, and a second wiring connecting the first wiring and the upper second conductive type semiconductor layer;
Forming a signal line connected to the other end of the first wiring;
Removing the lower first conductive semiconductor layer and the lower second conductive semiconductor layer after forming the signal line. A method of manufacturing a semiconductor device.
(13)
The method of manufacturing a semiconductor device according to (12), wherein the lower second conductive semiconductor layer and the upper second conductive semiconductor layer are formed by implanting impurity element ions as the impurities using an ion implantation method.
(14)
The implantation energy of the impurity element ions at the time of forming the lower second conductive type semiconductor layer is made larger than the implantation energy of the impurity element ions at the time of forming the upper second conductive type semiconductor layer (13) The manufacturing method of the semiconductor device of description.
(15)
The method for manufacturing a semiconductor device according to (13), wherein when the lower second conductive type semiconductor layer is formed, the implantation energy of the impurity element ions is gradually reduced.
(16)
The method for manufacturing a semiconductor device according to any one of (12) to (15), wherein the lower first conductive semiconductor layer and the lower second conductive semiconductor layer are removed by a polishing process.

  DESCRIPTION OF SYMBOLS 1,1A-1C, 2 ... Semiconductor device, 10 ... Semiconductor substrate, 11 ... N-type area | region, 12 ... P well, 13 ... P + diffusion layer, 20 ... P-type MOST, 30 ... Signal line, 41 ... 1st wiring 42 ... second wiring, 50 ... diode, 60 ... N-type MOST.

Claims (16)

A substrate including a first conductivity type region and a second conductivity type region;
A signal line provided on the substrate;
A semiconductor element formed in the first conductivity type region;
A first wiring connecting the semiconductor element and the signal line;
A semiconductor device comprising: the first wiring and a second wiring connecting the second conductivity type region. The semiconductor device according to claim 1, wherein the second conductivity type region extends from a front surface of the substrate to a back surface of the substrate. The semiconductor device according to claim 1, wherein the semiconductor element is a MOS (Metal Oxide Semiconductor) transistor. The semiconductor device according to claim 1, wherein the first conductivity type region is a p-type region, and the second conductivity type region is an n-type region. A semiconductor element and a signal line provided on the substrate;
A first wiring connecting the semiconductor element and the signal line;
And a second wiring having one end connected to the first wiring and the other end exposed at the end or covered with an insulating material. Forming a protective element and a semiconductor element on a substrate;
Forming a first wiring having one end connected to the semiconductor element and a second wiring connecting the first wiring and the protection element on the substrate;
Forming a signal line connected to the other end of the first wiring;
Removing the protective element after forming the signal line. A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 6, wherein a diode including a stacked structure of a first conductivity type semiconductor layer and a second conductivity type semiconductor layer is formed as the protection element. A first conductivity type semiconductor substrate is used as the substrate,
By implanting impurity element ions into the first conductive semiconductor substrate using an ion implantation method, the first conductive semiconductor layer is separated into a lower first conductive semiconductor layer and an upper first conductive semiconductor layer. The method for manufacturing a semiconductor device according to claim 7, wherein the second conductivity type semiconductor layer is formed. By further implanting impurity element ions into a partial region of the upper first conductive type semiconductor layer covering the second conductive type semiconductor layer using an ion implantation method, the second conductive type semiconductor layer is formed on the second conductive type semiconductor layer. The method for manufacturing a semiconductor device according to claim 8, wherein an additional second conductivity type semiconductor layer penetrating the upper first conductivity type semiconductor layer is formed. The method for manufacturing a semiconductor device according to claim 7, wherein the laminated structure is removed by a polishing process. The method for manufacturing a semiconductor device according to claim 6, wherein a MOS (Metal Oxide Semiconductor) transistor is formed as the semiconductor element. Forming a lower second conductive semiconductor layer sandwiched between the lower first conductive semiconductor layer and the upper first conductive semiconductor layer by implanting impurities into the first conductive type substrate;
By further adding the impurity to a predetermined region of the lower first conductive semiconductor layer, the upper first conductive semiconductor layer is connected to the lower second conductive semiconductor layer and penetrates the upper first conductive semiconductor layer in the thickness direction. Forming a two-conductivity type semiconductor layer;
Forming a semiconductor element in the upper first conductivity type semiconductor layer;
Forming a first wiring having one end connected to the semiconductor element, and a second wiring connecting the first wiring and the upper second conductive type semiconductor layer;
Forming a signal line connected to the other end of the first wiring;
Removing the lower first conductive semiconductor layer and the lower second conductive semiconductor layer after forming the signal line. A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 12, wherein the lower second conductive semiconductor layer and the upper second conductive semiconductor layer are formed by implanting impurity element ions as the impurities using an ion implantation method. 14. The implantation energy of the impurity element ions at the time of forming the lower second conductive semiconductor layer is made larger than the implantation energy of the impurity element ions at the time of forming the upper second conductivity type semiconductor layer. Semiconductor device manufacturing method. The method of manufacturing a semiconductor device according to claim 13, wherein when forming the lower second conductive type semiconductor layer, the implantation energy of the impurity element ions is gradually reduced. The method of manufacturing a semiconductor device according to claim 12, wherein the lower first conductive semiconductor layer and the lower second conductive semiconductor layer are removed by a polishing process.

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