KR20120100504A - Stereoscopic image display and method of fabricatng upper plate thereof - Google Patents

Abstract

PURPOSE: A stereoscopic image display device and an upper plate manufacturing method thereof are provided to enlarge a vertical viewing angle and increase brightness of a 2D image. CONSTITUTION: A pattern retarder(300) is matched with a liquid crystal display panel. The pattern retarder passes first polarization light through a first pattern. The pattern retarder passes second polarization light through a second pattern. Polarized glasses(310) comprise a left-eye filter and a right-eye filter. Only the first polarization light passes through the left-eye filter. Only the second polarization light passes through the right-eye filter.

Description

STEREOSCOPIC IMAGE DISPLAY AND METHOD OF FABRICATNG UPPER PLATE THEREOF}

The present invention relates to a stereoscopic image display device and a top plate manufacturing method thereof.

The stereoscopic image display device implements a stereoscopic image, that is, a three-dimensional (3D) image by using a stereoscopic technique or an autostereoscopic technique. The binocular parallax method uses a parallax image of the left and right eyes with a large stereoscopic effect, and there are glasses and no glasses, both of which are put to practical use. The spectacle method realizes a stereoscopic image by using polarizing glasses or liquid crystal shutter glasses to display the right and left parallax images in a direct view type display device or a projector by changing the polarization directions of the parallax images in a time division manner. In the autostereoscopic method, an optical plate such as a parallax barrier for separating an optical axis of a left and right parallax image is generally provided in front of a display screen.

The glasses type stereoscopic image display device is divided into polarized glasses and shutter glasses. In the polarizing glasses method, a polarization splitter such as a patterned retarder must be bonded to the display panel. The pattern retarder separates the polarization of the left eye image and the right eye image displayed on the display panel. When viewing a stereoscopic image on a polarized glasses type stereoscopic display device, the viewer wears polarized glasses to see the polarization of the left eye image through the left eye filter of the polarizing glasses and the polarization of the right eye image through the right eye filter of the polarizing glasses. You can feel the three-dimensional effect.

In the conventional stereoscopic image display device of polarized glasses, the display panel may be applied as a liquid crystal display panel. Due to the thickness of the upper glass substrate of the liquid crystal display panel and the thickness of the upper polarizing plate, the vertical viewing angle is bad due to the parallax between the pixel array of the liquid crystal display panel and the pattern retarder. In this case, when the viewer views a stereoscopic image displayed on a polarized glasses type stereoscopic image display device at a higher or lower viewing angle than the front side of the liquid crystal display panel, the left and right eyes are overlapped when viewed in monocular (left or right eye). You can feel the crosstalk.

In order to solve the 3D crosstalk problem of vertical viewing angle in a polarized glasses type stereoscopic display device, Japanese Laid-Open Patent Publication No. 2002-185983 and the like form a black stripe on a pattern retarder as shown in FIG. I have suggested a method. Alternatively, the width of the black matrix formed in the liquid crystal display panel may be increased. However, when the black stripe is formed on the pattern retarder, not only the luminance is lowered in the 2D / 3D image but also the moire may be caused by the interaction of the black matrix and the black stripe. The method of increasing the width of the black matrix lowers the aperture ratio and lowers the luminance in the 2D / 3D image.

The present invention provides a stereoscopic image display device and a top plate manufacturing method capable of enlarging an upper and lower viewing angle, increasing luminance in a 2D image, and increasing an aperture ratio.

The stereoscopic image display device of the present invention includes a liquid crystal display panel having a liquid crystal layer formed between the first and second substrates; A pattern retarder bonded on the liquid crystal display panel and configured to pass first polarized light through a first pattern and pass second polarized light through a second pattern; And polarizing glasses including a left eye filter through which only the first polarization passes and a right eye filter through which only the second polarization passes.

The first substrate includes first and second top common electrodes.

Each of the subpixels of the liquid crystal display panel includes a main pixel portion defined by the first upper common electrode, and an active black stripe defined by the second upper common electrode.

A first common voltage of a reference potential is applied to the first upper common electrode in the 2D mode and the 3D mode. The voltage of the reference potential is applied to the second upper common electrode in the 2D mode, and a voltage swinging between the positive voltage higher than the reference potential and the negative voltage lower than the reference potential in the 3D mode.

The second substrate may include a data line to which a video data voltage is supplied; A gate line crossing the data line and sequentially supplied with a gate pulse; A TFT formed at an intersection of the data line and the gate line; A pixel electrode connected to the TFT; And a storage electrode overlapping an edge of the pixel electrodes, to which a voltage of the reference potential is supplied. At least one of the gate line and the storage electrode faces a boundary between the first upper common electrode and the second upper common electrode.

The storage electrode has an 'H' shape.

The first substrate further includes a column spacer for maintaining a cell gap between the first and second substrates.

The first and second upper plate common electrodes have the same shape and are alternately disposed.

The stereoscopic image display further includes an insulating layer formed between the first and second upper common electrodes at an overlapping portion of the first and second upper common electrodes. The insulating layer includes a material that is lower than the height of the column spacer and is the same as the material of the column spacer.

One TFT is formed for each subpixel. The pixel electrode is shared between the main pixel portion and the active black stripe in each of the subpixels.

The pixel electrode includes a first pixel electrode formed on the main pixel portion, and a second pixel electrode formed on the active black stripe. The TFT includes a first TFT supplying a data voltage from the data line to the first pixel electrode in response to an n (n is positive integer) gate line, and the data line in response to an n + 1 th gate line. And a second TFT for supplying a data voltage from the second pixel electrode.

The manufacturing method of the stereoscopic image display device may include forming a first upper common electrode on the first substrate by using a first photolithography process using a first photo mask; Forming an insulating layer on a portion of the first upper common electrode using a first photolithography process using a second photo mask; And forming a second upper common electrode on the first substrate by using a third photolithography process using the first photo mask.

The second upper common electrode overlaps the first upper common electrode with the insulating layer interposed therebetween.

The present invention forms the first and second top common electrodes on the top plate to form a main pixel portion displaying a 2D / 3D image on each of the subpixels, and an active black stripe displaying a 2D image and acting as a black stripe in 3D mode. do. As a result, the present invention can enlarge the vertical viewing angle in the stereoscopic image display device, increase the luminance in the 2D image, and increase the aperture ratio.

1 is a view schematically showing a stereoscopic image display device according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating driving circuits of the liquid crystal display panel illustrated in FIG. 1.
3 is a cross-sectional view illustrating a vertical cross-sectional structure of the liquid crystal display panel illustrated in FIG. 1.
4 is an equivalent circuit diagram of a subpixel according to the first embodiment of the present invention.
FIG. 5 is a plan view illustrating an implementation of the subpixel illustrated in FIG. 4.
FIG. 6 is a plan view illustrating another implementation of the subpixel illustrated in FIG. 4.
7 is a waveform diagram illustrating a common voltage applied to the first and second upper common electrodes in the 2D mode.
FIG. 8 is a waveform diagram illustrating a common voltage applied to the first and second upper common electrodes in the 3D mode.
9 is an equivalent circuit diagram of a subpixel according to the second embodiment of the present invention.
FIG. 10 is a plan view illustrating an implementation of the subpixel illustrated in FIG. 9.
11 is a plan view illustrating an increase in resistance of the first and second upper common electrodes.
12 is a plan view illustrating a pattern of first and second top common electrodes according to an exemplary embodiment of the present invention.
13A through 13D are cross-sectional views illustrating a manufacturing process of the upper common electrode by cutting along the line “I ′” in FIG. 12.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 to 3, a stereoscopic image display device according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a pattern retarder 300, and polarizing glasses 310.

The liquid crystal display panel 100 displays 2D image and 3D image data. The liquid crystal display panel 100 includes a liquid crystal layer formed between two glass substrates. The liquid crystal display panel 100 includes pixels arranged in a matrix by a cross structure of the data lines DL and the gate lines GL. Each of the pixels is implemented by a liquid crystal cell and includes an R subpixel, a G subpixel, and a B subpixel.

Data lines DL, gate lines GL, TFTs, pixel electrodes PIX, storage capacitors Cst, and the like are formed on the TFT array substrate SUBS2 of the liquid crystal display panel 100. The TFT supplies the data voltage from the data line DL to the pixel electrode PIX in response to the gate pulse from the gate line GL. For this purpose, the drain electrode DE of the TFT is connected to the data line DL and its source electrode SE is connected to the pixel electrode PIX. The gate electrode GE of the TFT is connected to the gate line GL. In FIG. 3, "GI" is a gate insulating film covering the gate metal patterns including the gate electrode GE, the gate line GL, the storage electrode STRG, and the like of the TFT. The storage capacitor Cst includes a pixel electrode PIX, a storage electrode STRG, and dielectrics GI and PASSI formed between the electrodes PIX and STRG. &Quot; SEMI " is a semiconductor channel between the drain electrode and the source electrode of the TFT and includes an active layer and an ohmic contact layer. "PASSI" is a passivation layer covering a TFT and covering a source / drain metal including the source / drain electrodes SE and DE of the TFT, the data line DL, and the like. The pixel electrode PIX is formed of a transparent conductive pattern connected to the source electrode SE of the TFT through a contact hole penetrating through the passivation layer PASSI. The transparent conductive pattern may be selected as indium tin oxide (ITO).

The black matrix BM, the color filter CF, and the upper common electrodes COM1 and COM2 are formed on the color filter array substrate SUBS1 of the liquid crystal display panel 100. The upper common electrodes COM1 and COM2 are separated into a first upper common electrode COM1 and a second upper common electrode COM2. The upper common electrodes COM1 and COM2 may be patterned in a transparent conductive pattern such as ITO. Each of the RGB subpixels includes a main pixel portion defined by the first upper common electrode COM1 and an active black stripe defined by the second upper common electrode COM2. Thus, a boundary between the first upper common electrode COM1 and the second upper common electrode COM2 is present in the RGB subpixels. The main pixel unit displays data of the input image in the 2D mode and the 3D mode. In contrast, the active black stripe serves as a pixel for displaying the data of the input image in the 2D mode, whereas the active black stripe serves as a black stripe for extending the vertical viewing angle by displaying the black gray level in the 3D mode. The main pixel portion and the active black stripe may be interchanged or their sizes may be changed depending on the positions and sizes of the first upper common electrode COM1 and the second upper common electrode COM2.

Polarizing plates POL1 and POL2 are bonded to each of the TFT array substrate SUBS2 and the color filter array substrate SUBS1 of the liquid crystal display panel 100, and an alignment layer for setting a pre-tilt angle of the liquid crystal ( ALM1, ALM2) are formed. A column spacer CS may be formed between the TFT array substrate SUBS2 and the color filter array substrate SUBS1 to maintain a cell gap of the liquid crystal layer.

The liquid crystal cells are driven by a vertical electric field between the pixel electrode PIX formed on the TFT array substrate SUBS2 and the top common electrodes COM1 and COM2 formed on the color filter array substrate SUBS1, thereby driving the color filter array substrate SUBS1. Adjust the amount of light passing through the upper polarizing plate (POL1) formed in the. Each of the pixels displays an image using a liquid crystal cell driven according to a video data voltage applied to the pixel electrode.

The liquid crystal display panel 100 may be implemented by a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode. The liquid crystal display panel 100 may be driven in a normally white mode. In the normally white mode, the light transmittance of the liquid crystal cell decreases as the potential difference between the pixel electrode Vcom and the upper common electrodes COM1 and COM2 increases, and the potential difference between the pixel electrode Vcom and the upper common electrodes COM1 and COM2 decreases. Maximum is minimum.

The backlight unit may be disposed on the rear surface of the liquid crystal display panel 100. The backlight unit is implemented as an edge type or direct type backlight unit to irradiate light to the liquid crystal display panel 100.

The pattern retarder 300 is attached to the upper polarizer of the liquid crystal display panel 100. The pattern retarder 300 may include a first pattern 300a facing the odd-numbered line in the pixel array of the liquid crystal display panel 100 and a second pattern facing the even-numbered line in the pixel array of the liquid crystal display panel 100. 300b. The optical axes of the first pattern 300a and the second pattern 300b are different from each other. The first pattern 300a and the second pattern 300b may be implemented as a birefringent medium that delays the phase of incident light by 1/4 wavelength.

In the pixel array of the liquid crystal display panel 100, the odd-numbered line may display a left eye image and the even-numbered line may display a right eye image. In this case, light of the left eye image displayed on the radix line of the pixel array is incident on the first pattern 300a through linearly polarized light through the upper polarizer, and light of the right eye image displayed on the even line of the pixel array passes through the upper polarizer. The light is incident on the second pattern 300b by linearly polarized light. The linearly polarized light passing through the upper polarizing plate in the odd-numbered line and the linearly polarized light passing through the upper polarizing plate in the even-numbered line are linearly polarized light having the same optical axis. In the pattern retarder 300, the first pattern 300a delays the phase of the linearly polarized light incident through the upper polarizer by 1/4 wavelength to pass the light of the left eye image to the left circularly polarized light. The second pattern 300b delays the phase of the linearly polarized light passing through the upper polarizing plate by 1/4 wavelength to pass the light of the right eye image to the right circularly polarized light.

The left eye polarization filter of the polarizing glasses 310 passes only the left circle polarization, and the right eye polarization filter passes only the right circle polarization. When the viewer wears polarized glasses 310, the viewer sees only the pixels of the odd-numbered lines of the pixel array in which the left eye image is displayed in the left eye, and only the pixels in the even-numbered lines of the pixel array in which the right eye image is displayed in the right eye. You will feel a three-dimensional effect due to binocular parallax.

The stereoscopic image display device of the present invention includes a data driving circuit 102, a gate driving circuit 103, a common voltage switching circuit 106, a data formatter 105, a timing controller 101, a backlight driving circuit, and the like. The backlight driving circuit drives the light source of the backlight unit, and controls the backlight brightness by performing global dimming and local dimming according to the input image under the control of the timing controller 101. The backlight driving circuit is omitted in the drawing.

Each of the source drive ICs of the data driving circuit 102 includes a shift register, a latch, a digital-to-analog converter (DAC), an output buffer, and the like. The data driving circuit 102 latches digital video data RGB of 2D / 3D video under the control of the timing controller 101. The data driving circuit 102 inverts the polarity of the data voltage by converting the digital video data RGB into analog positive gamma compensation voltage and negative gamma compensation voltage in response to the polarity control signal POL. Gamma compensation voltages are generated by a gamma voltage generation circuit (not shown) and supplied to source drive ICs. The data driving circuit 102 outputs the positive / negative data voltage to the data lines DL in response to the source output enable signal SOE. The data driving circuit 102 outputs data voltages (Vdata of FIG. 7) of the 2D image in which the left eye image and the right eye image are not distinguished in the 2D mode. The data driving circuit 102 supplies the data voltage of the left eye image and the data voltage (Vdata of FIG. 8) to the data lines DL in the 3D mode.

The gate driving circuit 103 includes a shift register, a level shifter, and the like. As shown in FIGS. 7 and 8, the gate driving circuit 103 may include a gate pulse (or scan pulse) synchronized with a data voltage supplied to the data lines DL under the control of the timing controller 101. Feed sequentially.

The common voltage switching circuit 106 generates the first and second upper common voltages Vcom1 and Vcom2. The first upper common voltage Vcom1 is supplied to the first upper common electrode COM1. In addition, the common voltage switching circuit 106 supplies the storage reference voltage Vstrg set to the DC voltage of the reference potential RL or a similar potential to the storage electrode STRG. The second upper common voltage Vcom2 is supplied to the second upper common electrode COM2. The common voltage switching circuit 106 generates the first and second upper common voltages Vcom1 and Vcom2 as DC voltages of the reference potentials RL of FIGS. 7 and 8 under the control of the timing controller 101 in the 2D mode. . In the 2D mode, the first and second upper common voltages Vcom1 and Vcom2 are equipotential voltages of the reference potential RL. The common voltage switching circuit 106 generates the first upper common voltage Vcom1 as the DC voltage of the reference potential RL under the control of the timing controller 101 as shown in FIG. 8 in the 3D mode, and the second upper common voltage. (Vcom2) is generated with an alternating voltage that is inverted every frame period.

The data formatter 105 receives 3D image data from the host system 104 and separates the left eye image data and the right eye image data for each line and transmits the same to the timing controller 101.

The timing controller 101 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable (DE), and a dot clock CLK from the host system 104. Timing control signals for controlling the operation timing of the driving circuit 102 and the gate driving circuit 103 are generated. The timing control signals include a gate timing control signal for controlling the operation time of the gate driving circuit 103 and a data timing control signal for controlling the operation timing of the data driving circuit 102 and the polarity of the data voltage. The timing controller 101 may receive a mode signal Mode from the host system 104 and determine a 2D / 3D mode. The timing controller 101 is generated at different logic levels in the 2D mode and the 3D mode to generate the switching control signal COM for controlling the common voltage switching circuit 106.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP controls the start operation timing of the gate driving circuit 103. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate driving circuit 103.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE). It includes. The source start pulse SSP controls the data sampling start timing of the data driving circuit 102. The source sampling clock SSC is a clock signal for shifting the source start pulse SSP and controls the sampling timing of data. The polarity control signal POL controls the polarity of the data voltage output from the data driving circuit 102. The source output enable signal SOE controls the data voltage output timing and the charge sharing timing of the data driving circuit 102. If the digital video data to be input to the data driving circuit 102 is transmitted in mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

The timing controller 101 may control the operation timing of the driving circuits 102, 103, and 106 at a frame frequency of input frame frequency x i (i is a positive integer) Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the phase-alternating line (PAL) scheme.

The host system 104 transmits 2D / 3D image data and timing signals Vsync, Hsync, DE, and CLK through a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. 101). The host system 104 supplies the timing controller 101 with a mode signal Mode indicating the 2D mode and the 3D mode. The host system 104 supplies 2D image data to the timing controller 101 in the 2D mode, while supplying 3D image data including the left eye image and the right eye image in the 3D mode to the data formatter 105.

The user may select a 2D mode and a 3D mode through the user input device 110. The user input device 110 may include a touch screen, an on screen display (OSD), a keyboard, a mouse, a remote controller, or the like attached or embedded on the liquid crystal display panel 100.

The host system 104 switches between 2D mode operation and 3D mode operation in response to user data input through the user input device 110. The host system 104 uses a 2D / 3D identification code encoded in data of an input image, for example, a 2D / 3D identification code that can be coded in an electronic program guide (EPG) or an electronic service guide (ESG) of a digital broadcasting standard. By detecting, 2D mode and 3D mode can be distinguished.

Each of the RGB subpixels of the liquid crystal display panel 100 may be implemented as an equivalent circuit diagram of FIG. 4 or 9.

4 is an equivalent circuit diagram of a subpixel according to the first embodiment of the present invention. 5 and 6 are plan views illustrating implementations of the subpixel illustrated in FIG. 4.

4 to 6, each of the RGB sub pixels includes one TFT, two liquid crystal cells Clc1 and Clc2, and one storage capacitor Cst.

The TFT is turned on in response to a gate pulse from the gate line G1 to supply data voltages supplied through the data line D1 to the first and second liquid crystal cells Clc1 and Clc2 and the storage capacitor Cst. Are commonly supplied to the pixel electrodes PIX.

The first liquid crystal cell Clc1 includes a pixel electrode PIX, a first upper common electrode COM1, and a liquid crystal layer formed between the electrodes PIX and COM1 to display 2D / 3D image data. It works negatively. The second liquid crystal cell Clc2 displays 2D image data in 2D mode, including a pixel electrode PIX, a second upper common electrode COM2, and a liquid crystal layer formed between the electrodes PIX and COM2. It acts as an active black stripe displaying black gradation in mode. As illustrated in FIGS. 5 and 6, the pixel electrode PIX is patterned into one transparent conductive pattern and shared in the first and second liquid crystal cells Clc1 and Clc2.

The storage capacitor Cst maintains the voltages of the first and second liquid crystal cells Clc1 and Clc2 until the next data is written into the first and second liquid crystal cells Clc1 and Clc2. The storage capacitor Cst is shared in the first and second liquid crystal cells Clc1 and Clc2 as shown in FIGS. 5 and 6.

An area D having no upper plate common electrode exists at a boundary between the first upper plate common electrode COM1 and the second upper plate common electrode COM2. As a result, an electric field is not applied to the liquid crystal molecules present in the boundary area D between the first upper plate common electrode COM1 and the second upper plate common electrode COM2, so that the disclination is performed in the boundary area D. May cause light leakage. In order to block such light leakage, the present invention is arranged on the TFT array substrate SUBS2 so as to face the boundary area D of the first upper common electrode COM1 and the second upper common electrode COM2 as shown in FIG. 5 or FIG. 6. Metal wires are formed on the substrate to block light incident from the backlight unit. The metal line formed in the boundary area D may be selected as the storage electrode STRG as illustrated in FIG. 5, or may be selected as the gate line GL as illustrated in FIG. 6.

FIG. 5 illustrates one sub-pixel present in the n-th line LINEn of the liquid crystal display panel 100.

Referring to FIG. 5, the storage electrode STRG is patterned in a 'H' shape across the center portion of the subpixel.

The boundary area D between the upper common electrodes COM1 and COM2 crosses the central portion of the subpixel including the first and second liquid crystal cells Clc1 and Clc2. Accordingly, the storage electrode STRG patterned in a 'H' shape overlaps the edges of both sides of the pixel electrode PIX and is formed along the boundary area D between the upper common electrodes COM1 and COM2. .

 The gate line GLn is formed above or below the pixel electrode PIX of the subpixel and does not overlap the pixel electrode PIX. The TFT is formed in the corner region of the subpixel, which is an intersection of the data line DLm and the gate line GLn, and is connected to the pixel electrode PIX.

FIG. 6 illustrates two subpixels existing in an n-th line LINEn and an n + 1 line of the liquid crystal display panel 100.

Referring to FIG. 6, gate lines GLn and GLn + 1 are formed in the boundary region D1 between the liquid crystal cells Clc1 and Clc2 across the center portion of each of the nth line and the n + 1th subpixel. Light leakage is blocked in the boundary area D1.

The storage electrode STRG is patterned in an 'H' shape and shared between the subpixels of the nth line and the subpixels of the n + 1th line. The storage electrode STRG patterned in an 'H' shape overlaps the edges of both sides of the n-th pixel electrode PIX, and the edges of both sides of the n + 1th pixel electrode PIX. Overlaps with seat A portion of the storage electrode STRG patterned in the shape of 'H' may have a boundary area D2 between the second upper common electrode COM2 of the n th line and the first upper common electrode COM1 of the n + 1 th line. Is formed.

 The gate line GLn partially overlaps with the pixel electrode PIX across the central portion of the pixel electrode PIX of the subpixel. The TFT is formed at a central portion of one side of the vertical side of the subpixel, which is an intersection of the data line DLm and the gate line GLn, and is connected to the pixel electrode PIX.

7 is a waveform diagram illustrating common voltages Vcom1 and Vcom2 applied to the first and second upper common electrodes COM1 and COM2 in the 2D mode. 8 is a waveform diagram illustrating common voltages Vcom1 and Vcom2 applied to the first and second upper common electrodes COM1 and COM2 in the 3D mode.

Referring to FIG. 7, the first common voltage Vcom1 applied to the first upper common electrode COM1 and the second common voltage Vcom2 applied to the second upper common electrode COM2 in the 2D mode are reference potentials. Generated by the equipotential DC voltage of (RL). The voltage of the reference potential RL may vary depending on panel characteristics, and may be, for example, a DC voltage of 6.5V. The storage reference voltage Vstrg applied to the storage electrode STRG is generated as a DC voltage of the reference potential RL.

In FIG. 7, "Vdata" is a data voltage applied to the data line, and pulses of "G1 to G4" represent a gate pulse synchronized with the data voltage Vdata.

The data voltage Vdata is applied to the pixel electrodes PIX shared between the first and second liquid crystal cells Clc1 and Clc2 through the TFT, and the reference potential is applied to the first and second upper common electrodes COM1 and COM2. Common voltages Vcom1 and Vcom2 of (RL) are applied.

In the 2D mode, the data voltage of the 2D image is supplied to the data line and the gate pulse is supplied to the gate line. In this case, the difference voltage V1 between the common voltages Vcom1 and Vcom2 between the data voltage and the reference potential is applied to the first and second liquid crystal cells Clc1 and Clc2 included in one subpixel. Accordingly, the data voltage of the 2D image is written in the first and second liquid crystal cells Clc1 and Clc2 in the 2D mode.

Referring to FIG. 8, the first common voltage Vcom1 applied to the first upper common electrode COM1 in the 3D mode is generated as a DC voltage of the reference potential RL. The storage reference voltage Vstrg is also generated as a DC voltage of the reference potential RL. The second common voltage Vcom2 applied to the second upper common electrode COM2 is between a positive polarity voltage + L higher than the reference potential RL and a negative polarity voltage −L lower than the reference potential RL. Generated by an alternating voltage swinging. The voltage of the reference potential RL may vary depending on panel characteristics, and may be, for example, a DC voltage of 6.5V. In this case, the + L potential can be set to 12V and the -L potential can be set to 0V.

The polarities of the data voltages Vdata supplied to the data lines of the liquid crystal display panel 100 are periodically reversed. The positive data voltage Vdata is higher than the reference potential RL, and the negative data voltage Vdata is lower than the reference potential RL. For example, the polarity of the data voltage Vdata may be reversed every one horizontal period and every one frame period. The second common voltage Vcom2 is applied as a voltage having a polarity opposite to that of the data voltage Vdata. Accordingly, the second common voltage Vcom2 may be inverted every one horizontal period and its polarity may be inverted every one frame period. The positive second common voltage Vcom2 is higher than the reference potential RL, and the negative second common voltage Vcom2 is lower than the reference potential RL. One horizontal period is a time at which data is written on one line of the liquid crystal display panel 100, which is equal to the time obtained by dividing one frame period by the number of lines of the liquid crystal display panel.

The data voltage Vdata is applied to the pixel electrodes PIX shared between the first and second liquid crystal cells Clc1 and Clc2 through the TFT, and the common voltage is applied to the first and second upper common electrodes COM1 and COM2. (Vcom1, Vcom2) is applied.

In the 3D mode, the data voltage of the 3D image is supplied to the data line and the gate pulse is supplied to the gate line. In this case, the difference voltage V1 between the data voltage of the left eye or right eye image and the first common voltage Vcom1 of the reference potential is applied to the first liquid crystal cell Clc1. Therefore, in the 2D mode, data voltages of left and right eye images are written in the first and second liquid crystal cells Clc1 and Clc2.

The second liquid crystal cell Clc2 is applied with a voltage V2 having a greater potential difference than V1 due to the data voltages having the opposite polarities and the second common voltage. The voltage V2 is set to the black gradation voltage. As described above, in the normally white mode, the light transmittance of the liquid crystal cell is lower as the potential difference between the pixel electrode Vcom and the upper common electrodes COM1 and COM2 increases. Therefore, since the second liquid crystal cell Clc2 charges a voltage of black gray or similar gray, the second liquid crystal cell Clc2 functions as a black stripe.

9 is an equivalent circuit diagram of a subpixel according to the second embodiment of the present invention. FIG. 10 is a plan view illustrating an implementation of the subpixel illustrated in FIG. 9. The subpixel of FIG. 9 may be driven in a 2D / 3D mode as shown in FIGS. 7 and 8 to display a 2D or 3D image.

9 and 10, each of the RGB subpixels may include first and second TFTs TFT1 and TFT2, first and second liquid crystal cells Clc1 and Clc2, and first and second storage capacitors. Cst1, Cst2).

The first TFT TFT1 is turned on in response to gate pulses from the first gate lines G1 and GLn1 to supply a data voltage supplied through the data line D1 to the first liquid crystal cell Clc1 and the first storage device. The first pixel electrode PIX1 is shared with the capacitor Cst1. The gate electrode of the first TFT TFT1 is connected to the first gate lines G1 and GLn1. The drain electrode of the first TFT TFT1 is connected to the data line D1, and the source electrode thereof is connected to the first pixel electrode PIX1.

The second TFT TFT2 is turned on in response to gate pulses from the second gate lines G2 and GLn2 to supply a data voltage supplied through the data line D1 to the second liquid crystal cell Clc2 and the second storage device. The second pixel electrode PIX2 is shared with the capacitor Cst2. The second pixel electrode PIX2 is a transparent conductive pattern separated from the first pixel electrode PIX1. The gate electrode of the second TFT TFT2 is connected to the second gate lines G2 and GLn2. The drain electrode of the second TFT TFT2 is connected to the data line D1, and the source electrode thereof is connected to the second pixel electrode PIX2.

The first liquid crystal cell Clc1 displays 2D / 3D image data including a first pixel electrode PIX, a first upper common electrode COM1, and a liquid crystal layer formed between the electrodes PIX1 and COM1. It acts as the main pixel part. The second liquid crystal cell Clc2 displays 2D image data in 2D mode including a second pixel electrode PIX2, a second upper common electrode COM2, and a liquid crystal layer formed between the electrodes PIX2 and COM2. It operates as an active black stripe that displays black gradation in 3D mode.

The first storage capacitor Cst1 maintains the voltage of the first liquid crystal cell Clc1 until the next data is written in the first liquid crystal cell Clc1. The storage electrode STRG of the first storage capacitor Cst1 overlaps both vertical sides of the first pixel electrode PIX1 and receives a DC voltage of the reference potential RL. The second storage capacitor Cst2 maintains the voltage of the second liquid crystal cell Clc2 until the next data is written in the second liquid crystal cell Clc2. The storage electrode STRG of the second storage capacitor Cst2 overlaps both vertical sides of the second pixel electrode PIX2 and receives a DC voltage of the reference potential RL.

Metal wires are formed at the boundary between the first upper common electrode COM1 and the second upper common electrode COM2 to block light leakage. The metal line formed in the boundary area D may be implemented with FIG. 10, the gate lines GLn1 and GLn2, and the storage electrode STRG.

The first and second upper common electrodes COM1 and COM2 may be embodied in a transparent conductive pattern patterned as shown in FIG. 11. The first and second upper common electrodes COM1 and COM2 are patterned in a staggered and electrically insulated form. In FIG. 11, "CONT1" and "CONT2" are contact portions to which a common voltage is applied to the upper common electrodes COM1 and COM2. The first and second common voltages Vcom1 and Vcom2 are silver dots formed on the edges of the TFT array substrate SUBS2 and the color filter array substrate SUBS1 or contact portions CONT1 and CONT2 connected to the conductive balls. Is applied to the upper plate common electrodes COM1 and COM2. However, in each of the upper common electrodes COM1 and COM2, the resistance R of the upper common electrodes COM1 and COM2 increases as the distance from the contact portions CONT1 and CONT2 increases, thereby increasing the resistance of the common voltages Vcom1 and Vcom2. The voltage drop can be large. In this case, the image quality of the liquid crystal display panel becomes nonuniform depending on the screen position. Since the upper common electrodes COM1 and COM2 of FIG. 11 are patterned in different shapes, the upper common electrodes COM1 and COM2 should be patterned by a photolithography process using a separate photo mask.

According to the present invention, in order to reduce the number of photo masks for patterning the top common electrodes COM1 and COM2 and to reduce the voltage drop due to the resistance of the transparent conductive pattern, the top common electrodes COM1 and COM2 are formed as shown in FIG. 12. Pattern.

Referring to FIG. 12, the first and second upper common electrodes COM1 and COM2 are patterned in the same shape and disposed to be staggered with each other.

The first and second upper common electrodes COM1 and COM2 are patterned in the form of square bands connecting stripe patterns in a horizontal direction. Since the first and second upper common electrodes COM1 and COM2 have the same shape, they may be patterned by a photolithography process using the same photo equipment as one photo mask.

The common voltages Vcom1 and Vcom2 are applied to each of the first and second upper common electrodes COM1 and COM2 through a plurality of contact portions CONT formed at at least two sides including a horizontal side and a vertical side of the rectangular band. do.

The top plate manufacturing method of the present invention performs a photolithography process to form the second top plate common electrode COM2 on the top plate, and then shifts the photomask by a predetermined distance SFT in the diagonal direction, and then performs the photolithography process again. The first upper common electrode COM1 is patterned. The top plate manufacturing method of the present invention includes the top plate common electrodes COM1 and COM2 at portions where the top plate common electrodes COM1 and COM2 overlap to insulate the first and second top plate common electrodes COM1 and COM2. The insulating layers INS1 and INS2 are formed in between. The insulating layers INS1 and INS2 may be formed by simultaneously patterning the same material as the column spacer CS with the column spacer CS as shown in FIGS. 13A through 13D.

13A to 13D are cross-sectional views illustrating a manufacturing process of upper plate common electrodes COM1 and COM2 by cutting along the line “I ′ ′” in FIG. 12.

The top plate manufacturing method of the present invention performs a photolithography process after depositing ITO on the color filter array substrate SUBS1 on which the black matrix BM and the color filter CF are formed as shown in FIG. 13A. As a result, the second upper common electrode COM2 patterned in the form of the first photo mask is formed on the color filter array substrate SUBS1. The color filter CF is omitted in the drawing.

In the top plate manufacturing method of the present invention, a photoresist (PR) is applied on the color filter array substrate SUBS1 to a predetermined thickness so as to cover the second top common electrode COM2 as shown in FIG. 13B. Subsequently, the top plate manufacturing method of the present invention aligns the second photo mask implemented with the half tone photo mask on the color filter array substrate SUBS1. The second photo mask includes a transmissive portion T having a maximum light transmittance, a blocking portion M having a minimum light transmittance, and a halftone portion HT having a moderate light transmittance. The light transmittance of the halftone part HT is lower than that of the transmission part T and higher than that of the blocking part M. FIG. In FIG. 12, the halftone portion HT passes light having a lower amount of light than the transmission portion T toward the overlapping portion, facing the overlapping portion where the insulating layers INS1 and INS2 are to be formed.

In the top plate manufacturing method of the present invention, after irradiating ultraviolet (UV) to the photoresist (PR) through the second photo mask, the photoresist (PR) is developed with a developer. As a result of developing the photoresist, as shown in FIG. 13C, all of the photoresist PR of the portion of the second photo mask that faces the transmissive portion T is removed, and the photoresist PR of the photoresist PR facing the blocking portion M has a thickness thereof. Is hardly reduced and remains. The photoresist remaining in the portion facing the blocking portion M of the second photo mask remains as the column spacer CS. In the second photo mask, the thickness of the photoresist PR facing the halftone part HT is lowered, so that patterns of the insulating layers INS1 and INS2 remain on the second upper common electrode COM2. The patterns of the column spacer CS and the insulating layers INS1 and INS2 are cured through a baking process. Therefore, the column spacer CS and the insulating layers INS1 and INS2 are simultaneously patterned.

In the top plate manufacturing method of the present invention, after depositing ITO on the color filter array substrate SUBS1 on which the second top plate common electrode COM2 and the insulating layers INS1 and INS2 are formed, the first photo mask is diagonally formed as shown in FIG. 12. The photolithography step is performed by shifting the direction by a predetermined distance SFT. As a result, the first upper common electrode COM1 patterned in the form of a first photo mask is formed on the color filter array substrate SUBS1.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

100 liquid crystal display panel 300 pattern retarder
310: polarizing glasses COM1, COM2: upper common electrode
PIX: Pixel electrode STRG: Storage electrode

Claims (12)

A liquid crystal display panel having a liquid crystal layer formed between the first and second substrates;
A pattern retarder bonded on the liquid crystal display panel and configured to pass first polarized light through a first pattern and pass second polarized light through a second pattern; And
And a polarizing glasses including a left eye filter through which only the first polarization passes and a right eye filter through which only the second polarization passes.
The first substrate includes first and second top common electrodes,
Each of the subpixels of the liquid crystal display panel includes a main pixel portion defined by the first upper common electrode, and an active black stripe defined by the second upper common electrode,
A first common voltage of a reference potential is applied to the first upper common electrode in the 2D mode and the 3D mode,
The voltage of the reference potential is applied to the second upper common electrode in the 2D mode, and the voltage swinging between the positive voltage higher than the reference potential and the negative voltage lower than the reference potential is applied in the 3D mode. Stereoscopic display device characterized in that.
The method of claim 1,
The second substrate,
A data line to which a video data voltage is supplied;
A gate line crossing the data line and sequentially supplied with a gate pulse;
A TFT formed at an intersection of the data line and the gate line;
A pixel electrode connected to the TFT; And
A storage electrode overlapping an edge of the pixel electrodes, to which a voltage of the reference potential is supplied;
And at least one of the gate line and the storage electrode opposes a boundary between the first upper common electrode and the second upper common electrode.
The method of claim 2,
And the storage electrode has an H shape.
The method of claim 1,
The first substrate further comprises a column spacer for maintaining a cell gap between the first and second substrates.
The method of claim 4, wherein
The first and second upper plate common electrodes have the same shape and are alternately disposed with each other.
The method of claim 5, wherein
And an insulating layer formed between the first and second upper common electrodes in an overlapping portion of the first and second upper common electrodes,
And the insulating layer is lower than the height of the column spacer and comprises the same material as the material of the column spacer.
The method of claim 2,
One TFT is formed for each sub-pixel,
And the pixel electrode is shared between the main pixel portion and the active black stripe in each of the sub-pixels.
The method of claim 2,
The pixel electrode includes a first pixel electrode formed on the main pixel portion, and a second pixel electrode formed on the active black stripe.
The TFT includes a first TFT supplying a data voltage from the data line to the first pixel electrode in response to an n (n is positive integer) gate line, and the data line in response to an n + 1 th gate line. And a second TFT for supplying a data voltage from the second pixel electrode.
A liquid crystal display panel having a liquid crystal layer formed between the first and second substrates, a pattern retarder bonded on the liquid crystal display panel and configured to pass first polarized light through a first pattern and pass second polarized light through a second pattern; And a polarizing glasses including a left eye filter through which only the first polarization passes and a right eye filter through which only the second polarization passes.
Forming a first top common electrode on the first substrate using a first photolithography process using a first photo mask;
Forming an insulating layer on a portion of the first upper common electrode using a first photolithography process using a second photo mask; And
Forming a second upper common electrode on the first substrate using a third photolithography process using the first photo mask,
And the second upper common electrode overlaps the first upper common electrode with the insulating layer interposed therebetween.
The method of claim 9,
And a column spacer for maintaining a cell gap between the first and second substrates simultaneously with the insulating layer, on the first substrate.
11. The method of claim 10,
And the insulating layer is lower than the height of the column spacer and includes the same material as the material of the column spacer.
The method of claim 9,
The first and second upper plate common electrodes have the same shape and are alternately disposed with each other.

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