KR20120098031A - Memory, memory system including the same and operating method of memory and memory system - Google Patents

Abstract

PURPOSE: A memory, a memory system including the same, and a method for operating the memory and the memory system are provided to improve the accuracy of write data by controlling the number of fail bits which are allowed according to a data type. CONSTITUTION: Data is inputted(S101). Information about a fail allowable value is inputted(S102). Data is stored to allow a fail below the fail allowable value(S103). The fail allowable value is determined according to a data type. [Reference numerals] (AA) Start; (BB) Finish; (S101) Inputting data; (S102) Receiving information about a fail allowable value; (S103) Storing data to allow fail below a fail allowable value

Description

Memory, a memory system including the same and a method of operating the memory and the memory system {MEMORY, MEMORY SYSTEM INCLUDING THE SAME AND OPERATING METHOD OF MEMORY AND MEMORY SYSTEM}

The present invention relates to a method of operating a memory.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function that requires rewriting data at regular intervals.

The nonvolatile memory cell is a device capable of electrical program / erase operation, and performs a program and erase operation by changing a threshold voltage of the cell while electrons are moved by a strong electric field applied to a thin oxide film.

During the program operation of the nonvolatile memory device, a verification operation for confirming whether the program target cells are programmed above the verify voltage is performed. In addition, cells that are not completed by the program after completion of the verification program are classified as pass cells. Cells in which the program is not completed are classified into fail cells to perform additional program operations.

In this case, it is necessary to check how many fail cells (hereinafter, fail bits) are included in a single page according to the operation of the nonvolatile memory device. In particular, as the error correcting code (ECC) processing algorithm is applied to the nonvolatile memory device, even if the entire cell is not in the pass state, it is reported that a fail bit occurs within the allowable bit range by the ECC processing algorithm. You need to complete the program.

This method reduces the time required to complete the program of nonvolatile memory. However, the allowable number of fail bits and the time required to complete the program can be regarded as a trade-off relationship. The larger the number of allowable fail bits, the longer it takes to complete the program, but the less accurate the program. The smaller the number of allowed fail bits, the shorter the time required to complete the program, but the higher the program accuracy. Because.

The accuracy of the program depends on the type of data. In the conventional case, the number of fail bits allowed is fixed regardless of the type of data, and thus the advantage of the data cannot be taken in any direction.

The present invention provides a method of operating a memory that can increase the accuracy of recorded data or reduce the time required for a program by adjusting the number of fail bits allowed according to the type of data.

A method of operating a memory according to the present invention includes: receiving data; Receiving information regarding a fail permission value; And storing the data such that a fail of the fail allowable value or less occurs.

In addition, a method of operating a memory system according to the present invention includes a memory controller and a method of operating a memory system including a memory controlled by the memory controller, the method comprising: transferring data from the memory controller to the memory; Generating information regarding a fail permission value according to the type of the data in the memory controller; Transferring information about the fail permission value from the memory controller to the memory; And storing the data such that the memory has a fail value less than or equal to the fail allowance value.

In addition, the memory according to the present invention, the cell array for storing the input data packet; A fail check unit for checking a fail value of the data packet; A fail value comparison unit for comparing a fail value of the data packet with a fail permission value; And a controller configured to store the data packet in the cell array such that a fail value of the data packet becomes equal to or less than the fail allowable value according to a comparison result of the fail value comparator.

In addition, the memory system according to the present invention, a memory controller; And a memory controlled by the memory controller, wherein the memory controller transfers information about a data packet and a fail permission value generated according to a type of the data packet to the memory, and the memory permits the fail permission. The data packet is stored to cause a failure of less than the value.

The memory operating method according to the present invention reduces the time required for the program by increasing the number of allowable fail bits when programming data requiring relatively low accuracy by adjusting the number of allowable fail bits according to the type of data. When programming data that requires relatively high accuracy, the data can be programmed accurately by reducing the number of fail bits allowed so that memory operates effectively according to the data type.

1 is a flowchart illustrating a memory operating method according to the present invention;
2 is a flowchart illustrating a method of operating a memory system according to the present invention;
3 is a block diagram of a memory system according to the present invention;

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

1 is a flowchart illustrating a memory operating method according to the present invention.

As shown in FIG. 1, the method of operating a memory includes: receiving data (101); receiving information on a fail permission value (S102); and storing data such that a fail below a fail allowance value occurs (S103). ).

Hereinafter, a method of operating a memory will be described with reference to FIG. 1.

The method of operating a memory according to the present invention may be applied to a memory including a plurality of memory cells and having a different speed at which the plurality of memory cells respectively store (write) data. The most representative example of a memory including such a memory cell is a nonvolatile memory. Nonvolatile memories store data in a manner that changes the threshold voltage of a memory cell. In this case, a program pulse is applied to the memory cell to change the threshold voltage of the memory cell. However, the speed at which the threshold voltage changes is different for each memory cell so that a program pulse is applied until all memory cells are programmed. Hereinafter, an example in which the memory is a nonvolatile memory will be described. Such a memory operation method is not limited to the nonvolatile memory.

When the storage (write) operation is started, the memory receives data from the outside (S101). In the case of non-volatile memory, the unit of reading / writing data is pages. Therefore, the data received at one time in the data input step S101 corresponds to the data to be stored in one page.

The memory receives information regarding a failing allowance value together with the data (S102). The fail tolerance is the maximum number of failed bits (the number of program cells failed in a page, the number of fail bits below) to be determined as a program pass on a single page. Say. In other words, if the number of fail bits that are not properly programmed is greater than the allowable value after applying the program pulse to the memory cells included in the page, the program is failed and the program pulse is applied again. If the number is smaller than the fail allowable value, the program passes and the data storage operation is terminated.

Meanwhile, in the present invention, the allowable fail value is determined according to the type of data. Types of data are classified according to the accuracy required for the data. For example, consider image data, picture data, audio data, and text data. Image data and photo data are often difficult for a user to recognize even when a part of data is lost. Therefore, image data or photo data can be regarded as relatively low accuracy data required for the data. However, in the case of text data, even if only a small part of data is lost, wrong text information can be delivered to the user. Therefore, the character data may be regarded as relatively high accuracy data required for the data. In particular, if the character data contains information such as a specific password, all the bits must be correct, which means that the data needs a very high accuracy.

In this manner, the image data and the photo data correspond to different types of data than character data. Also, when the image data and the photo data are input, the fail allowance value is larger than the fail allowance value when the character data is input. In other words, the smaller the accuracy required for the data according to the type of data, the larger the fail tolerance value, and the larger the accuracy required for the data, the smaller the fail tolerance value. The type of data may not be classified into two types as in the above-described example, but may be variously classified according to a user's setting. In addition, as the classification of data types varies, it is natural that the fail tolerance can be further refined accordingly.

The memory receives this fail tolerance with data. This fail allowance value input step S102 may be performed simultaneously with the data input step S101 as well as before or after the data input step S101. As shown in the flowchart of FIG. 1, the fail permission value information input step S102 is not necessarily performed after the data input step S101. 1 corresponds to one embodiment.

The memory may store information about the fail allowance value determined according to the type of data thus input. If the same type of data is continuously input by storing the fail allowance value, the fail allowance value may be input only once, and the operation of comparing the number of incorrectly stored bits, that is, the number of fail bits and the fail allowance value, is stable. Can be done. The stored fail allowance may be updated with a newly entered fail allowance when data types are changed.

After receiving the information regarding the data and the fail allowable value, the data is stored so that a fail value of the data is equal to or less than the fail allowable value (S103). The data storage step S103 refers to a step of performing a program operation of applying a program pulse in the case of the nonvolatile memory. The fail value of data refers to the number of memory cells that are not properly programmed when the program pulses are applied to the plurality of memory cells included in the page to store the data and then verified. Number). If the fail value of the data is larger than the allowable fail value, a program pulse is applied to the plurality of memory cells again. This operation is repeated until the fail value of the data is smaller than the allowable fail value. That is, in the case of nonvolatile memory, a program pulse is repeatedly applied until the data fail value is smaller than the allowable fail value. If the data fail value is smaller than the allowable fail value, the data storage step (S103) ends and the data storage operation is terminated. It ends.

The memory operating method according to the present invention differs from the conventional one in that the allowable fail value is changed according to the type of data to be stored. Regardless of the type of data, if you increase the fail allowance in a batch, the data can be stored correctly, but the time required to store the data is long. Cannot be stored correctly. Therefore, by varying the fail tolerance according to the type of data, the data is operated with a focus on storing accurate data rather than a data storage speed for data requiring high accuracy, and the data storage speed for data requiring low accuracy. Flexible storage operation is possible by operating. In addition, this method has the advantage that the performance of the memory can be improved without improving the physical characteristics of the memory.

2 is a flowchart illustrating a method of operating a memory system according to the present invention.

As shown in FIG. 2, the method of operating a memory system includes: in a method of operating a memory system including a memory controller and a memory controlled by the memory controller, transferring data from the memory controller to the memory (S201); Generating information about the fail permission value according to the type of data in the memory controller (S202), transferring information about the fail permission value from the memory controller to the memory (S203), and failing the fail value or less to the memory; In step S204, the data is stored.

Hereinafter, a method of operating a memory system will be described with reference to FIG. 2.

The operating method of the memory system according to the present invention may be applied when the memory includes a plurality of memory cells and the speed at which the plurality of memory cells stores data is different. The following description is the same as described above in the description of FIG. 1, and the following description will be given with an example of a nonvolatile memory system.

In the memory system, when a storage operation (or a write operation) is started, the memory controller transfers data received from the outside of the chip to the memory (S201). In the case of non-volatile memory, the unit of reading / writing data is pages. Therefore, the data transferred to the memory at one time by the memory controller in the data transfer step S201 corresponds to the data to be stored in one page.

The memory controller generates information about a fail permission value according to the type of data (S202). The description of the fail tolerance according to the type of data and the type of data is the same as described above in the description of FIG. 1. The memory controller may generate the fail tolerance value corresponding to the type of data in advance in step S202, and output the fail tolerance value corresponding to the type of data, or may directly process the information regarding the type of data to generate the fail tolerance value. However, fail generation information generation step (S202) is not necessarily to be performed in the memory controller, it may be generated directly by receiving information on the type of data in the memory, or may be generated outside the integrated circuit.

The memory controller transmits information regarding the fail permission value to the memory together with the data (S203). The fail allowance value information transferring step S203 corresponds to the fail allowance value information input step S102 of FIG. 1. The following description is the same as the description of FIG. 1 and thus will be omitted. In addition, the data transfer step (S201), fail allowance value information generation step (S202), fail allowance value information transfer step (S203) of the fail tolerance value information generation step (S202) is fail tolerance value information transfer step (S203) Of course, it should be ahead, but the rest does not matter. For example, it is possible to operate in the order of fail allowance value information generation step S202, fail allowance value information transfer step S203, and data forwarding step S201, and fail allowance value information generation step S202 and fail allowance value. The information delivery step S203 and the data delivery step S201 may be performed at the same time. 2 corresponds to one embodiment.

The memory, which has received the information about the data and the fail permission value from the memory controller, stores the data so that the fail value of the data is equal to or lower than the fail permission value (S204). Data fail values and data storage in the nonvolatile memory system are the same as described above with reference to FIG. 1. When the fail value of the data is smaller than the allowable fail value, the data storing step S204 is finished and the data storing operation is terminated.

3 is a configuration diagram of a memory system according to the present invention.

As shown in FIG. 3, the memory system includes a memory controller 310, a cell array 321 storing an input data packet DATA, and a fail check unit 322 checking a fail value FAIL of the data packet. According to the result of the comparison between the fail value comparison unit 323 and the fail value comparison unit 323 comparing the fail value FAIL of the data packet with the fail allowable value REF, the fail value FAIL of the data packet is allowed to fail. The controller 324 stores the data packet DATA in the cell array 321 to be equal to or less than the value REF, and includes a memory 320 controlled by the memory controller 310. The data packet DATA is a multi-bit digital signal because it contains a plurality of data.

Hereinafter, an operation of the memory system and the memory will be described with reference to FIG. 3. As described above with reference to FIGS. 1 and 2, the memory system and the memory according to the present invention may be applied when the speed of storing (writing) data in a plurality of memory cells is different. An example applied to a memory (particularly a flash memory) will be described.

The memory controller 310 controls the operation of the memory 320 and transmits a command CMD, a data packet DATA, and a fail permission value REF to the memory. The command CMD refers to a read command, a write command, and the like. The present invention relates to an operation of storing data, and thus, the command CMD will be described with reference to a case where the command CMD is a write command. . The data packet DATA indicates a unit of data that is read / written in response to one command CMD. In the case of a nonvolatile memory, the data packet DATA indicates data read from one page or written to one page. The fail allowance value REF is the same signal as described above in the description of FIGS. 1 and 2 and is a digital signal of at least one bit or more. The fail allowance REF is determined according to the type of data, and the description of the fail allowance REF and the type of data is the same as described above with reference to FIGS. 1 and 2.

The memory controller 310 transmits the data packet DATA and the fail permission value REF to the memory 320 together with the command CMD (here, a write command). In this case, the data packet DATA and the fail permission value REF may be simultaneously delivered, or one of them may be delivered first and the other may be delivered later.

The memory 320 receives a command CMD, a data packet DATA, and a fail permission value REF received from the memory controller 310 so that the data packet may fail under the fail allowance value REF. 321). Looking at the operation of the memory 320 in more detail as follows. Hereinafter, the fail value FAIL of the data packet refers to the number of failing memory cells among the memory cells storing the data packet DATA, that is, the number of bits of data not properly stored in the data packet DATA.

The controller 324 applies a program pulse to a plurality of memory cells included in the cell array 321 in order to store the data packet DATA in the cell array 321 in response to the command CMD. In this case, the memory cell in which the data packet DATA is to be stored is determined by an address (not shown in FIG. 3).

In the verify operation after the program pulse is applied, the fail check unit 322 checks a fail value FAIL of the data packet. In other words, after the program pulse is applied, it counts the number of memory cells that are not properly programmed. When the check of the fail value FAIL of the data packet is completed, the check result is sent to the fail value comparison unit 323. For reference, the fail check unit 322 may include a counter to check a fail value (FAIL) of the data packet.

The fail value comparison unit 323 compares the fail value FAIL and the fail allowance value REF of the data packet and applies the program pulse to the cell array 321 by the control unit 324 according to the comparison result. Determine. If the fail value FAIL of the data packet is greater than the fail allowable value REF, the controller 324 further applies a program pulse to the cell array 321, and the fail value FAIL of the data packet corresponds to the fail allowance value (REF). If less than REF, the controller 324 terminates the storing operation of the data packet DATA without applying a program pulse to the cell array 321. For reference, when the fail value FAIL and the fail allowance value REF of the data packet are the same, it may be determined by a user whether to further apply a program pulse.

As described above with reference to FIGS. 1 and 2, the memory system and the memory according to the present invention increase the accuracy of storing the data packet DATA according to the type of the data packet DATA or to store the data packet DATA. Since it is possible to determine whether to reduce the time required, there is an advantage that a more flexible storage operation of the data packet DATA can be performed. This is possible by varying the fail allowance REF according to the type of the data packet DATA, unlike the conventional fail allowance REF. Therefore, an advantage may be obtained in one of the accuracy of data packet DATA storage and the time required for storing the data packet DATA, and thus an optimal storage operation may be performed according to the type of the data packet DATA.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will recognize that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (20)

Receiving data;
Receiving information regarding a fail permission value; And
Storing the data such that a fail below the fail tolerance value occurs;
Operating method of a memory comprising a.
The method of claim 1,
The fail tolerance value is determined according to the type of data.
The method of claim 2,
The type of data is
A method of operating a memory classified according to the accuracy required for the data.
The method of claim 3, wherein
Depending on the type of data above,
And the fail allowance value increases as the accuracy required for the data decreases, and the fail allowance value decreases as the accuracy required for the data increases.
The method of claim 2,
And storing information about the received fail tolerance value after receiving the information on the fail permission value.
The method of claim 2,
Storing the data,
And comparing the fail allowable value with a fail value of the data, and store the data such that a fail value of the data is equal to or less than the fail allowable value.
In the operating method of a memory system including a memory controller and a memory controlled by the memory controller,
Transferring data from the memory controller to the memory;
Generating information regarding a fail permission value according to the type of the data in the memory controller;
Transferring information about the fail permission value from the memory controller to the memory; And
Storing the data such that a fail of the fail tolerance value or less occurs in the memory;
Operating method of a memory system comprising a.
8. The method of claim 7,
The fail tolerance value is determined according to the type of data.
The method of claim 8,
The type of data is
A method of operating a memory system classified according to the accuracy required for the data.
The method of claim 9,
Depending on the type of data above,
The fail tolerance increases as the accuracy required for the data decreases, and the fail tolerance decreases as the accuracy required for the data increases.
The method of claim 8,
Storing the data,
Compare the fail allowance with a fail value of the data, and store the data such that a fail value of the data is equal to or less than the fail allowable value.
A cell array for storing input data packets;
A fail check unit for checking a fail value of the data packet;
A fail value comparison unit for comparing a fail value of the data packet with a fail permission value; And
A controller configured to store the data packet in the cell array such that a fail value of the data packet is equal to or less than the fail allowable value according to a comparison result of the fail value comparator.
Memory containing.
13. The method of claim 12,
The fail tolerance of the data packet is determined according to the type of the data packet.
The method of claim 13,
The type of data packet is
Memory classified according to the accuracy required for the data packet.
The method of claim 14,
According to the type of data packet,
The smaller the accuracy required for the data packet, the greater the fail tolerance of the data packet, and the greater the accuracy required for the data packet, the smaller the fail tolerance of the data packet.
The method of claim 13,
And a fail tolerance storing unit configured to store a fail tolerance of the data packet. Memory controller; And
A memory system including a memory controlled by the memory controller,
The memory controller transfers information about a data packet and a fail allowance value generated according to the type of the data packet to the memory, and the memory stores the data packet so that a fail equal to or less than the fail allowance value occurs.
18. The method of claim 17,
The fail tolerance is determined according to the type of data packet.
19. The method of claim 18,
The type of data packet is
A memory system classified according to the accuracy required for the data packet.
20. The method of claim 19,
According to the type of data packet,
The fail tolerance increases as the accuracy required for the data packet decreases, and the fail tolerance becomes smaller as the accuracy required for the data packet increases.

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