KR20120094396A - Semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent the deterioration of an MTJ(Magnetic Tunnel Junction) device by preventing the deterioration of a multilayer pattern. CONSTITUTION: A multilayer pattern(30a) is formed on a substrate(10). A sacrificial film pattern(20a) with a hole exposing a preset area of the multilayer pattern is formed. A metal film pattern is formed in the hole. The sacrificial film pattern is removed. A magneto-resistive device is formed by patterning a multilayer using the metal film pattern as an etch mask.

Description

Manufacturing Method of Semiconductor Device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a pad region of a semiconductor device.

DRAM, a widely used memory device, has the advantages of high speed operation and high integration, whereas volatile memory not only loses data when power is turned off, but also continuously refreshes data during operation (REFRESH). There is a big disadvantage in terms of power dissipation since it must be rewritten via. In addition, flash memory, which is characterized by non-volatile and high density, has a disadvantage of slow operation. On the other hand, a magnetoresistive memory (MRAM) for storing information by using magnetoresistance difference has an advantage that it can be highly integrated while having characteristics of nonvolatile and high speed operation.

On the other hand, MRAM refers to a nonvolatile memory device using a change in magnetoresistance according to the magnetization direction between the ferromagnetic material. Cell structures that are most commonly used in MRAMs include GMR devices using Giant Magneto-Resistance (GMR) effects and magnetic tunnel junctions using Tunnel Magneto-Resistance (TMR) effects. (Magnetic Tunnel Junction (MTJ)) devices, etc. In addition, spin-valve devices including a ferromagnetic layer reinforced with a permanent magnet and a free layer used as a soft magnetic layer to overcome the disadvantages of the GMR device. In particular, the MTJ device has a high speed and low power, and is used as a substitute for a capacitor of a DRAM and thus may be applied to low power and high speed graphics and mobile devices.

In general, the magnetoresistive element has a small resistance when the two magnetic layers have the same spin direction (that is, the direction of the magnetic momentum), and a larger resistance when the spin directions are opposite. As described above, the bit data can be written in the magnetoresistive memory device by using the fact that the resistance of the cell varies depending on the magnetization state of the magnetic layer. In the case of the MTJ-structured magnetoresistive memory as an example, in a MTJ memory cell having a ferromagnetic layer / insulation layer / ferromagnetic layer structure, electrons passing through the first ferromagnetic layer pass through an insulating layer used as a tunneling barrier. The tunneling probability depends on the magnetization direction of the layer. That is, the tunneling current is maximum when the magnetization directions of the two ferromagnetic layers are parallel, and minimum when they are antiparallel. For example, when the resistance is large, the data '1' (or '0') and the resistance are When small, data '0' (or '1') can be regarded as recorded. Here, one of the two ferromagnetic layers is referred to as a stator magnetization layer in which the magnetization direction is fixed, and the other is called a free magnetization layer in which the magnetization direction is reversed by an external magnetic field or current.

On the other hand, many laboratories and schools have studied these magnetic memories for a long time, but the reason that has not been commercialized so far is that the vertical and redeposition-free magnetic tunnel junction structure is maintained while maintaining the aspect ratio of 1: 2 or 1: 3. The development of the etching process has not been accomplished. That is, until recently, it has been a problem that it is very difficult to pattern a multilayer film to manufacture a magnetic tunnel junction structure.

The present invention provides a method of manufacturing a semiconductor device having a magnetic tunnel junction element with improved process reliability.

The present invention comprises the steps of forming a multi-layered pattern for forming a magnetoresistive element on the substrate; Forming a sacrificial layer pattern having holes for exposing predetermined areas of the multilayer pattern to pattern the multilayer pattern; Forming a metal film pattern in the hole; Removing the sacrificial layer pattern; And forming a magnetoresistive element by patterning a multilayer for constituting the magnetoresistive element using the metal film pattern as an etch mask.

The method for manufacturing a semiconductor device according to the present invention does not apply dry etching when forming a pattern of a metal hard mask used as a pattern for a device for MTJ. Therefore, it is possible to prevent the deterioration of the characteristics of the MTJ element by preventing damage to each layer, particularly the upper layer, constituting the MTJ element by dry etching of the metal hard mask pattern.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a semiconductor device manufactured according to the method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
2 and 3 are cross-sectional views showing the magnetic tunnel resistance element shown in FIG.
4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

The present invention forms a contact hole having an aspect ratio of 1: 2 or 1: 3, deposits TaN with a barrier metal, and fills the contact hole using a copper damascene process. A method of forming a hard mask pattern of a magnetic tunnel junction structure by removing a silicon oxide by wet etching after planarization by chemical mechanical polishing (CMP) after deposition of a material having a high selectivity with copper by a sputtering method.

The present invention is applicable to magnetic RAM, spin-transfer torque RAM (STT) RAM and vertical magnetic RAM (perpendicular magnetic RAM), which are magnetic memories using magnetization reversal of a magnetic tunnel junction structure.

The present invention provides a pattern of a metal hard mask having a high aspect ratio of 1: 2 or 1: 3 to form a pattern having a 1: 2 or 1: 3 aspect ratio of a magnetic tunnel junction structure (hereinafter referred to as MTJ) for application to a magnetic memory. The process can proceed without etching.

When the pattern of the metal hard mask is formed by applying the present invention, a metal hard mask of a material that is difficult to form a pattern through dry etching, such as MTJ, may be formed without performing a dry etching process. Therefore, there is no deterioration in characteristics of the MTJ element after manufacture, and the process of forming the top electrode contact is eliminated by using copper having low resistance, so that the electrode of the MTJ element can be formed with a small number of steps. By applying the present invention to a next-generation memory which is difficult to form a pattern of a core structure such as a magnetic memory, a memory having high efficiency can be manufactured without deterioration.

1 is a cross-sectional view of a semiconductor device manufactured according to the method of manufacturing a semiconductor device according to the embodiment of the present invention.

Referring to FIG. 1, a semiconductor device may include gate patterns 12, 13, 14, and 15, interlayer insulating layers 11, 16, and 20, bit lines 17, and bit line contacts 18 on a substrate 10. The lower electrode 19, the magnetic tunnel resistance element 30, the upper electrode 40, and the wiring 50 are formed. The gate patterns 12, 13, 14, and 15 may include a lower insulating layer 12, a conductive layer 13, a hard mask layer 15, and sidewall spacers 13.

The magnetic tunnel junction element 30 has a multilayer thin film structure in which alloys containing a metal material having a difficult pattern formation by applying a dry etching process such as Co, Fe, Pt, and Ta are applied. Accordingly, in the manufacturing of the magnetic tunnel junction device, a relatively hard mask such as silicon oxide and silicon nitride is used in addition to the photoresist made of a polymer material, but there is a problem that the etching selectivity with the magnetic tunnel junction device is not high.

To overcome this problem, a metal such as TiN or Ta may be used as a hard mask in the manufacture of a magnetic tunnel junction device. However, in the case of Ta, the stress of the film is large, which may cause the phenomenon of lifting at the interface of each layer forming the magnetic tunnel junction element. In addition, a process of removing the oxide film to form the metal wiring after the pattern formation with a well-oxidized metal should be additionally applied. There is a problem. In the case of TiN, since the etching selectivity with the magnetic tunnel junction device is not high, it is necessary to deposit a thick layer, and due to the thick metal hard mask, a portion of the hard mug is easily redeposited during the etching process of the magnetic tunnel junction device.

2 and 3 are cross-sectional views showing the magnetic tunnel resistance element shown in FIG.

Figure 2 is a magnetic tunnel junction element with an in-plane MTJ layer, Figure 3 is a magnetic tunnel junction element with a vertical MTJ layer. The magnetic tunnel resistance element shown in FIG. 1 may be the element shown in FIG. 2 or the element shown in FIG. 3. In some cases, it can also be adapted to other types of magnetic tunnel resistance elements.

Referring to FIG. 2, the magnetic tunnel junction element of the in-plane MTJ layer includes a lower electrode layer 31, a pinning layer 32, a pinned layer 33, a tunnel barrier layer 34, and a free layer. And a free layer 35 and a capping layer 36. The lower electrode layer is a metallic material, the pinning layer 33 is an antiferromagnetic material such as PtMn or IrMn, and the pinned layer 33 is a synthetic anti-ferromagnetic material composed of an alloy of Co, Fe, or three layers of CoFeB / Ru / CoFe. ) Consists of a structure. The tunnel barrier layer is a metal oxide, and a high resistance material is used. The free layer 35 is made of an alloy of ferromagnetic materials such as Co, Fe, and Ni. The capping layer 36 is made of a metal material such as Ta, Ru, and the like, and is positioned on the top layer of the MTJ element.

In addition, referring to FIG. 3, the magnetic tunnel junction element having the vertical MTJ layer may include a lower electrode layer 31a, a pinning layer 32a, a pinned layer 33a, a tunnel barrier layer 34a, Free layer 35a, pinned layer 33b. And a capping layer 36a.

4A to 4F are process cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 4A, an interlayer insulating film 11 and gate patterns 12, 13, 14, and 15 are formed on the substrate 10. The gate patterns 12, 13, 14, and 15 may include a lower insulating layer 12, a conductive layer 13, a hard mask layer 15, and sidewall spacers 13. The bit line 16 and the bit line contact 18 penetrating the interlayer insulating layer 16 are formed on the gate pattern. Subsequently, an electrode film 19 to be a lower electrode of the magnetic tunnel junction element is formed.

Subsequently, a multi-layer pattern 30a in which each layer constituting the magnetic tunnel junction element is stacked is formed thereon. Subsequently, an interlayer insulating film pattern 20a having contact holes 60 is formed thereon to pattern each multilayer pattern 30a constituting the magnetic tunnel junction element. Here, the interlayer insulating film pattern 20a eventually serves as a sacrificial film.

Subsequently, referring to FIG. 4B, an ALD process may be performed to prevent the diffusion of copper and to prevent damage due to plasma applied to the side surface during the dry etching process of the multilayer pattern 30a before the copper is embedded in the contact hole 60. The TaN film 41 is applied to the upper, lower and side surfaces of the contact hole 60 by a few nanometers in thickness. The copper film 42 is formed on the contact hole by applying the damascene method.

Referring to FIG. 4C, the copper film 42 and the upper contact hole are applied by applying a chemical mechanical polishing process using an abrasive having a high selectivity due to a difference in removal rate between the copper film 42 and the silicon oxide film, which is the interlayer insulating film 20a. The copper film 42 is removed so that a step of the silicon oxide film may occur about 10 to 20 nanometers. The TaN film 43 having a high selectivity for the copper film 42 and the etching gas is deposited to a thickness of 20 to 30 nanometers on top of the copper film 42 that is removed and remains only inside the contact hole.

Referring to FIG. 4D, the TaN film 43 deposited on the top of the contact hole is removed and planarized using a chemical mechanical polishing process so that the TaN film 43 is not left outside the contact hole.

Subsequently, referring to FIG. 4E, a wet etching is applied to remove the interlayer insulating film 20a other than the contact hole in which the TaN film 43 and the copper film 42 are embedded. Subsequently, the multilayered pattern for forming the MTJ element using the metal hard masks 42 and 43 composed of the copper film 42 and the TaN film 43 as an etching barrier and using an etching gas such as CH 3 OH or CH 4 / NH 3 ( Dry etch 30a). In order to prevent oxidation on the top and side surfaces of the patterned multilayer patterns 30a to form the dry etched metal hard masks 42 and 43 and the MTJ element, the silicon nitride film 44 is chemically vapor deposited (CVD). Deposit. In this process, the TaN film 43 is removed.

Subsequently, as shown in FIG. 4F, the silicon oxide film 20 is deposited on the patterned multilayer pattern 30a and the metal hard masks 42 and 43 covered with the silicon nitride film 45, and then subjected to a CMP process to apply functification. After the metal wiring 50 is formed.

As described above, the method of manufacturing a semiconductor device according to the present embodiment is an etching mask used when dry etching a multi-layered pattern for an MTJ element, and the etching rate of TaN, which is etched by CH3OH or CH4 / NH3, is very low. And using a hard mask containing Cu. In particular, TaN and Cu having high etching selectivity are stacked in the order of TaN / Cu / TaN to realize a metal hard mask having a thickness of about 50 nanometers.

In addition, in order to prevent diffusion of the copper film 42, a structure in which TaN 43 is thinly deposited on upper and lower portions and side surfaces of the copper film 42 is used. In the present exemplary embodiment, when a pattern of a metal hard mask is formed for dry etching of the MTJ layer, a contact hole is formed in the interlayer insulating film, and then a TaN film and a copper film are stacked in the contact hole. Subsequently, the planarization process is performed to leave the TaN film and the copper film only in the buried contact holes. In the planarization process, a high dishing ratio between the silicon oxide layer and the copper film used as the interlayer insulating film is used to cause severe dishing in the contact hole.

The pattern of the metal hard mask can be formed without applying the dry etching process by filling the portion where dishing occurs with the TaN film, and removing the interlayer insulating film, which was used as a die, by leaving the TaN film only in the contact hole again by the planarization process. . Since there is no application of the dry etching process, it is possible to prevent deterioration of the multilayer pattern for the MTJ device, which is a lower layer, when the metal hard mask pattern is formed. The metal hard mask pattern having a high aspect ratio may be formed by a method of forming a pattern through filling a contact hole.

Subsequently, the manufacturing method of the semiconductor device according to the present embodiment will be described in stages.

First, an interlayer insulating film is deposited over the multilayer film to form a metal hard mask pattern on the multilayer film stacked for the MTJ element. Subsequently, a photoresist pattern is prepared by applying a photolithography process to selectively remove the deposited interlayer insulating film to form contact holes. Subsequently, the contact hole is formed by dry etching using the pattern of the photoresist formed on the interlayer insulating film as a mask.

Subsequently, TaN is deposited on the bottom, side, and top of the contact hole by applying an atomic layer deposition process on the contact hole formed in the interlayer insulating film. Subsequently, a TaN film is formed in a contact hole by a damycin process as a barrier film for preventing diffusion of copper.

Subsequently, the copper film formed on the interlayer insulating film is removed by a chemical mechanical polishing process using a slurry having an interlayer insulating film and a high etching selectivity. At this time, dishing is generated in the upper portion of the contact hole. TaN is deposited by sputtering in order to fill up the region caused by dishing on the contact hole.

Subsequently, TaN is formed on the contact hole and the interlayer insulating layer by using a chemical mechanical polishing process to form TaN only in the contact hole. Thus, a metal hard mask pattern made of TaN, copper, and TaN structures is formed. Next, the interlayer insulating film surrounding the metal hard mask pattern is removed.

Subsequently, the multilayer film deposited for the MTJ device is patterned using a metal hard mask pattern as an etch barrier. Subsequently, a silicon nitride film is formed by chemical vapor deposition in order to prevent oxidation of the patterned MTJ element and the upper and side surfaces of the metal hard mask pattern. Subsequently, an interlayer insulating film is formed on the MTJ element on which the silicon nitride film is formed and the metal hard mask pattern, and the upper surface of the metal hard mask is exposed by applying a chemical mechanical polishing process. A metal wire is formed by depositing a metal material such as Ti, TiN, Al, Cu, or the like on the exposed metal hard mask pattern.

As described above, the method of manufacturing a semiconductor device according to the present embodiment does not apply dry etching when forming a pattern of a metal hard mask used as a pattern for a device for MTJ. Therefore, it is possible to prevent damage to each layer constituting the MTJ element, particularly the free layer, on the upper layer by dry etching of the metal hard mask pattern, thereby preventing the deterioration of the characteristics of the MTJ element, such as deterioration of Tunnel Magneto-Resistance (TMR) performance. Can be. In addition, a hard mask pattern in which TaN and copper are laminated with high etching selectivity with each layer of the MTJ element may be used as a barrier in applying a chemical mechanical polishing process for planarization in a subsequent metal wiring process. In addition, by using the metal hard mask pattern made of copper and TaN as the upper electrode, it is possible to form an excellent upper electrode of low resistance.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, I will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

Claims (12)

Forming a multi-layered pattern for forming the magnetoresistive element on the substrate;
Forming a sacrificial layer pattern having holes for exposing predetermined areas of the multilayer pattern to pattern the multilayer pattern;
Forming a metal film pattern in the hole;
Removing the sacrificial layer pattern; And
Forming a magnetoresistive element by patterning a multilayer for constituting the magnetoresistive element using the metal film pattern as an etching mask;
Method for manufacturing a semiconductor device comprising a.
The method of claim 1,
Forming the metal film pattern in the hole
Forming a first diffusion barrier metal along a shape of the hole;
Forming an etching barrier metal on the diffusion preventing metal; And
And forming a second diffusion barrier metal on the etch barrier metal.
The method of claim 1,
Wherein the first and second diffusion barrier metals are TaN, and the etching barrier metal is copper.
The method of claim 2,
Forming the metal film pattern in the hole
Forming a second diffusion barrier metal on the etching barrier metal
In the process of forming the etching barrier metal, the upper portion of the hole is dished using a chemical mechanical polishing process, and the second diffusion barrier metal is formed in the space formed in the upper portion of the hole by the dishing. The semiconductor device manufacturing method characterized by the above-mentioned.
The method of claim 1,
The metal film pattern is a manufacturing method of a semiconductor device, characterized in that the TaN / Cu / TaN pattern.
The method of claim 1,
Forming an insulating film having the same height as the metal film pattern in a peripheral region of the metal film pattern; And
And forming a metal wiring in contact with the metal film pattern.
The method according to claim 6,
Forming an insulating film having the same height as the metal film pattern in the peripheral region of the metal film pattern
Forming the insulating film to cover the metal film pattern; And
And exposing the metal film pattern by a chemical mechanical polishing process.
The method of claim 7, wherein
And forming a silicon nitride film on the top and side surfaces of the metal film pattern to prevent oxidation of the metal film pattern.
The method of claim 1,
A multi-layered pattern for forming a magnetoresistive element is a method for manufacturing a semiconductor device, characterized in that for a magnetic tunnel junction element.
The method of claim 1,
The multilayer pattern is
A lower electrode layer, a pinning layer, a pinned layer, a tunnel barrier layer, a free layer, and a capping layer are stacked.
The method of claim 1,
The multilayer pattern is
A lower electrode layer, a pinning layer, a pinned layer, a tunnel barrier layer, a free layer, a pinned layer, and a capping layer are stacked.
The method of claim 1,
And forming a bit line and a bit line contact between the substrate and the multilayer pattern for forming a magnetoresistive element.

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