KR20120093730A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to reduce manufacturing costs by forming a penetrating electrode. CONSTITUTION: A semiconductor chip comprises a substrate, filler(104), a bonding wire(106), and a first conductive layer(108). The substrate comprises one surface and the other surface facing the one side. A supporting film is laminated at one side of the substrate. A penetration hole is buried in the filler. The bonding wire passes through the filler. The first conductive layer is connected to one end of the bonding wire. A second conductive layer is connected to the other end of the bonding wire. The second conductive layer electrically interlinks the other end of the bonding wire and a bonding pad formed on the other side of the substrate.

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device in which a through electrode is formed with a bonding wire and a method for manufacturing the same.

Recently, with the miniaturization, high performance of electronic products, and the increase in demand for mobile mobile products, the demand for ultra-large-capacity semiconductor memories is increasing. Semiconductor memory manufacturers are trying to increase the storage capacity of semiconductor memory devices through a multi chip package in which several semiconductor chips are mounted in one semiconductor package.

Stack type multi chip packages (P stack type multi chip package) that stacks the semiconductor chips vertically and packaged by a method of mounting a plurality of semiconductor chips in one semiconductor package is preferred. Multi-layer chip package technology can reduce the manufacturing cost of the package through a simplified process and have advantages such as mass production, while lacking a wiring space for electrical connection inside the package due to the increase in the number and size of the stacked chips. have. In view of these considerations, a package structure using a through electrode (TSV) has been proposed as an example of a stack package. The package employing the through electrode has a structure in which a through electrode is formed in each chip at the wafer stage, and then the physical and electrical connection between the chips is made vertically by the through electrode.

In general, a through electrode forms a via on a silicon wafer, a seed film is formed on a surface of the via, and then a metal film filling the via is formed through a plating process. However, since plating is performed from the side surface of the via on which the seed film is formed, there is a problem in that the plating is not performed well and voids are generated or the metal film is unevenly generated, thereby degrading device characteristics. In addition, the plating process has a problem of low productivity and reproducibility.

An object of the present invention is to provide a semiconductor device excellent in electrical characteristics and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can fundamentally eliminate a void generation or a non-uniform plating problem of a through electrode.

It is still another object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can reduce manufacturing costs by forming a through electrode by a simple method.

A semiconductor device according to an embodiment of the present invention includes a semiconductor chip, wherein the semiconductor chip includes a substrate having one surface and the other surface opposite thereto, and a filler filling a through hole formed from one surface of the substrate toward the other surface. And a bonding wire embedded in the filler and penetrating the filler, and a first conductive layer connected to one end of the bonding wire.

The first conductive layer is gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd) , Tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), tantalum (Ta) or molybdenum (Mo) may include any one or more. .

The semiconductor device may further include a support film having an opening in a region where the first conductive layer is located and stacked on one surface of the substrate, and further comprising a second conductive layer connected to the other end of the bonding wire. You may.

In this case, the second conductive layer may electrically connect a bonding pad formed on the other end of the bonding wire and the other surface of the substrate, and may include a seed metal layer and a metal layer stacked on the seed metal layer.

The semiconductor device may include one or more semiconductor chips including a second chip electrically connected to one end or the other end of the bonding wire through solder bumps.

In this case, the second chip may include a second substrate having one surface and the other surface opposite thereto; A second filler filling a second through hole formed from one surface of the second substrate toward the other surface; A second bonding wire embedded in the second filler and penetrating the second filler; And a third conductive layer connected to one end of the second bonding wire.

The second chip may further include a fourth conductive layer connected to the other end of the second bonding wire, and the fourth conductive layer may have a structure in which a seed metal layer and a metal layer are sequentially stacked.

The semiconductor device may be a semiconductor package, a memory module, a computer, a mobile device, or a home appliance.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a via hole from the other surface of the substrate having one surface and the other surface opposite thereto to form the via hole toward the one surface, and forming a first conductive layer on the bottom surface of the via hole. Forming a bonding wire having one end connected to the first conductive layer and standing in the via hole, filling the via hole with a filler, and connecting the other end of the bonding wire to a bonding pad existing on the other surface of the substrate. It may include the step of forming a second conductive layer.

Specifically, the forming of the first conductive layer on the bottom of the via hole may include forming a copper layer on the bottom of the via hole by electroless plating, and on the other end of the bonding wire and the other surface of the substrate. The forming of the second conductive layer connecting the existing bonding pads may include forming a seed metal layer connecting the other end of the bonding wire and the bonding pads on the other surface of the substrate and forming a metal layer on the seed metal layer. It may include the step.

In this case, the seed metal layer may be formed by electroless plating, chemical vapor deposition, or sputtering, and the metal layer may be formed by electroplating.

Meanwhile, after the forming of the second conductive layer connecting the other end of the bonding wire and the bonding pad on the other surface of the substrate, the method may further include grinding one surface of the substrate to expose the first conductive layer. can do.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: forming a bonding wire in the first conductive layer of a support film having a first conductive layer on one surface, forming a through hole in a substrate, and bonding the bonding wire And attaching one surface of the support film and one surface of the substrate to insert a wire into the through hole, and filling the through hole with a filler.

Before forming a bonding wire in the first conductive layer of the support film having the first conductive layer on the one surface or after filling the through hole with the filler, the first conductive layer is directed to the other side of the support film. It may comprise the step of forming an opening in the support film to be exposed.

The method may further include forming a second conductive layer connecting the other end of the bonding wire to the bonding pad existing on the other surface of the substrate after the step of filling the through hole with the filler.

In this case, the forming of the second conductive layer connecting the bonding pads on the other surface of the substrate may include forming a seed metal layer connecting the other end portion of the bonding wire and the bonding pads on the other surface of the substrate. The method may include forming a metal layer on the seed metal layer.

The semiconductor device and its manufacturing method of the present invention have excellent electrical characteristics, can fundamentally eliminate the void problem or uneven plating problem of the through electrode, and can reduce the manufacturing cost by forming the through electrode by a simple method.

1 is a partial cross-sectional view of a semiconductor chip in accordance with an embodiment of the present invention.
2 is a partial cross-sectional view of a semiconductor chip according to another exemplary embodiment of the present invention.
3 and 4 are cross-sectional views of some components of a semiconductor package according to an embodiment of the present invention.
5A through 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
6A through 6F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. In addition, in the drawings, the thicknesses of the films (layers) and regions may be exaggerated for clarity. In addition, if it is mentioned that the film (layer) is on another film (layer) or substrate 'on', 'top' it may be formed directly on the other film (layer) or substrate, or another film (layer) between them. ) May be intervened. In addition, the spatially relative terms 'bottom', 'bottom', 'top', 'top', etc., as shown in the drawings, correlate one device or component with another device or components. It is used to describe easily, and is not used as a term meaning an upper part and a lower part in actual use. That is, the device may be oriented in other directions, and thus spatially relative terms may be interpreted according to the orientation in actual use.

1 is a partial cross-sectional view of a semiconductor chip in accordance with an embodiment of the present invention. Referring to FIG. 1, the semiconductor chip 100 of the present invention includes a substrate 102, a filler 104, a bonding wire 106, and a first conductive layer 108.

The substrate 102 has one surface (bottom surface 102a) and the other surface (top surface 102b) opposite thereto, and is wired to a backing material made of silicon (Si), GaAs, LiTaO ₃ , LiNbO ₃ , sapphire, or the like. The substrate may be formed, or may be a package substrate that electrically connects the semiconductor chip inside the package to an external printed circuit board (PCB) and supports the semiconductor chip, or may be a conventional printed circuit board itself. have. Hereinafter, unless otherwise stated, the substrate 102 will be described based on a silicon wafer. However, the core idea of the present invention may be applied to other materials and substrates of different uses.

There is a through hole penetrating from one surface 102a of the substrate 102 to the other surface 102b, and the through hole may be filled with the filler 104. The filler 104 may fill the through hole to perform fixing and insulating functions of the bonding wire 106. The filler 104 may be formed of an insulator including any one or more of an organic material and an inorganic material, but is not limited to the type of the filler. For example, organic materials such as polyimide, parylene, Teflon, epoxy resin, or benzo-cyclo-butenes (BCB) may be used, and SiOF, SiO _x , and BPSG (borophosphosilicate glass) And inorganic materials such as spin on glass (SOG) materials such as HSQ (hydrosilsesquioxane). In addition, amorphous carbon, elastomers and the like can be used.

The bonding wire 106 may be connected to one surface of the substrate 102 to the other surface to become an electrical connection path. That is, when the stack package is spherical, it may be an electrical connection path between the upper and lower chips. The bonding wire 106 may be a wire including any one or more of gold (Au), silver (Ag) copper (Cu), or aluminum (Al), but the present invention is not limited thereto. Gold is a chemically stable metal and has the advantage of forming wires without surface oxidation in the air, but its high price is a disadvantage. Copper and gold-silver wires have lower electrical conductivity than gold wires, but have a lower price.

The support film 110 may exist on one surface 102a of the substrate. The support film 110 has an opening V ₁ in a region where the first conductive layer 108 is located to expose the first conductive layer 108 so that an electrical connection path between the upper and lower chips is formed when the chips are stacked. You can do that. The support film 110 may be used without limitation as long as the material exhibits non-conductivity. For example, it may include rubber, paper, plastic, ceramic, and the like. Preferably it may be a plastic film. For example, polyethylene terephthalate (PET), polyimide (PI), polyethylene naphthalate (PEN), polystyrene (PS), polyether sulfone (PES), polyarylate (PAR), polycarbonate (PC), polyethylene (PE) or cycloolefin (COC) It may be a plastic film containing any one or more of a copolymer).

The first conductive layer 108 may be electrically connected to one end of the bonding wire 106 and may support the bonding wire 106. The second conductive layer 114 may be present at the other end of the bonding wire 106, and the first insulating layer 112 may be present at the other surface 102b of the substrate. The first insulating layer 112 may be a solder resist. The first conductive layer 108 or the second conductive layer 114 may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), and titanium (Ti). ), Platinum (Pt), palladium (Pd), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), tannium (Ta) or molybdenum ( A metal containing any one or more of Mo), a conductive organic material, a conductive inorganic material, and the like, and may be formed of a single layer film or a multilayer film.

The second conductive layer 114 may be a single layer film or a multilayer film that electrically connects the other end of the bonding wire and a bonding pad (not shown) present on the other surface 102b of the substrate. For example, it may be a multilayer film of a seed metal layer and a metal layer.

2 is a partial cross-sectional view of a semiconductor chip according to another exemplary embodiment of the present invention. 2, a semiconductor chip 100 according to another embodiment of the present invention may include a substrate 102, a filler 104, a bonding wire 106, a first conductive layer 108, and a second conductive layer 123. And a bonding pad 120. Hereinafter, a description will be given with reference to FIG. 2, and the description overlapping with the above-described parts will be omitted or simply described.

A bonding pad 120 may exist on the other surface 102b of the substrate constituting the first chip 100, and the second conductive layer 123 electrically connecting the bonding pad 120 and the bonding wire 106. This may exist. The second conductive layer 123 may be a single layer film or a multilayer film made of a conductive material. For example, the bonding pad 120 and the second conductive layer 123 may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), and titanium. (Ti), platinum (Pt), palladium (Pd), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), tantalum (Ta) or molybdenum It may be a single layer film or a multilayer film of a metal containing any one or more of (Mo). Specifically, the second conductive layer 123 may include a lower 2-1 conductive layer 122 and a 2-2 conductive layer 124 stacked thereon, and the 2-1 conductive layer ( 122 may be a seed metal layer, and the second-second conductive layer 124 may be a metal layer.

In addition, a second insulating layer 126 exposing a portion of the second conductive layer 123 may exist, and the second insulating layer 126 may be a solder resist.

3 and 4 are cross-sectional views of some components of a semiconductor package according to an embodiment of the present invention. The semiconductor package according to an embodiment of the present invention may be a package in which semiconductor chips including the first chip 100 and the second chip 200 are sequentially stacked on the package substrate 50, and the package substrate 50. ) And an interposer 70 may be additionally stacked between the first chip 100 and the first chip 100.

The first chip 100 and the second chip 200 may be the same type of semiconductor chip or may be different types of semiconductor chips. 3 and 4 illustrate, as an example, a semiconductor chip of the type shown in FIG. 2, but a semiconductor chip of the type shown in FIG. 1 may be used. In addition, the number of semiconductor chips shown in FIGS. 3 and 4 is merely an example, and two or more semiconductor chips may be stacked.

The package substrate 50 may electrically connect the semiconductor chip inside the package and an external printed circuit board (PCB) and support the semiconductor chip. The package substrate 50, the interposer 70, the first chip 100, and the second chip 200 may be electrically connected by solder bumps 302, 304, and 306. The first chip 100 and the second chip 200 may be memory devices such as DRAM or FLASH, or may be logic devices. The interposer 70 may be a substrate on which a predetermined circuit pattern is formed for electrical connection between the first chip 100 and the package substrate 50. The first chip 100 and the second chip 200 may be molded with an encapsulant 400 to protect the external chip from the temperature, humidity, and the like. The encapsulant 400 may be an epoxy molding compound (EMC).

The second chip 200 may include a second substrate having one surface and the other surface opposite thereto; A second filler filling a second through hole formed from one surface of the second substrate toward the other surface; A second bonding wire embedded in the second filler and penetrating the second filler; And a third conductive layer connected to one end of the second bonding wire. In addition, the fourth conductive layer corresponding to the second conductive layer described above may be included. As those skilled in the art to which the present invention pertains can sufficiently deduce, detailed reference numerals are omitted in FIGS. 3 and 4.

The semiconductor device of the present invention is a memory module including the above-described laminated package, a computer such as a personal computer (PC), a notebook, a tablet PC, a mobile phone, a mobile phone, a personal digital assistant (PDA), an MP3 player (MP3 Player), and the like. It may be a home appliance such as a device, a refrigerator, a washing machine, or a TV.

 5A through 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. Hereinafter, a description will be given with reference to FIGS. 5A to 5F, but a portion overlapping with the above description will be omitted or simply described.

Referring to FIG. 5A, the supporting film 110 having the first conductive layer 108 is prepared. As described above, the support film 110 may be used without limitation as long as the material shows non-conductivity. The first conductive layer 108 may be used as long as it is a material showing conductivity, but a single layer film or a multilayer film including a copper layer (copper alloy layer) is preferable.

There is no limitation on the method of forming the first conductive layer 108 on the support film 110. For example, the first conductive layer 108 may be formed by laminating a metal film (copper film, copper / aluminum film, etc.) on the support film 110 and patterning. As another example, after forming a metal thin film on the support film 110 by a thin film formation method such as vacuum deposition or sputtering, the process may be patterned. As another example, the support layer 110 may be formed by partially forming the polymer layer having liquid or fluidity on the patterned metal sheet and curing the polymer to partially embed the first conductive layer 108.

Referring to FIG. 5B, a bonding wire 106 is formed on the first conductive layer 108 of the support film 110. There is no limitation on the method of forming the bonding wire 106. For example, the bonding wire 106 can be formed by a wire bonding apparatus. The wire bonding apparatus may position the capillary over the first conductive layer 108 through the XY stage and then lower the capillary to adhere to the first conductive layer 108. In this case, the position of the first conductive layer 108 may be automatically found through the pattern recognition device, or the position of the first conductive layer 108 may be manually found. After forming one end of the bonding wire in the first conductive layer 108, the wire may be cut by a clamp to complete the bonding wire 106.

Referring to FIG. 5C, a substrate 102 is prepared and a through hole H penetrating the substrate is formed. The through hole H may be formed by Deep Reactive Ion Etching (DRIE) or laser drilling, but the formation method is not limited thereto. The first insulating layer 112 may exist on the substrate, and various structures (elements, not shown), such as a transistor, a capacitor, and a bubble pattern, may exist on the substrate 102.

Referring to FIG. 5D, the support film 110 is stacked on one surface 102a of the substrate 102 so that the bonding wire 106 penetrates the inside of the through hole H. Referring to FIG. There is no limitation in the method of bonding the support film 110 and the substrate 102. For example, the support film 110 and the substrate 102 may be adhered through an adhesive layer (not shown), or the support film 110 may be fused to the substrate 102.

Referring to FIG. 5E, the inside of the through hole H is filled with a filler. As described above, the type of the filler 104 is not limited. Filling material 104 may be buried in a chemical vapor deposition (CVD), vacuum evaporation, spin coating, sol-gel coating, screen printing (screen printing) , Dispensing, or the like can be used.

For example, when SiOF is used as a filler, gas (CF ₄ , C ₂ F _6, etc.) containing fluorine (F) is introduced into a PECVD (Plasma Enhance CVD) method using TEOS (Tetra Ethyl Ortho Silicate) and O ₃ . Doping method, using TEOS + H ₂ O + C ₂ F ₆ as the raw material, using Electron Cyclotron Resonance (PER) -PECVD, using a gas substituted with one OC ₂ H ₅ group with F and H ₂ O in TEOS Can be used. As another example, amorphous carbon, fluorine-containing amorphous carbon (aC: F), and hydrogen-containing amorphous carbon (a-Si: H) deposited by PECVD may be used as a filler. As another example, the SOG material and the organic polymer may be filled by spin coating.

Referring to FIG. 5F, an opening V ₁ may be formed on the support film 110 to expose the first conductive layer 108. The opening V ₁ may be an electrical connection path to another semiconductor chip or a substrate existing below the semiconductor chip stacking.

In addition, it is also possible to form opening part V1 _first . That is, before forming the bonding wire (in the state of FIG. 5A), the opening V ₁ may be formed.

Thereafter, the process of forming the second conductive layer (114 of FIG. 1) on the upper surface of the filler 104 may be further roughened. The second conductive layer may be formed as shown in 114 of FIG. 1, and as shown in FIG. 2, to connect the other end of the bonding wire to a bonding pad (not shown) existing on the other surface of the substrate. It may be formed. In this case, the second conductive layer may be a multilayer film including a 2-1 conductive layer and a 2-2 conductive layer, and specifically, may be a seed metal layer and a metal layer formed on the seed metal layer.

6A through 6F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention. Hereinafter, a description will be given with reference to FIGS. 6A to 6F, but a portion overlapping with the above description will be omitted or simplified description.

First, as shown in FIG. 6A, a substrate 102 having one surface 102a and the other surface 102b opposite thereto is prepared. A bonding pad 120 may be present on the other surface 102b of the substrate 102, and a first insulating layer 112 may be present on one surface 102a and / or the other surface 102b of the substrate 102. Although not shown in the drawings, the substrate 102 may be formed with semiconductor devices such as transistors and capacitors, various wiring layers, or the like.

Next, as shown in FIG. 6B, a via hole V ₂ is formed from the other surface 102b of the substrate 102 toward the one surface 102a. The via hole V ₂ may be formed by a DRIE or laser drilling method, but is not limited thereto. In addition, although the cross sectional area of the via hole V ₂ is illustrated, the cross sectional area may not be constant. For example, the cross sectional area may be narrowed toward the bottom of the via hole V ₂ (toward one surface 102a of the substrate).

Next, as illustrated in FIG. 6C, a bonding wire 106 may be formed after the first conductive layer 108 ′ is formed on the bottom surface of the via hole V ₂ and the first insulating layer 112. The first conductive layer 108 ′ is sufficient to be formed (coated) at least on the bottom surface of the via hole V ₂ and may not necessarily be formed on the entire surface of the substrate. In addition, an insulating layer (not shown) for electrical insulation between the first conductive layer 108 ′ and the substrate 102 on the bottom or side surfaces of the via hole V ₂ before the first conductive layer 108 ′ is formed. Can be additionally formed.

The first conductive layer 108 ′ may be formed by chemical vapor deposition, sputtering, electroless plating, screen printing, or the like, but is not limited thereto. For example, a copper layer, a nickel layer, an aluminum layer, a gold layer, etc. may be formed by electroless plating, and a thin film of tungsten, aluminum, etc. may be formed by chemical vapor deposition, and metal (copper, Aluminum, silver, etc.) paste may be applied, followed by drying and firing to form the first conductive layer 108 '.

There is no limitation on the method of forming the bonding wire 106. For example, FIG. 6C illustrates a method of forming a bonding wire by a wire bonding apparatus. That is, the capillary 130 is positioned above the via hole V ₂ of the substrate 102 through the XY stage of the wire bonding apparatus, and then the capillary 130 is lowered to exist on the bottom surface of the via hole V ₂ . After bonding to the first conductive layer 108 can be bonded by applying ultrasonic energy (untrasonic energy) and thermal energy, and may be bonded while applying a load through the capillary 130. Thereafter, the wires 130 may be lifted up to cut the wires by the clamps 132 to complete the bonding wires 106.

Next, as shown in FIG. 6D, the via hole V ₂ may be filled with the filler 104. In FIG. 6D, the first conductive layer 108 ′ on the first insulating layer 112 is removed to leave the first conductive layer 108 only on the bottom surface of the via hole V ₂ . 112. The upper first conductive layer 108 'may not be removed. If not removed, it may be used as part of the second conductive layer to be described later.

The filler 104 may be used without limitation as long as it is a non-conductive material, and chemical vapor deposition, vacuum deposition, spin coating, sol-gel coating, screen printing, and dispensing may be used. For example, when SiOF is used as a filler, gas (CF ₄ , C ₂ F _6, etc.) containing fluorine (F) is introduced into a PECVD (Plasma Enhance CVD) method using TEOS (Tetra Ethyl Ortho Silicate) and O ₃ . Doping method, using TEOS + H ₂ O + C ₂ F ₆ as the raw material, using Electron Cyclotron Resonance (PER) -PECVD, using a gas substituted with one OC ₂ H ₅ group with F and H ₂ O in TEOS Can be used. As another example, amorphous carbon, fluorine-containing amorphous carbon (aC: F), and hydrogen-containing amorphous carbon (a-Si: H) deposited by PECVD may be used as a filler. As another example, the SOG material, the organic polymer, or the like may be filled by spin coating.

Next, as shown in FIG. 6E, the second-first conductive layer 122 connecting the other end (upper end) of the bonding wire 106 to the bonding pad 120 existing on the other surface of the substrate 102 is connected. Can be formed. For example, the second-first conductive layer 122 may be a seed metal layer. The 2-1 conductive layer 122 may be formed by chemical vapor deposition, sputtering, electroless plating, or the like, and the method of forming the second conductive layer 122 is not limited thereto. That is, after coating (depositing) the material forming the 2-1 conductive layer (seed metal layer) on the entire surface of the substrate and patterning, the 2-1 conductive layer (seed metal layer) 122 as shown in FIG. 6E. ) Can be formed. In addition, as described above, the first conductive layer 108 ′ present on the first insulating layer 112 may be used as a seed metal layer without removing the first conductive layer 108 ′.

Next, as shown in FIG. 6F, the second-first conductive layer 124 is formed on the second-first conductive layer 122 to form the second-first conductive layer 122 and the second-two conductive layer ( The second conductive layer 123 including the 124 may be formed. The second-2 conductive layer 124 can be used without limitation as long as it is a conductive material, but a material containing metal is preferable. Thereafter, the second insulating layer 126 may be additionally formed. The second conductive layer 123 does not have to be a two-layered structure, and may have a structure in which any one of the second-one conductive layer 122 or the second-two conductive layer 124 is omitted, or a multilayer of three or more layers. It may be a structure. The second conductive layer 124 may be formed by chemical vapor deposition, sputtering, electroplating, or the like, and the method of forming the second conductive layer 124 is not limited thereto. For example, the second-second conductive layer 124 made of a copper layer may be formed by electroplating.

Thereafter, one surface 102a of the substrate may be ground to expose the first conductive layer 108 to manufacture a semiconductor chip as shown in FIG. 2, and FIGS. 3 and 4 using a known semiconductor package manufacturing technique. Laminated packages such as those shown in FIG. In addition, a memory module including the laminated package manufactured as described above, a personal computer (PC), a notebook (notebook), a computer such as a tablet PC, mobile phones, mobile devices such as PDA (Personal Digital Assistant), MP3P (MP3 Player) And home appliances such as a refrigerator, a washing machine, and a TV can be manufactured.

102 substrate 104 filler
106: bonding wire 108: first conductive layer
110: support film 112: first insulating layer
114 and 123: second conductive layer 120: bonding pad
122: 2-1 conductive layer 124: 2-2 conductive layer
126: second insulating layer 302, 304, 306: solder bump

Claims (20)

In a semiconductor device comprising a semiconductor chip, the semiconductor chip
A substrate having one surface and the other surface opposite thereto;
A filler filling a through hole formed from one surface of the substrate toward the other surface;
Bonding wires embedded in the filler to penetrate the filler; And
And a first conductive layer connected to one end of the bonding wire. The method of claim 1,
The first conductive layer is gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd) , Tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), tantalum (Ta) or molybdenum (Mo) . The method of claim 1,
The semiconductor device further comprises a support film having an opening in a region where the first conductive layer is located and laminated on one surface of the substrate. The method of claim 1,
And a second conductive layer connected to the other end of the bonding wire. The method of claim 4, wherein
And the second conductive layer electrically connects the other end of the bonding wire and a bonding pad formed on the other surface of the substrate. The method of claim 5,
The second conductive layer includes a seed metal layer and a metal layer stacked on the seed metal layer. The method of claim 1,
And at least one semiconductor chip including a second chip electrically connected to one end or the other end of the bonding wire through solder bumps. The method of claim 7, wherein
The second chip may include a second substrate having one surface and the other surface opposite thereto; A second filler filling a second through hole formed from one surface of the second substrate toward the other surface; A second bonding wire embedded in the second filler and penetrating the second filler; And a third conductive layer connected to one end of the second bonding wire. 9. The method of claim 8,
The second chip further includes a fourth conductive layer connected to the other end of the second bonding wire. 10. The method of claim 9,
The fourth conductive layer has a structure in which a seed metal layer and a metal layer are sequentially stacked. The method of claim 1,
The semiconductor device is a semiconductor package, a memory module, a computer, a mobile device or a home appliance. Forming a via hole from the other surface of the substrate having one surface and the other surface opposite thereto to the one surface;
Forming a first conductive layer on a bottom of the via hole;
Forming a bonding wire having one end connected to the first conductive layer and standing in the via hole;
Filling the via hole with a filler; And
Forming a second conductive layer connecting the other end of the bonding wire to a bonding pad existing on the other surface of the substrate;
Method for manufacturing a semiconductor device comprising a. The method of claim 12,
The forming of the first conductive layer on the bottom of the via hole includes forming a copper layer on the bottom of the via hole by electroless plating. The method of claim 12,
Forming a second conductive layer connecting the other end of the bonding wire and the bonding pads on the other surface of the substrate may include forming a seed metal layer connecting the other end of the bonding wire and the bonding pads on the other surface of the substrate. Forming and forming a metal layer on the seed metal layer. 15. The method of claim 14,
And the seed metal layer is formed by electroless plating, chemical vapor deposition, or sputtering, and the metal layer is formed by electroplating. The method of claim 12,
After forming the second conductive layer connecting the other end of the bonding wire and the bonding pads on the other surface of the substrate, grinding the one surface of the substrate to expose the first conductive layer. Manufacturing method of the device Forming a bonding wire on the first conductive layer of the support film having the first conductive layer on one surface;
Forming a through hole in the substrate;
Attaching one surface of the support film and one surface of the substrate such that the bonding wire is inserted into the through hole; And
Filling the through-hole with a filler
Method for manufacturing a semiconductor device comprising a. 18. The method of claim 17,
Before forming a bonding wire in the first conductive layer of the support film having the first conductive layer on the one surface or after filling the through hole with the filler, the first conductive layer is directed to the other side of the support film. Forming an opening in the support film so as to be exposed. 18. The method of claim 17,
And forming a second conductive layer connecting the other end of the bonding wire and the bonding pad on the other surface of the substrate after the step of filling the through hole with a filler. 20. The method of claim 19,
The forming of the second conductive layer connecting the bonding pads existing on the other surface of the substrate may include forming a seed metal layer connecting the other end portion of the bonding wire and the bonding pads existing on the other surface of the substrate and the seed metal layer. Forming a metal layer on the semiconductor device;

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