KR20120084602A - A redundancy control circuit for 1t-sram using electrical fuse programming - Google Patents

Abstract

PURPOSE: A redundancy control circuit of a 1T-SRAM using an electrical fuse programming is provided to prevent the drop of program power by directly applying external program power to an e-Fuse(electrical Fuse) cell in a program mode. CONSTITUTION: A program selection bit selecting unit(220) selects a specific bit line by outputting a bit line selection signal which is reversed through decoding. An e-Fuse cell array(230) programs a failed address by activating an e-Fuse cell connected to the selected word line and the bit line. A repair address comparing unit(240) outputs a matching signal if the failed address is identical to a memory access address at each bit. When the failed address is programmed in the e-Fuse cell array, an external voltage source is supplied.

Description

A redundancy control circuit for 1T-SRAM using electrical fuse programming

The present invention relates to a redundancy control circuit, and more particularly, in the program mode, an external program power is directly applied to an e-use cell, and the e-use cell is separated into a write port and a read port. The present invention relates to a 1T-SRAM redundancy control circuit using electrical fuse programming with a significantly reduced layout area.

Recently, as the resolution of display panels increases, a large amount of SRAM IP is required. Large-scale SRAM IP is being researched using 1T-SRAM cell with small cell size instead of 6T-SRAM cell.

On the other hand, as memory capacity increases, defects occur due to process defects, etc., resulting in a decrease in memory yield. Therefore, a large memory requires a redundancy circuit that replaces a defective memory cell with a spare memory cell. The redundancy circuit allows data to be read or written from a redundant memory cell when a repair address is selected that selects a defective memory cell.

The method of programming the repair address of a defective memory cell is a laser program method of cutting a metal fuse or a polysilicon fuse using a laser having a large energy, and a high current in a polysilicon fuse. An e-Fuse (electrical fuse) program method that blows fuses by flowing a high current, and short-circuits by applying a high voltage to an antifuse, an oxide-nitride-oxide (ONO) capacitor, which is a thin oxide film There is an antifuse program.

Of these programming methods, the e-Fuse method does not require laser equipment, does not require a charge pump to supply a high voltage, and can be programmed in both a wafer state and a package state.

1 is a diagram illustrating a conventional e-Fuse cell circuit.

As shown in FIG. 1, the conventional e-Fuse cell circuit 100 includes an e-Fuse, first to fifth NMOSs MN1 to MN5, first to second PMOSs MP1 and MP2, and a reference. A resistor Rref is provided.

The e-Fuse is a gate polysilicon, and a logic voltage VDD is applied at one end thereof, and the other end thereof is connected to the node 1 (N1). The first NMOS MN1 is a program transistor, and a program signal PGM is applied to a gate, a ground voltage VSS is applied to a source, and a drain thereof is connected to the node 1 N1. The second to third NMOSs MN2 are reset transistors. The reset signal MRESET is applied to the gate, the ground voltage VSS is applied to the source, and the drain of the second NMOS MN2 is the node 3 (MN2). At N3), the drain of the third NMOS MN3 is connected to node 4 N4, respectively.

The first to second PMOS MP1 and MP2 and the fourth to fifth NMOSs MN4 and MN5 constitute a latch circuit, and the first PMOS MP1 has a source connected to the node 1 N1. The drain is connected to node 3 (N3) and the gate is connected to node 4 (N4). The second PMOS MP2 has a source connected to node 2 (N2), a drain connected to node 4 (N4), and a gate connected to node 3 (N3). In the fourth NMOS MN4, a ground voltage VSS is applied to the source, a drain is connected to the node 3 (N3), and a gate is connected to the node 4 (N4). In the fifth NMOS MN5, a ground voltage VSS is applied to a source, a drain is connected to node 4 (N4), and a gate is connected to node 3 (N3). The logic resistor VDD is applied at one end of the reference resistor Rref, and the other end is connected to the node 2 N2.

The operation of the conventional e-Fuse cell circuit 100 configured as described above is as follows.

In the program mode, when the program signal PGM is activated high, a high current flows in the e-use, causing the e-use to blow. At this time, the reset signal MRESET remains low. Whether or not the e-Fuse is cut off applies a pulse to the reset signal MRESET while the program signal PGM is low. If the resistance of the e-Fuse is smaller than the reference resistance Rref, the voltages of the node 3 (N3) and the node 4 (N4) are latched to the logic voltage VDD and 0V, respectively. When the e-Fuse is programmed, the e-Fuse resistance is larger than the reference resistance Rref, so the voltages of the node 3 (N3) and the node 4 (N4) are latched to 0 V and the logic voltage VDD, respectively.

However, the conventional technique of programming the repair address of a memory cell using the conventional e-Fuse cell circuit reduces the logic voltage (VDD) to 1.2V or less as the semiconductor process technology scales down. There is a problem that the program power applied to the fuse cell is reduced. If sufficient program power is not applied to the e-Fuse as described above, the possibility of program defects is increased.

In addition, a circuit that compares a programmed repair address with a memory access address may be implemented using a CMOS logic circuit, but a layout area occupied increases as the number of repairable memory bits increases.

The technical problem to be solved by the present invention is to apply an external program power directly to the e-Fuse cell in the program mode, to separate the e-Fuse cell into a write port and a read port, and to achieve electrical fuse programming that significantly reduces the layout area. It is to provide a redundancy control circuit of 1T-SRAM used.

The redundancy control circuit of 1T-SRAM using e-Fuse programming according to the present invention for achieving the above technical problem, receives a row address and outputs the inverted word line selection signal (WWLb) through decoding to select a specific word line A row decoder unit 210 to cause it; A program select bit selector 220 for receiving a column address and outputting a bit line select signal BIT_SELb inverted through decoding to select a specific bit line; An e-Fuse cell array 230 in which a bad address is programmed by activating an e-Fuse cell connected to the selected word line and bit line; And a repair address comparison unit 240 for comparing the bad address and the memory access address MA for each bit and outputting a matching signal FA_MATCH when the match is performed. It is characterized by supplying an external voltage source (FSOURCE) when programmed in.

The present invention solves the problem that the program power applied to the e-Fuse cell falls, and the layout area is reduced by about 19%.

1 is a diagram illustrating a conventional e-Fuse cell circuit.
2 is a block diagram of a redundancy control circuit of 1T-SRAM using electrical fuse programming in accordance with the present invention.
FIG. 3A illustrates a timing diagram of a program mode in a redundancy control circuit of 1T-SRAM using electrical fuse programming according to the present invention.
3b is an electrical fuse according to the invention Shows a timing diagram of a power-on read mode in a 1T-SRAM redundancy control circuit using programming.
3c is an electrical fuse according to the invention A timing diagram of a comparison mode in a 1T-SRAM redundancy control circuit using programming is shown.
4 is a circuit diagram showing a detailed configuration of a dual port e-Fuse cell of a redundancy control circuit of 1T-SRAM using electrical fuse programming according to the present invention.
5 is a circuit diagram illustrating a detailed configuration of a repair address comparison unit of a redundancy control circuit of 1T-SRAM using electrical fuse programming according to the present invention.
6 is a diagram illustrating a simulation result comparing program power applied to a dual port e-Fuse cell and program power applied to a conventional e-Fuse cell according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

2 is a block diagram of a redundancy control circuit of 1T-SRAM using electrical fuse programming in accordance with the present invention.

Referring to FIG. 2, the redundancy control circuit 200 of 1T-SRAM using electrical fuse programming according to the present invention includes a row decoder 210, a program bit selector 220, and an e-Fuse cell array 230. The repair address comparison unit 240 and the power switching unit 250 are included. In addition, it further includes a control logic 260 for generating a control signal required in accordance with an operation mode, that is, a program mode, a power-on read mode and a comparison mode.

The row decoder 210 receives a row address RA_OTP [2: 0] and outputs a word line selection signal (WWLb (Write Word-Line bar) [7: 0] signal) inverted through decoding. Select the word line. The program bit selection circuit unit 220 receives the column address FA [3: 0] and outputs the bit line selection signal PGM_BIT_SELb [9: 0] signal inverted through decoding to select a specific bit line. .

In the e-Fuse cell array 230, a defective address is programmed by activating an e-Fuse cell connected to the selected word line and bit line. The repair address comparison unit 240 compares the bad address stored in the e-Fuse cell array 230 with the memory access address MA [9: 0] for each bit and compares the matching signals FA_MATCH [in the comparison mode. 7: 0] signal) high to output. However, if no matching address is found, all of the matching signals FA_MATCH [7: 0] will be output low.

The power switching unit 250 supplies an external voltage source FSOURCE in a program mode and a logic voltage VDD in a power-on read mode and a comparison mode.

In the redundancy control circuit according to an embodiment of the present invention, the capacity of the e-Fuse cell is 8 x 10 bits, and the cell array is composed of 8 rows x 10 columns, thereby providing a total of eight bad memory repair addresses. Save it. The 1T-SRAM used in the display driving chip is repaired in word-line units, considering the layout area. Ten columns of the e-Fuse cell array indicate the number of address bits of the 1T-SRAM used in the WVGA class. Considered.

The logic voltage VDD is 1.2V, and the external program voltage source FSOURCE supplies 4.2V in program mode and 0V in power-on read mode and compare mode. Because of the large program current, the program is performed bit by bit, taking into account the voltage drop in the power supply line. The program voltage is 4.2V and the program time is 200mA. The MOS device used in the design uses a 1.2V logic transistor and a 3.3V medium voltage (MV) transistor.

3A, 3B and 3C show timing diagrams of a program mode, a power-on read mode, and a comparison mode, respectively, which are operating modes of a redundancy control circuit of 1T-SRAM using electrical fuse programming according to the present invention.

Referring to FIG. 3A, the program mode is a mode in which a repair address of a bad memory cell is programmed into an e-use cell. In the present invention, an external voltage source FSOURCE is used to supply sufficient program power to the e-use cell. Since an embodiment of the present invention uses a 3.3V transistor, the external voltage source FSOURCE uses 4.2V, which is 1.33 times the 3.3V. In general, a 3.3V device has a maximum voltage of 3.6V when reliability is considered. However, in the present invention, 4.2V is preferable because the e-Fuse cell is programmed only once.

 In operation in the program mode, the program signal PGM is applied with the control logic to the row address RA_OTP [2: 0], the column address FA [3: 0], and the external voltage source FSOURCE of 4.2V. ) Is applied high for 200us. As a result, the e-Fuse cell specified by the row address RA_OTP [2: 0] and the column address FA [3: 0] is programmed. At this time, the memory access address MA [9: 0] maintains a don't care state.

3B, the power-on mode is a mode for automatically storing program information of an e-Fuse cell in a D-latch circuit. Looking at the operation in the power-on mode, after the power-on, when the RSTb signal is activated from low to high by the control logic, the e-Fuse in response to the sensing signal (SAEN signal) of the redundancy control circuit. Program information is stored in the D-latch circuit through the read port transistor of the e-Fuse cell.

Finally, referring to FIG. 3C, the comparison mode is a mode for comparing whether a repair address of a bad memory cell, which is program information of an e-Fuse cell, and a memory access address match.

Looking at the operation in the comparison mode, when the bad address comparison signal (COMP_FA) is activated high with the memory access address (MA [9: 0]) applied first, eight memory repair addresses stored in the D-latch circuit. After comparing with the memory access address, the result is output as a matching signal (FA MATCH [7: 0] signal). That is, if there are e-Fuse rows that match the memory access addresses MA [9: 0] among the eight bad addresses stored in the D-latch circuit, the matching rows among the matching signals FA_MATCH [7: 0] are high ( high) will be activated and output. At this time, the external voltage source FSOURCE applies 0V and the RSTb signal applies a logic voltage VDD.

4 is a circuit diagram showing a detailed configuration of a dual port e-Fuse cell of a redundancy control circuit of 1T-SRAM using electrical fuse programming according to the present invention.

As shown in FIG. 4, the dual port e-Fuse cell circuit 230 according to an embodiment of the present invention may include a NOR gate NOR, an e-Fuse 211, and first to second NMOSs MN1. , MN2), first PMOS MP1, and D-latch circuit 212.

The NOR gate receives an inverted bit line selection signal (PGM_BIT_SELb [9: 0] signal) and an inverted word line selection signal (WWLb [7: 0] signal) and an output terminal is connected to the node 1 (N1). . The e-Fuse 212 has an external voltage source FSOURCE at one end thereof and is connected to the node 2 N2 at the other end thereof.

The first NMOS MN1 is a write port transistor, and an output of the NOR gate NOR is applied to a gate, a ground voltage VSS is applied to a source, and a drain is connected to the node 2 (N2). The second NMOS MN2 is a read port transistor, in which a sensing signal SAEN is applied to a gate, a drain is connected to the node 3 N3, and a source is connected to the node 2 N2.

In the dual port e-Fuse cell circuit 230 according to an embodiment of the present invention, the first NMOS MN1 uses a large channel width of 90 μm to allow sufficient program current to flow in the program mode. The second NMOS MN2 uses a small channel width of 1 μm to reduce the read current.

The first PMOS MP1 is a pull-up load transistor. The inverted load signal LOADb is applied to a gate, a logic voltage VDD is applied to a source, and a drain thereof is connected to the node 3 N3. The D-latch circuit receives the output signal Fuse_Data of the node 3 and receives the bad address IRA signal and the inverted bad address IFAb signal in response to the sensing signal SAEN and the inverted sensing signal SAENb. Output

D-latch circuit 212 according to an embodiment of the present invention is the second to third PMOS (MP2, MP3), the third to fourth NMOS (MN3, MN4), the transmission gate (212-1) and First to third inverters INV1 to INV3 are provided.

In the second PMOS MP2, an output of the node 3 (Fuse_Data) is applied to a gate, and the logic voltage VDD is applied to a source. The inverted sensing signal SAENb is applied to a gate of the third PMOS MP3, and a source is connected to the drain of the second PMOS. In addition, the sensing signal SAEN is applied to the gate of the third NMOS MN3, the drain is connected to the third PMOS drain, and the output of the node 3 Fuse_Data is connected to the gate of the fourth NMOS MN4. The ground voltage VSS is applied to the source, and the drain is connected to the source of the third NMOS.

The first inverter INV1 inverts the voltage level of the third NMOS MN3 drain to output the bad address IFA signal, and the second inverter INV2 inverts the output of the first inverter to The inverted bad address IFAb signal is output, and the third inverter inverts the output of the first inverter and outputs the inverted address. One end of the transmission gate 212-1 is connected to the third inverter output terminal and the other end thereof is connected to the first inverter input terminal.

The operation of the dual-mot e-use cell circuit configured as described above is described in the program mode and the power-on read mode as follows.

First, the external voltage source FSOURCE is supplied by the power switching unit 250 to the voltage applied to the e-Fuse cell in the program mode. According to an embodiment of the present invention, the external voltage source is 4.2V. At this time, the e-Fuse cell selected by the row address RA_OTP [2: 0] and the column address FA [3: 0] has an inverted word line selection signal (WWLb signal) and an inverted bit line selection signal ( The PGM_BIT_SELb signals) are all 0V, and the first NMOS MN1 of the write port is turned on. On the other hand, in the unselected e-Fuse cell, the power supply voltage VPP is applied to at least one signal among the inverted word line selection signal (WWLb signal) and the inverted bit line selection signal (PGM_BIT_SELb signal). One NMOS MN1 is turned off (Turn-OFF).

The cell programmed as described above causes the e-Fuse to blow as a large program current flows through the path of the external voltage source FSOURCE, e-Fuse, and the first NMOS MN1. The blown e-Fuse has a resistance of several tens of KΩ or more. Meanwhile, in the program mode, the D-latch circuit 215 maintains an opaque state.

Next, the load signal (LOADb signal) inverted by the control logic in the power-on read mode becomes low, while the fuse data of the node 3 is logic by the first PMOS MP1 of the pull-up load. Pulled up to voltage VDD. When the RSTb signal is switched from low to high and the sensing signal (SAEN signal) is activated high, the information of the e-use is lost due to the D-latch (Internal Failed Address, IFA). Is latched). In other words, when the e-Fuse is not programmed or programmed, the bad address IFA is latched to 0V and logic voltage VDD, respectively.

5 is a circuit diagram illustrating a detailed configuration of a repair address comparison unit of a redundancy control circuit of 1T-SRAM using electrical fuse programming according to the present invention.

As shown in FIG. 5, the repair address comparison unit 240 using the dynamic pseudo NMOS logic according to the present invention includes a fourth to fifth PMOS (MP4, MP5) and a bad address comparison circuit unit. 241 and fourth to fifth inverters INV4 and INV5.

In the fourth PMOS MP4, the comparison signal COMP_EN by the control logic is applied to the gate, the logic voltage VDD is applied to the source, the drain is connected to the node 4 N4, and the fifth PMOS MP5 is applied. The logic voltage VDD is applied to the source, the gate is connected to node 5 (N5), and the drain is connected to node 4 (N4).

The bad address comparison circuit unit 241 receives the bad address IFA and the memory access address MA and compares the bad address and the memory access address bit by bit in response to a comparison signal COMP_EN to match bits. If so, the internal matching signal IMATCH is output to the node 4 N4.

In the fourth inverter, an input terminal is connected to the node 4 (N4), an output terminal is connected to the node 5 (N5), and the fifth inverter inverts the voltage level of the fourth inverter to output a matching signal FA_MATCH.

In response to the comparison signal COMP_EN, the bad address comparison circuit unit 241 according to the embodiment of the present invention may compare the bad memory address and the memory access address by one bit, respectively, by 1-bits of first to Nth bits. It consists of bad address comparison circuit.

The first 1-bit bad address comparison circuit includes fifth to tenth NMOSs MN5 to MN10. The fifth NMOS MN5 is applied with the first bit IFAb [0] of the inverted bad address to the gate, the drain is connected to the node 4, and the sixth NMOS MN6 is connected to the gate with the bad bit. The first bit IFA [0] of the address is applied and connected in parallel with the fifth NMOS. The seventh NMOS MN7 has its gate applied with the first bit MA [0] of the memory access address, the drain is connected to the source of the fifth NMOS, and the eighth NMOS MN8 has its gate. The first bit MAb [0] of the inverted memory access address is applied to the drain, and the drain is connected to the source of the sixth NMOS. In the ninth NMOS MN9, the comparison signal COMP_EN is applied to a gate, a ground voltage VSS is applied to a source, a drain is connected to a source of the sixth NMOS, and a tenth NMOS is connected to a gate. The comparison signal COMP_EN is applied, a ground voltage VSS is applied to the source, and a drain is connected to the source of the eighth NMOS.

The first to Nth bad address comparison circuits 241-1 to 241 -N are connected in parallel between the node 4 (N6) and the ground voltage VSS, respectively, and each of the bad address comparison circuits is identical to each other. MA [9: 0]) is compared with the address of the bad memory cell by 1 bit.

The operation of the N-bit bad address comparison circuit using dynamic pseudo NMOS logic according to the present invention connected as described above is as follows.

When the comparison signal COMP_EN is 0V, the node 4 N4 maintains a precharge state with the logic voltage VDD, and the matching signal FA_MATCH signal outputs the logic voltage VDD. First, in the comparison mode, the comparison signal COMP_EN is activated high while the memory access address MA [9: 0] is set-up first.

If the 10-bit memory access address (MA [9: 0]) and the bad address (IFA [9: 0]) both match bits, node 4 (N4) maintains the logic voltage (VDD) and the bad address. The matching signal FA_MATCH signal outputs a logic voltage VDD, which means that the signals match. If any one of the 10-bit addresses differs more than one bit, node 4 (N4) is discharged to 0V, and the matching signal FA_MATCH signal outputs 0V.

The fifth PMOS MP7 is a latch-back transistor to prevent the node 4 (N4) from falling low due to coupling noise when all N-bit addresses match. It is to.

As a result, if even one of the matching signals FA_MATCH [7: 0] is outputted with the logic voltage VDD, one of the eight stored bad addresses is matched, and thus, the normal cell of 1T-SRAM is disabled. And replaced with a repair cell.

6 is a diagram illustrating a simulation result comparing program power applied to a dual port e-Fuse cell and program power applied to a conventional e-Fuse cell according to the present invention.

The 1T-SRAM redundancy control circuit according to the present invention was designed using Dongbu HiTek 0.11㎛ Mixed Signal process. Referring to FIG. 6, it can be seen that an e-Fuse cell according to the present invention is applied with more program power than when using a conventional e-Fuse cell.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

Claims (11)

In the redundancy control circuit,
A row decoder 210 for receiving a row address and outputting a word line selection signal WWLb inverted through decoding to select a specific word line;
A program select bit selector 220 for receiving a column address and outputting a bit line select signal BIT_SELb inverted through decoding to select a specific bit line;
An e-Fuse cell array 230 in which a bad address is programmed by activating an e-Fuse cell connected to the selected word line and bit line; And
And a repair address comparison unit 240 for outputting a matching signal FA_MATCH when the bad address and the memory access address MA are compared and matched for each bit.
Redundancy control circuit of 1T-SRAM using electrical fuse programming, characterized in that for supplying an external voltage source (FSOURCE) when the bad address is programmed into the e-Fuse cell array. The method of claim 1,
A program mode for programming the bad address into the e-Fuse cell array;
A power-on mode for automatically storing program information of the e-Fuse cell array in a D-latch circuit; And
Redundancy control circuit of 1T-SRAM using electrical fuse programming, characterized in that the operation mode compares the program information of the e-Fuse cell array and the memory access address. The method of claim 2,
A power supply for supplying the external voltage source FSOURCE to the e-Fuse cell array in the program mode and a logic voltage VDD to the e-Fuse cell array in the power-on read mode and the compare mode. Redundancy control circuit of 1T-SRAM using electrical fuse programming, characterized in that it further comprises a switching unit (250). The method of claim 3, wherein
Redundancy control circuit of 1T-SRAM using electrical fuse programming, characterized in that the external voltage source (FSOURCE) is 4.2V. The method of claim 1, wherein the e-Fuse cell,
Redundancy control circuit of 1T-SRAM using electrical fuse programming, characterized in that the write port (read port) and read port (read port) is separated from the dual port (dual port) structure. The method of claim 5, wherein the e-Fuse cell,
A NOR gate NOR receiving the inverted word line selection signal WWLb and the inverted bit line selection signal BIT_SELb and performing a negative logic sum operation;
A first NMOS NM1 having a NOR output applied to a gate and a ground voltage VSS applied to a source;
An e-Fuse having one end connected to the first NMOS drain and an external voltage source FSOURCE applied to the other end;
A second NMOS MN2 having a sensing signal SAEN applied to a gate thereof, and a source of which is connected to the drain of the first NMOS NM1;
A first PMOS MP1 having an inverted load signal LOADb applied to a gate, a logic voltage VDD applied to a source, and a drain thereof connected to a drain of the second NMOS MN2; And
The bad address IFA and the inverted bad address IFAb are received in response to the sensing signal SAEN and the inverted sensing signal SAENb by receiving the voltage level Fuse_Data of the drain of the second NMOS MN2. Redundancy control circuit of 1T-SRAM using electrical fuse programming, characterized in that it comprises an output D-latch circuit. The method according to claim 6,
The channel width of the first NMOS (MN1) is greater than the channel width of the second NMOS (MN2) 1T-SRAM redundancy control circuit using electrical fuse programming. The method of claim 7, wherein the D-latch circuit,
A second PMOS MP2 having a gate connected to the first PMOS drain and the second NMOS drain in common, and having a logic voltage VDD applied to the source;
A third PMOS (MP3) having the inverted sensing signal (SAENb) applied to a gate and having a source connected to the second PMOS drain;
A third NMOS MN3 having a sensing signal SAEN applied to a gate thereof and a drain thereof connected to the third PMOS drain;
A fourth gate connected to the first PMOS drain and the second NMOS drain in common, a drain connected to the third NMOS source, and a ground voltage VSS applied to the source; NMOS (MN4);
A first inverter outputting the bad address IFA signal by inverting the voltage level of the third NMOS drain;
A second inverter for inverting the output of the first inverter and outputting the inverted bad address (IFAb) signal;
A third inverter for inverting the output of the first inverter; And
Electrical fuse programming in response to the sensing signal (SAEN) and the inverted sensing signal (SAENb), one end of which is connected to the third inverter output terminal and the other end of which is connected to the first inverter input terminal. Redundancy control circuit of 1T-SRAM used. The method of claim 1, wherein the repair address comparison unit,
A fourth PMOS MP4 having a comparison signal COMP_EN applied to the gate and a logic voltage VDD applied to the source;
The internal matching signal IMATCH is output to the fourth PMOS drain when the bad address and the memory access address correspond to each bit in response to the comparison signal COMP_EN by receiving the bad address and the memory access address. A bad address comparison circuit unit 241;
A fourth inverter (INV4) for inverting and outputting the voltage level of the fourth PMOS drain;
A fifth PMOS (MP5) having a gate applied with an output of the fourth inverter, a logic voltage (VDD) applied to a source, and a drain connected to the fourth PMOS drain; And
And a fifth inverter (INV5) outputting the matching signal FA_MATCH by inverting the output voltage level of the fourth inverter. The redundancy control circuit of 1T-SRAM using electric fuse programming. The method of claim 9, wherein the bad address comparison circuit unit 241,
1 to N-th 1-bit bad address comparison circuits 241-1 to 241-N for comparing the bad address and the memory access address by 1 bit in response to the comparison signal COMP_EN. Redundancy control circuit of 1T-SRAM using electrical fuse programming. 11. The method of claim 10, wherein the first 1-bit bad address comparison circuit 241-1,
A fifth NMOS MN5 having a gate applied with the first bit IFAb [0] of the inverted bad address and having a drain connected to the fourth PMOS drain;
A sixth NMOS MN6 having a gate applied with the first bit IFA [0] of the bad address and having a drain connected to the fourth PMOS drain;
A seventh NMOS MN7 having a gate applied with the first bit MA [0] of the memory access address and having a drain connected to a source of the fifth NMOS;
An eighth NMOS MN8 having a gate applied with the first bit MAb [0] of the inverted memory access address and having a drain connected to a source of the sixth NMOS;
A ninth NMOS MN9 having a comparison signal COMP_EN applied to a gate, a ground voltage VSS applied to a source, and a drain thereof connected to a source of the seventh NMOS; And
An electrical fuse comprising a tenth NMOS (MN10) connected to a source of the eighth NMOS and a drain applied to a source and a ground voltage VSS to a source; Redundancy control circuit of 1T-SRAM using programming.

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