KR20120079501A - Non-volitile memory device - Google Patents

Abstract

PURPOSE: A nonvolatile memory device is provided to reduce parasitic capacitance by arranging floated bit lines around a bit line to which a program basis voltage is applied. CONSTITUTION: A first source selecting unit(103A) transmits a boosting voltage applied to a common source line to a first cell array in response to a first source selection signal. A first drain selecting unit(101A) disconnects the bit line from the first cell array in response to a first drain selection signal. A second source selecting unit disconnects the common source line from a second cell array. A second drain selecting unit(101B) transmits a program basis voltage to the second array through a second bit line in response to a second drain selection signal.

Description

Nonvolatile Memory Device {NON-VOLITILE MEMORY DEVICE}

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device that reduces interference between bit lines.

The flash memory device is an inactive memory device in which the input information is not erased even when the power is turned off during the information input. The flash memory device can freely input data. In other words, the flash memory device has both the advantages of ROM, which preserves stored data even when the power supply is cut off, and the RAM, which can freely input and output information.

The flash memory device was applied to the digital recorder (voice recorder) to form an initial market, and then, with the advent of MP3 players and digital cameras, a full-fledged consumption market was formed.

Flash memory devices are largely divided into NOR and NAND types, and NAND type leads in storage capacity, and NOR type leads in processing speed of information. The NOR type is mainly used as a storage medium for mobile phones, and the NAND type is used as a storage medium for MP3 players, smartphones, digital cameras and digital camcorders, and USB cards as portable storage devices.

Currently, one of the biggest issues with flash memory devices is reducing power consumption. In particular, when boosting an unselected bit line in a program operation, power consumption increases as the parasitic capacitance between the selected bit line and the unselected bit line increases. Here, the string connected to the unselected bit line performs an inhibit program operation.

The present invention provides a nonvolatile memory device that reduces parasitic capacitance between bit lines in a program operation.

The present invention provides a boosting voltage supply unit for supplying a boosting voltage to a common source line during an inhibit program operation, and a first source for transmitting the boosting voltage applied to the common source line to a first cell array in response to a first source selection signal. And a first drain selector which disconnects the first cell array and the bit line in response to a selector and a first drain select signal.

In order to reduce the parasitic capacitance between the bit lines, the present invention transmits a program basis voltage through the bit lines to the programmed cell arrays, and plots the bit lines to the prohibited cell arrays. Subsequently, the boosted voltage is transmitted to the cell array to be prohibited through the common source line. As a result, parasitic capacitance is reduced because the floating bit lines are arranged around the bit line to which the program basis voltage is applied.

1 is a circuit diagram illustrating a nonvolatile memory device.
FIG. 2 is a timing diagram illustrating an operation of the nonvolatile memory device of FIG. 1.
FIG. 3 is a diagram illustrating first to fourth bit lines in the nonvolatile memory device of FIG. 1.
4 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.
FIG. 5 is a circuit diagram illustrating the nonvolatile memory device of FIG. 4 in more detail.
FIG. 6 is a timing diagram illustrating an operation of the nonvolatile memory device of FIG. 5.
FIG. 7 is a diagram illustrating first to fourth bit lines in the nonvolatile memory device of FIG. 5.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

1 is a circuit diagram illustrating a nonvolatile memory device.

As shown in FIG. 1, a nonvolatile memory device includes a first string 1, a second string 2, a third string 3, a fourth string 4, a first controller 5, and a second string. The control unit 6 is included.

The first string 1 includes a first drain selector 11 connected in series, a first cell array 12 including a plurality of first memory cells MCA1 to MCA32, and a first source selector 13. It includes. The first drain selector 11 is connected to the first bit line BLO1, and the first source selector 13 is connected to the common source line CSL.

The second string 2 includes a second drain selector 21 connected in series, a second cell array 22 including a plurality of second memory cells MCB1 to MCB32, and a second source selector 23. It includes. The second drain selector 21 is connected to the second bit line BLE1, and the second source selector 23 is connected to the common source line CSL.

The third string 3 includes a third drain select unit 31 connected in series, a third cell array unit 32 including a plurality of third memory cells MCC1 to MCC32, and a third source select unit 33. It includes. The third drain selector 31 is connected to the third bit line BLO2, and the third source selector 33 is connected to the common source line CSL.

The fourth string 4 includes a fourth drain selector 41 connected in series, a fourth cell array 42 including a plurality of fourth memory cells MCD1 to MCD32, and a fourth source selector 43. It includes. The fourth drain selector 41 is connected to the fourth bit line BLE2, and the fourth source selector 43 is connected to the common source line CSL.

The first controller 5 controls the program, erase and read operations of the first and second cell arrays 12 and 22 and stores data. To this end, the first controller 5 includes a first precharge unit 51, a first selector 52, and a first page buffer 53. The first precharge unit 51 transfers the boosting voltage VBST to the selected bit line among the first and second bit lines BLO1 and BLE1 in response to the first and second precharge signals DICO1 and DICE1. . To this end, the first precharge unit 51 enables the first precharge unit 51A and the second precharge signal DICE1 to enable the response in response to the first precharge signal DICO1. 2, the precharge part 51B is included. The boosting voltage VBST may be at the level of the power supply voltage VEXT. The first selector 52 selectively connects the first page buffer 53 and the first and second bit lines BLO1 and BLE1. To this end, the first selector 52 may enable the first selector 52A and the second selector SELE1 in response to the first select signal SELO1. 52B). The first page buffer 53 transfers the program basis voltage VSS to the selected bit line among the first and second bit lines BLO1 and BLE1 and stores data during a read operation. The program base voltage VSS may be a ground voltage.

The second control unit 6 controls the program, erase and read operations of the third and fourth cell arrays 32 and 42 and stores data. To this end, the second controller 6 includes a second precharge unit 61, a second selector 62, and a second page buffer 63. The second precharge unit 61 transfers the boosting voltage VBST to the selected bit line among the third and fourth bit lines BLO2 and BLE2 in response to the third and fourth precharge signals DICO2 and DICE2. . To this end, the second precharge unit 61 may enable the third precharge unit 61A and the fourth precharge signal DICE2 to enable the response in response to the third precharge signal DICO2. Four pre-charge parts 61B are included. The boosting voltage VBST may be at the level of the power supply voltage VEXT. The second selector 62 selectively connects the second page buffer 63 and the third and fourth bit lines BLO2 and BLE2. To this end, the second selector 62 enables the third selector 62A to enable in response to the third select signal SELO2 and the fourth selector to enable in response to the fourth selector signal SELE2. 62B). The second page buffer 63 transfers the program basis voltage VSS to the selected bit line among the third and fourth bit lines BLO2 and BLE2, and stores data during a read operation. The program base voltage VSS may be a ground voltage.

The program operation of such a nonvolatile memory device will be described below.

FIG. 2 is a timing diagram illustrating an operation of the nonvolatile memory device of FIG. 1. It is assumed that the first memory cell MCA1 and the second memory cell MCC1 are programmed. Accordingly, the first bit line BLO1 and the third bit line BLO2 are selected, and the second bit line BLE1 and the fourth bit line BLE2 are unselected.

As shown in FIG. 2, the first and third precharge signals DICO1 and DICO2 maintain a low level at the time T1, and the second and fourth precharge signals DICE1 and DICE2 are activated to a high level. do. In addition, the first and third selection signals SELO1 and SELO2 are activated to a high level at the time T1, and the second and fourth selection signals SELE1 and SELE2 maintain a low level. Accordingly, the second and fourth bit lines BLE1 and BLE2 are charged with the boosting voltage VBST, and the first and third bit lines BLO1 and BLO2 are charged with the ground voltage VSS.

At the same time, the drain select signal DSL is activated at a high level, and the source select signal SSL is maintained at a low level. Accordingly, the first to fourth drain selection units 11 to 41 are enabled to respectively connect the first to fourth cell arrays 12 to 42 and the first to fourth bit lines BLO1, BLE1, BLO2, and BLE2. The first to fourth source selectors 13 to 43 are disabled to electrically disconnect each of the first to fourth cell arrays 12 to 42 and the common source line CSL. Therefore, the ground voltage VSS is supplied to the first and third cell arrays 12 and 32, and the boosting voltage VBST is supplied to the second and fourth cell arrays 22 and 42.

At the time T2, the program voltage VPGM is applied to the first word line WL1, and the pass voltage VPAS is applied to the remaining word lines WL2 to WL32. In this case, the first memory cell MCA1 connected to the selected first bit line BLO1 and the first word line WL1 and the second memory cell connected to the third bit line BLO2 and the first word line WL1. (MCC1) is programmed. Since the channels of the third memory cell MCB1 and the fourth memory cell MCD1 connected to the unselected second and fourth bit lines BLE1 and BLE2 and the first word line WL1 are boosted, the second and fourth bit lines BLE1 and BLE2 are respectively boosted. 4 FN tunneling does not occur between the floating gate of the memory cells MCB1 and MCD1 and the channel. That is, the second and fourth memory cells MCB1 and MCD1 are not programmed.

At the time T3, the supply of the program voltage VPGM and the pass voltage VPAS to the first word line WL1 and the second to 32nd word lines WL2 to WL32 are stopped. Thereafter, at time T4, the first and third select signals SELO1 and SELO2 and the second and fourth precharge signals DICE1 and DICE2 drain selection signals DSL are deactivated to a low level. As a result, the program operation for the first and second memory cells MCA1 and MCC1 and the forbidden program operation for the third and fourth memory cells MBC1 and MCD1 are completed. After that, the verification and program operation according to the ISPP method are performed crosswise.

3 is a diagram illustrating first through fourth bit lines BLO1, BLO2, BLE1, and BLE2 in the nonvolatile memory device of FIG. 1.

As shown in FIG. 3, the ground voltage VSS is applied to the first and third bit lines BLO1 and BLO2 in the program operation, and is applied to the second and fourth bit lines BLE1 and BLE2 in the inhibit program operation. Boosting voltage VBST is applied.

At this time, since the interval between the bit lines BLO1, BLO2, BLE1, and BLE2 is narrow, parasitic capacitance is applied between the bit lines BLO1, BLO2, BLE1, and BLE2 to which the ground voltage VSS and the boosting voltage VBST are applied. (C1) is generated. Such parasitic capacitance C1 causes a waste of power in the program operation.

4 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

As shown in FIG. 4, the nonvolatile memory device is disposed between the common source line CSL and the first cell array 102 and, during the inhibit program operation, the first cell array through the common source line CSL. Disposed between the first source selector 103, the first cell array 102, and the first bit line BL, which transmits the boosting voltage VBST to the first cell array 102, and the first cell array 102 during the inhibit program operation. ) And a first drain selector 101 to disconnect the first bit line BL. In addition, the nonvolatile memory device further includes a control unit 104 connected to the bit line BL and a boosting voltage supply unit 105 to supply the boosting voltage VBST to the common source line CSL.

FIG. 5 is a circuit diagram illustrating the nonvolatile memory device of FIG. 4 in more detail.

As illustrated in FIG. 5, the nonvolatile memory device may include a first string 1001, a second string 1002, a third string 1003, a fourth string 1004, a first controller 104A, and a second string. A control unit 104B and a boosting voltage supply unit 105 are included.

The first string 1001 includes a first drain selection unit 101A connected in series, a first cell array unit 102A including a plurality of first memory cells MCA1 to MCA32, and a first source selection unit 103A. It includes. The first drain selector 101A is enabled in response to the first drain select signal DSLO and is connected to the first bit line BLO1. The first source selector 103A is enabled in response to the first source select signal SSLO and is connected to the common source line CSL.

The second string 1002 includes a second drain select unit 101B connected in series, a second cell array unit 102B including a plurality of second memory cells MCB1 to MCB32, and a second source select unit 103B. It includes. The second drain selector 101B is enabled in response to the second drain select signal DSLE and is connected to the second bit line BLE1. The second source selector 103B is enabled in response to the second source select signal SSLE and is connected to the common source line CSL.

The third string 1003 includes a third drain select unit 101C connected in series, a third cell array unit 102C including a plurality of third memory cells MCC1 to MCC32, and a third source select unit 103C. It includes. The third drain selector 101C is enabled in response to the first drain select signal DSLO and is connected to the third bit line BLO2. The third source selector 103C is enabled in response to the first source select signal SSLO and is connected to the common source line CSL.

The fourth string 1004 includes a fourth drain selection unit 101D connected in series, a fourth cell array unit 102D including a plurality of fourth memory cells MCD1 to MCD32, and a fourth source selection unit 103D. It includes. The fourth drain selector 101D is enabled in response to the second drain select signal DSLE and is connected to the fourth bit line BLE2. The fourth source selector 103D is enabled in response to the second source select signal SSLE and is connected to the common source line CSL.

The first control unit 104A controls the program, erase and read operations of the first and second cell arrays 102A and 102B, and stores data. To this end, the first control unit 104A includes a first precharge unit 1041, a first selection unit 1042, and a first page buffer 1043. The first precharge unit 1041 transfers the precharge voltage VPREC to the first and second bit lines BLO1 and BLE1 in response to the first and second precharge signals DICO1 and DICE1. To this end, the first precharge unit 1041 may enable the first precharge unit 1041A and the second precharge signal DICE1 in response to the first precharge signal DICO1. Two pre-charging portions 1041B. The first selector 1042 selectively connects the first page buffer 1043 and the first and second bit lines BLO1 and BLE1. To this end, the first selector 1042 may enable the first selector 1042A and the second selector SELE1 in response to the first select signal SELO1. 1042B). The first page buffer 1043 transfers the program basis voltage VSS to the selected bit line among the first and second bit lines BLO1 and BLE1 and stores data during a read operation. The program base voltage VSS may be a ground voltage.

The second control unit 104B controls the program, erase and read operations of the third and fourth cell arrays 102C and 102D, and stores data. To this end, the second control unit 104B includes a second precharge unit 1044, a second selection unit 1045, and a second page buffer 1046. The second precharge unit 1044 transfers the precharge voltage VPREC to the third and fourth bit lines BLO2 and BLE2 in response to the third and fourth precharge signals DICO2 and DICE2. To this end, the second precharge unit 1044 enables the third precharge unit 1044A and the fourth precharge signal DICE2 to enable the response in response to the third precharge signal DICO2. 4 includes a precharge portion 1044B. The boosting voltage VBST may be at the level of the power supply voltage VEXT. The second selector 1045 selectively connects the second page buffer 1046 and the third and fourth bit lines BLO2 and BLE2. To this end, the second selector 1045 may enable the third selector 1045A and the fourth selector SELE2 in response to the third select signal SELO2. 1045B). The second page buffer 1046 transfers the program basis voltage VSS to a selected bit line among the third and fourth bit lines BLO2 and BLE2 and stores data during a read operation. The program base voltage VSS may be a ground voltage.

The boosting voltage supplier 105 supplies the boosting voltage VBST to the common source line CSL or discharges the common source line CSL in response to the supply control signal CONT. To this end, it includes a boosting voltage generator 1051, a discharge unit 1052, and an operation selector 1053. The operation selector 1053 supplies a first transfer gate T1 and a supply control that operate as a first transmitter for connecting the common source line CSL and the boosting voltage generator 1051 in response to a supply control signal CONT. The second transmission gate T2 acts as a second transmission unit for connecting the common source line CSL and the discharge unit 1052 in response to the signal CONT. Here, the supply control signal CONT is a signal that is activated to a high level when the nonvolatile memory device performs the inhibit program operation, and then is deactivated to a low level when the verify operation is performed.

FIG. 6 is a timing diagram illustrating an operation of the nonvolatile memory device of FIG. 5. It is assumed that the first memory cell MCA1 and the second memory cell MCC1 are programmed. Accordingly, the first bit line BLO1 and the third bit line BLO2 are selected, and the second bit line BLE1 and the fourth bit line BLE2 are unselected.

As shown in FIG. 6, the first and third precharge signals DICO1 and DICO2 maintain low levels at the time T1, and the second and fourth precharge signals DICE1 and DICE2 also maintain low levels. . In addition, the first and third selection signals SELO1 and SELO2 are activated to a high level at the time T1, and the second and fourth selection signals SELE1 and SELE2 maintain a low level. Accordingly, no voltage is supplied to the second and fourth bit lines BLE1 and BLE2, that is, a floating state, and the first and third bit lines BLO1 and BLO2 have a program basis voltage VSS. ) At the same time, the supply control signal CONT is activated to a high level so that the boosting voltage VBTS is supplied to the common source line CSL.

At the time T1, the first drain select signal DSLO maintains a low level, and the first source select signal SSLO is activated to a high level. In addition, the second drain select signal DSLE is activated to a high level, and the first source select signal SSLE maintains a low level. Accordingly, the first and third drain selectors 11 and 31 are enabled to electrically connect the first and third cell arrays 12 and 32 and the first and third bit lines BLO1 and BLO2, respectively. The first and third source selectors 13 and 33 are disabled to electrically disconnect the first and third cell arrays 12 and 32 and the common source line CSL, respectively. In addition, the second and fourth drain selectors 21 and 41 are disabled to electrically disconnect the second and fourth cell arrays 22 and 42 and the second and fourth bit lines BLE1 and BLE2, respectively. The second and fourth source selectors 23 and 43 are disabled to electrically connect the second and fourth cell arrays 22 and 42 and the common source line CSL, respectively. As a result, the program base voltage VSS is supplied to the first and third cell arrays 12 and 32, and the boosting voltage VBST is supplied to the second and fourth cell arrays 22 and 42.

At the time T2, the program voltage VPGM is applied to the first word line WL1, and the pass voltage VPAS is applied to the remaining word lines WL2 to WL32. In this case, the first memory cell MCA1 connected to the selected first bit line BLO1 and the first word line WL1 and the second memory cell connected to the third bit line BLO2 and the first word line WL1. (MCC1) is programmed. Channels of the third and fourth memory cells MCB1 and MCD1 connected to the unselected second and fourth bit lines BLE1 and BLE2 and the first word line WL1 are connected through the common source line CSL. Since boosted by the transferred boosting voltage VBST, FN tunneling does not occur between the floating gates of the second and fourth memory cells MCB1 and MCD1 and the channel. That is, the second and fourth memory cells MCB1 and MCD1 are not programmed.

At the time T3, the supply of the program voltage VPGM and the pass voltage VPAS to the first word line WL1 and the second to 32nd word lines WL2 to WL32 are stopped. Thereafter, at the time T4, the first and third select signals SELO1 and SELO2, the second and fourth precharge signals DICE1 and DICE2, the second drain select signal DSLE, and the first source select signal SSLO are provided. To low level. As a result, the program operation for the first and second memory cells MCA1 and MCC1 and the forbidden program operation for the third and fourth memory cells MBC1 and MCD1 are completed. After that, the verification and program operation according to the ISPP method are performed crosswise. During the verification operation, the supply control signal CONT is inactivated to a low level to connect the common source line CSL and the discharge unit 1052. Therefore, a current path is generated between the first to fourth strings 1001 to 1004 and the common source line CSL during the verification operation.

FIG. 7 is a diagram illustrating first to fourth bit lines BLO1, BLO2, BLE1, and BLE2 in the nonvolatile memory device of FIG. 5.

As shown in FIG. 7, in the program operation, the ground voltage VSS is applied to the first and third bit lines BLO1 and BLO2, and the second and fourth bit lines BLE1 and BLE2 are floated. Accordingly, the parasitic capacitance C2 is generated between the first bit line BLO1 and the third bit line BLO2, and the parasitic capacitance C2 is small because the distance between the two bit lines BLO1 and BLO2 is far.

As described above, the nonvolatile memory device in accordance with an embodiment of the present invention plots a bit line for inhibiting program operation in order to reduce parasitic capacitance between bit lines. In addition, the boosting voltage VBST is supplied to the string connected to the bit line operating the prohibited program through the common source line CSL. As a result, while the prohibition program operation on the string is normally performed, the parasitic capacitance between the bit lines is reduced, thereby reducing power waste of the nonvolatile memory device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. Will be apparent to those of ordinary skill in the art. For example, the logic gate and the transistor illustrated in the above embodiment may be implemented in different positions and types depending on the polarity of the input signal.

1001: first string 1002: second string
1003: third string 1004: fourth string
104A: first control unit 104B: second control unit
105: boosting voltage supply unit

Claims (7)

A boosting voltage supply unit supplying a boosting voltage to a common source line during an inhibit program operation;
A first source selector configured to transfer the boosting voltage applied to the common source line to a first cell array in response to a first source select signal; And
A first drain selector which disconnects the first cell array and the bit line in response to a first drain select signal
Nonvolatile memory device comprising a.
The method of claim 1,
A second source selector which disconnects a second cell array and the common source line in response to a second source select signal; And
And a second drain select unit configured to transfer a program initial voltage to the second cell array through a second bit line in response to a second drain select signal.
The method of claim 2,
And a controller configured to transfer the program base voltage to the second bit line and store data read in connection with the first and second bit lines.
The method of claim 3, wherein
And the first bit line is disconnected from the controller and is floated during the inhibit program operation.
The method of claim 1,
And the boosting voltage supply unit discharges the common source line during a verify operation.
The method of claim 5, wherein
The boosting voltage supply unit
A first transmitter transferring the boosting voltage to the common source line in response to a supply control signal; And
And a second transfer unit connecting the common source line and the discharge unit in response to the supply control signal.
The method according to claim 6,
And the supply control signal is a signal that is activated when the inhibit program operation is performed and then deactivated when the verification operation is performed.

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