KR20120076968A - Flexible printed circuit board - Google Patents

Abstract

PURPOSE: A flexible printed circuit board is provided to block an outflow of EMI(Electro Magnetic Interference) by forming a ground reinforcement structure on a first body portion of the flexible printed circuit board. CONSTITUTION: A second body portion(120) is extended from a first body portion(110). The first body portion comprises a signal wiring portion, a power wiring portion, a first ground layer, and a second ground layer. The first ground layer and the second ground layer are located on both sides of the signal wiring portion and the power wiring portion. A connector interlinking portion(140) is formed at one side of the second body portion. The connector interlinking portion is formed at one side of the first body portion. Line width of the signal wiring portion formed on the first body portion, the second body portion, the connector interlinking portion, and an interlinking portion is different.

Description

Flexible printed circuit board

The present invention relates to a flexible printed circuit board that can suppress electromagnetic interference (EMI) and electrostatic discharge (ESD).

Liquid crystal display devices (LCDs), which are used for TVs and monitors due to their high contrast ratio and are advantageous for displaying moving images, are characterized by optical anisotropy and polarization of liquid crystals. The principle of image implementation by

Such a liquid crystal display is an essential component of a liquid crystal panel bonded through a liquid crystal layer between two side-by-side substrates, and realizes a difference in transmittance by changing an arrangement direction of liquid crystal molecules with an electric field in the liquid crystal panel. do.

Such a liquid crystal display is usually driven by providing a driving signal necessary for driving the liquid crystal panel to the liquid crystal panel through a control board which is a printed circuit board (PCB). In this case, the electrical connection between the control board and the liquid crystal panel may be made by a flexible printed circuit board (FPCB, hereinafter referred to as "FPCB").

On the other hand, in the liquid crystal display device, not only FPCB but also control board are generating EMI (Electromagnetic interference) and ESD (ElectroStatic Discharge). Especially, FPCB generates a lot of EMI and ESD at the part connected to PCB on the liquid crystal panel side. .

As such, when EMI and ESD occur, there is a concern that the function of the liquid crystal display device may be degraded. In recent years, in the manufacture of the liquid crystal display device, suppressing EMI and ESD has become an important factor in improving the function of the display device. .

Conventionally, in order to reduce EMI and ESD, a technique of absorbing noise by grounding the electrical and electronic equipment (GND) has been introduced, but there is a problem that it is difficult to suppress the occurrence of EMI and ESD because it cannot be easily grounded.

In addition, the general FPCB causes a problem of degrading the performance of the product due to signal distortion caused by the impedance difference.

The present invention is to solve the above problems, it is an object to suppress the occurrence of EMI and ESD of the FPCB to prevent malfunction.

In addition, an object of the present invention is to provide an FPCB having a predetermined structure for impedance matching. Through this, the purpose is to improve the signal transmission efficiency of the FPCB.

In order to achieve the above object, the present invention provides a first body portion and a second body portion extending from the first body portion, a connector connecting portion formed on one side of the second body portion, and one side of the first body portion. In a flexible printed circuit board comprising a connection portion formed in the first printed circuit board, the first body portion includes a signal wiring portion, a power wiring portion, and first and second ground layers on both sides of the signal wiring portion and the power wiring portion. Line widths of the signal wires formed in the first and second body parts, the connector connection part, and the connection part are different from each other, and the spacing between the signal wire and the ground wire is also different from each other so that impedance is matched. Provided are a flexible printed circuit board.

In this case, the plurality of signal wires of the first body part have a line width of 70 μm, respectively, and a distance between the plurality of signal wires and the plurality of ground wires is maintained at 150 μm, and the second body part and the The plurality of signal wires of the connector connection portion each have a line width of 70 μm, and the spacing between the plurality of signal wires and the plurality of ground wires is maintained at 70 μm, and the plurality of signal wires of the connection portion have a wire width of 230 μm, respectively. And a distance between the plurality of signal wires and the plurality of ground wires is 70 μm, and the first body part forms a first power wire part above the first base layer and the first base layer. A copper foil layer is formed, and a second copper foil layer for forming the signal wiring portion is formed below the first base layer, and the first ground layer is formed on the first copper foil layer, and the second The resin layer is formed on the second copper layer.

In addition, a power supply wiring and the ground wiring are formed on the first copper foil layer, and the signal wiring is formed on the second copper foil layer, and between the first copper foil layer and the first ground layer, a first plating layer and a first wiring layer. A first coverlay film, a first bonding sheet, a second base layer and a plurality of adhesive layers are interposed.

A second plating layer, a second coverlay film, a second bonding sheet, a third base layer, and a plurality of adhesive layers are interposed between the second copper foil layer and the second ground layer, and an upper portion of the first ground layer. A first solder resin layer is formed thereon, and a second solder resin layer is formed on the second ground layer.

In addition, the second body portion and the connector connecting portion may have first and second copper foil layers formed on both sides of the first base layer and the first base layer, and the first plating layer and the first copper foil layer formed on the first copper foil layer. A coverlay film is formed, and a second plating layer and a second coverlay film are formed below the second copper foil layer, and a portion of the first coverlay film of the connector connection part is opened to expose the first plating layer. do.

In this case, a reinforcing plate is formed on an upper portion of the second coverlay film of the connector connection portion, and the connection portion is formed with a first copper foil layer on one side of the first base layer and the first base layer, and the upper portion of the first copper foil layer. The first plating layer and the first coverlay film are formed thereon.

A portion of the first coverlay film is opened to expose the first plating layer.

As described above, according to the present invention, by further forming a ground reinforcing structure in the first body portion of the FPCB, where EMI and ESD are most generated, EMI and ESD generated from the FPCB can be shielded from leaking to the outside. It works. Through this, there is an effect that can prevent the problem that the function of the liquid crystal display device is degraded through EMI and ESD.

In addition, the FPCB of the present invention has the effect that the ground reinforcement structure is formed only in response to the region where EMI and ESD are most generated, thereby maintaining the bending property, which is an inherent characteristic of the FPCB.

In addition, the FPCB of the present invention sets impedance matching by differently setting the width of the high-speed signal wiring and the interval between the high-speed signal wiring and the ground wiring and the width of the power wiring and the distance between the power wiring and the ground wiring for each region. The effect is to be satisfied.

Through this, there is an effect that can prevent the problem of lowering the performance of the product due to signal distortion due to the impedance difference.

1 is a plan view schematically showing the appearance of the FPCB according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of the laminated structure of the FPCB of FIG.
3A to 3C are enlarged plan views showing a part of wiring of an FPCB according to an embodiment of the present invention.
4A to 4C are simulation results of FIGS. 3A to 3C.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

1 is a plan view schematically showing the appearance of an FPCB according to an embodiment of the present invention.

As illustrated, the FPCB 100 includes the body parts 110 and 120 and the wiring part 150 formed on one surface of the body parts 110 and 120, the connection parts 130 and 140, the device part (not shown), and the circuit part. (Not shown) and a connector (not shown).

In detail, each of the body parts 110 and 120 forms a wiring part 150, a connector connection part 140, a circuit part (not shown), and an element connection part (not shown), and an element connection part (not shown). It is for supporting an element (not shown) mounted on, and is formed in a film form by receiving a resin containing polyimide or PET.

In this case, the body parts 110 and 120 may include an out lead bonding (OLB) connection part 130, a circuit part (not shown), and a first body part 110 and a first body part (not shown) to form an element connection part (not shown). It is formed to extend on one side of the 110 and may be made of a second body portion 120 for forming the connector connecting portion 140.

The wiring part 150 is for connecting the connector connection part 140 and the OLB connection part 130 and may be formed on one surface of the body parts 110 and 120. In this case, the wiring unit 150 may include a signal wiring unit 151 and a power wiring unit 153.

The signal wiring unit 151 transfers a signal applied to the connector connecting unit 140 and may be formed of a plurality of signal wirings 155. The power supply wiring 153 is for applying power and may include a plurality of power wirings 157 and a plurality of ground wirings 159a, 159b, and 159c.

The signal wires 155, the power wires 157, and the ground wires 159a, 159b, and 159c are connected to the OLB of the first body part 110 at the connector connection part 140 formed at one end of the second body part 120. It extends to the connecting portion 130 is preferably formed so as not to overlap and cross each other.

At this time, the power wiring 153 is formed between the signal wiring 151 is effective in the space utilization of the FPCB 100. That is, the ground wirings 159a, 159b, and 159c are formed between the signal wirings 155.

In addition, the connection parts 130 and 140 are for connecting the wiring part 150 with an element (not shown), an external driving element (not shown), and a connector (not shown), and an element connection part (not shown). The OLB connector 130 and the connector connector 140 are included.

Here, the device connection unit (not shown) is a place for mounting the device (not shown), it may be connected to the OLB connection unit 130. In this case, the device connection part (not shown) may be formed by etching the protective layer in the region connected with the device and exposing the copper foil inside thereof to the outside.

In addition, the element connection unit (not shown), in forming the signal wiring unit 151, the first body portion spaced apart from the second body portion 120 as much as possible to secure the maximum space in the body portion (110, 120) It is preferable to form in the one end region of the (110).

That is, the device connection part (not shown) may be disposed to form the signal wiring part 151 between the device connection part (not shown) and the second body part 120.

In this case, the device may include various circuit elements such as a dual-inline package (DIP), a PGA package, a chip scale package (CSP), a through-hole array connector, and the like.

In the device connection part (not shown), a plurality of grid patterns pins (not shown) are formed in order to mount the above-described various circuit devices.

The OLB connector 130 connects the FPCB 100 to a liquid crystal panel (not shown) of the LCD. The OLB connector 130 includes a plurality of input / output pads 131 and a plurality of input / output pads 131. ) May be formed by etching the protective layer and exposing the copper foil inside thereof to the outside.

In addition, the connector connection unit 140 is for mounting and electrically connecting a connector (not shown), and external drive elements such as the FPCB 100 and the printed circuit board (PCB) or the system through the connector connection unit 140. Electrical connection).

In addition, the connector connection unit 140 is for mounting an electric connector by mounting a connector (not shown), and the power wiring connection unit connected to the signal wiring connection unit 141 and the power wiring unit 153 connected to the signal wiring unit 151. 143 may include.

In this case, the connector connecting portion 140 may etch a portion of the protective layer of the second body portion 120 so that a pin (not shown) formed in the connector (not shown) may be connected to the connector connecting portion 140, and the copper foil therein may be removed. A plurality of contact pads 145 formed by exposing to the outside are configured.

The circuit unit (not shown) is embedded in the first and second body parts 110 and 120 to be connected to the wiring unit 150. The circuit unit (not shown) includes a resistor or a capacitor.

The FPCB 100 according to the embodiment of the present invention having the above-described structure can effectively suppress the generation of EMI and ESD, can match the impedance, and improve the performance of the product by signal distortion due to the impedance difference. The problem of deterioration can be prevented.

This will be described in detail with reference to FIG. 2 below.

FIG. 2 is a cross-sectional view schematically illustrating a laminated structure of the FPCB of FIG. 1.

As shown, the FPCB 100 can be largely divided into 4 areas, where 1 area is an area in which an OLB connection portion (130 in FIG. 1) of the FPCB (100 in FIG. 1) is formed, and a second area is an FPCB. The first body part (110 in FIG. 1) of FIG. 1, the third area may be defined by dividing the second body part (120 in FIG. 1), and the fourth area into the connector connection part (140 in FIG. 1). have.

Looking at each of these regions in detail, the first region, the third region, and the fourth region are largely composed of one layer. First, the first region is formed on the first base layer 201a. 210a is attached through the adhesive 203a, a first plating layer 211a is formed on the first copper foil layer 210a, and a first coverlay film 215a is formed on the first plating layer 211a. It is attached via

A power wiring part 153 of FIG. 1 is formed in the first copper foil layer 210a.

In this case, the first base layer 201a is made of a resin-based material such as polyimide or polyester.

A portion of the first coverlay film 215a of the first region is opened to expose the lower first plating layer 211a, and a second coverlay is disposed on the rear surface of the first base layer 201a of the first region. The film 215b is attached through the adhesive 213b.

The first region is an OLB connector (130 of FIG. 1) in which a plurality of input / output wirings (131 of FIG. 1) of the FPCB 100 are formed, and the liquid crystal panel of the liquid crystal display device is connected through the OLB connector (130 of FIG. 1). Not shown) and the FPCB 100 is electrically connected.

The third and fourth regions are the second body portion 120 (FIG. 1) and the connector connection portion (140 of FIG. 1) for forming the connector connection portion (140 of FIG. 1) of the FPCB 100, respectively. In the fourth region, first and second copper foil layers 210a and 210b are formed on both sides of the first base layer 201a to form a circuit portion (not shown) and a wiring portion (150 in FIG. 1).

In this case, the first copper foil layer 210a is formed to extend from the first copper foil layer 210a of the first region, and the power wiring part (153 of FIG. 1) is provided on the first copper foil layer 210a of the third and fourth regions. ) Is formed, and a circuit portion (not shown) and a signal wiring portion (151 of FIG. 1) are formed in the second copper foil layer 210b.

First and second plating layers 211a and 211b are formed on each of the first and second copper foil layers 210a and 210b, and first and second covers are disposed on the first and second plating layers 211a and 211b, respectively. The ray films 215a and 215b are attached through the adhesive layers 213a and 213c.

Here, a part of the first coverlay film 215a is also opened in the fourth region to expose the lower first plating layer 211a.

In addition, a rear surface of the second coverlay film 215a in the fourth region in which the connector (not shown) is mounted may be prevented from being damaged and the connector (not shown) may be connected to an external driving device (not shown). The reinforcing plate 260 is formed with the adhesive layer 213d therebetween to facilitate fastening.

The second region is the first body portion 110 of the FPCB 100 (110 in FIG. 1), and the FPCB 100 of the present invention has the second region largely in the first to third layers A, B, and C. Characterized in that to be made.

In the first layer A, first and second copper foil layers 210a and 210b are formed on both sides of the first base layer 201a to form a circuit portion (not shown) and a wiring portion (150 in FIG. 1). have.

Here, each of the first and second copper foil layers 210a and 210 is attached to both sides of the first base layer 201a through the adhesive layers 203a and 203b, and the first copper foil layer 210a is formed of the first region. It is comprised extending from the 1 copper foil layer 210a, and the 2nd copper foil layer 210b is comprised extending from the 2nd copper foil layer 210b of a 3rd and 4th area | region.

In the first and second copper foil layers 210a and 210b, after the dry film is laminated, a circuit part (not shown) and a wiring part (not shown) complex to the first and second copper foil layers 210a and 210b through exposure and etching. 150 of 1 is formed, and a power wiring part 153 of FIG. 1 is formed in the first copper foil layer 210a. The power wiring part 153 of FIG. 1 includes a plurality of power wirings 157 of FIG. Ground wiring (159a in FIG. 1).

In addition, a circuit portion (not shown) and a signal wiring portion (151 in FIG. 1) are formed in the second copper foil layer 210b, and the circuit portion (not shown) is formed of a resistor and a capacitor, and the like. The signal wiring (155 in FIG. 1) of 151 includes high speed signal wiring formed between DDR Clock, USB, HDMI, and the like.

Here, the first base layer 201a and the first and second copper foil layers 210a and 210b form a core layer.

In particular, it is formed to satisfy the impedance matching of the high-speed signal wiring (155 of FIG. 1) and the power wiring (157 of FIG. 1), which is a serial interface of the FPCB 100 of the present invention. do.

That is, the impedance of each region of the FPCB 100 is matched, so that the signal transmission efficiency is high and the width of the signal wiring (155 of FIG. 1) and the power wiring (157 of FIG. 1) can be minimized to minimize the occurrence of EMI and ESD. And a gap between the signal wiring (155 of FIG. 1) and the power wiring (157 of FIG. 1) and the ground wiring (159a, 129b, and 159c of FIG. 1).

Through this, it is possible to prevent the problem of degrading the performance of the product due to signal distortion due to the impedance difference. We will discuss this in more detail later.

In this case, in the FPCB 100 of the present invention, the signal wiring unit 151 of FIG. 1 and the power wiring unit 153 of FIG. 1 are formed on different layers, and thus, the structure of the complex power wiring unit 153 of FIG. EMI and ESD can be minimized.

In addition, the first and second copper foil layers 210a and 210b may each have a thickness of 12 μm, and the first base layer 201a between the first and second copper foil layers 210a and 210b may have a thickness of 25 μm. The thickness of the adhesive layers 203a and 203b interposed between the first base layer 201a and the first and second copper foil layers 210a and 210b is preferably 10 μm, respectively.

Accordingly, the distance between the first and second copper foil layers 210a and 210b is maintained at 45 μm, so that the signal and the power supply wirings 153 of FIG. 1 are formed in the first and second copper foil layers 210a and 210b, respectively. It is possible to prevent the occurrence of electrical interference between the wiring portions 151 of FIG.

First and second plating layers 211a and 211b are formed on each of the first and second copper foil layers 210a and 210b, and first and second covers are disposed on the first and second plating layers 211a and 211b, respectively. The ray films 215a and 215b are attached through the adhesive layers 213a and 213c.

In this case, the first and second plating layers 211a and 211b are formed to improve the corrosion resistance and the wear resistance of the first and second copper foil layers 210a and 210b.

Here, the first body part (110 in FIG. 1) is composed of the widest area in the FPCB 200, and the first body part (110 in FIG. 1) has the most complicated circuit part (not shown) and wiring part (Fig. 1). 150 of 1 is formed. Thus, EMI and ESD are most likely to occur in the first body part 110 of FIG. 1.

In particular, the second copper foil layer 210b formed on the first body part 110 (in FIG. 1) may be formed of high-speed signal wiring (155 in FIG. 1) and resistors and capacitors formed between DDR clock, USB, and HDMI. By including a circuit unit (not shown), the EMI and the ESD is most generated in the second copper foil layer 210b.

Therefore, the FPCB 100 of the present invention is characterized in that it further comprises a ground reinforcing structure in the first body portion (110 of FIG. 1) where EMI and ESD occur most.

That is, the second and third layers B and C having a ground reinforcing structure are further formed on both sides of the first layer A of the second region corresponding to the first body part 110 of FIG. It is characterized in that the occurrence of EMI and ESD of the first body portion (110 in FIG. 1) is minimized.

In more detail, the second layer B is positioned with the first bonding sheet 240a interposed on the first layer A, and the first layer A in which the second layer B is located. The third side C is further provided with the second bonding sheet 240b interposed therebetween.

At this time, the first and second bonding sheets 240a and 240b are formed of the first layer A and the first layer A, which are required to be bonded to each other with heat and pressure applied by the press during the bonding operation by the heat press. As a kind of auxiliary sheet used to indirectly and uniformly indirectly transfer to the second and third layers B and C, it is also called a thermal conductive sheet or a release sheet.

The first and second bonding sheets 240a and 240b may be polytetrafluoroethylene (PTFE) films called Teflon, or may be made of silicone resin.

As such, the ground wires (159b and 159c of FIG. 1) are respectively attached to the second and third layers B and C attached to both sides of the first layer A through the first and second bonding sheets 240a and 240b. That is, the second layer (B) is a third copper foil layer 210c is attached to the second base layer 201b through the adhesive 203c, and the upper portion of the third copper foil layer 210c The third plating layer 211c is stacked.

Here, an element connecting portion (not shown) and a second ground wiring (159b of FIG. 1) are formed on the third copper foil layer 210c, and a second ground wiring (159b of FIG. 1) is formed on the third plating layer 211c. The first solder resin layer 250a is formed to cover the one surface of the FPCB 100 while protecting the insulation.

In this case, the device connection part (not shown) is a pin (not shown) of a plurality of grid patterns for connecting various circuit elements and wiring parts (150 of FIG. 1) mounted on the FPCB 100. A portion of the resin layer 250a is opened to expose the lower third plating layer 211c.

In the third layer C, a fourth copper foil layer 210d is attached to the third base layer 201c through an adhesive 203d, and a fourth plating layer (210) is disposed on the third copper foil layer 210d. 211d) are stacked.

Here, the third ground wire (159c of FIG. 1) is formed on the fourth copper foil layer 210d, and the FPCB 100 is protected while the third ground wire (159c of FIG. 1) is protected on the fourth plating layer 211d. The second solder resin layer 250b is formed to cover one surface of the substrate.

The first and second solder resin layers 250a and 250b are made of polyimide resin.

As described above, the FPCB 100 according to the present invention has a second and a third ground wiring line above and below the second copper foil layer 210b in the first region of the FPCB 100 where EMI and ESD are most likely to occur. By placing the third and fourth copper foil layers 210c and 210d on which the first and second copper foil layers 159b and 159c are formed, the EMI and the ESD generated in the second copper foil layer 210b may be shielded from the outside. .

That is, EMI and ESD leaked to the upper side of the second copper foil layer 210b are the first ground wire (159a in FIG. 1) of the first copper foil layer 210a or the second ground wire (the third copper foil layer 210c). 1 through 159b of FIG. 1, and EMI and ESD flowing out to the lower side of the second copper foil layer 210b are shielded through the third ground wiring (159c of FIG. 1) of the fourth copper foil layer 210d. do.

Therefore, the circuit part (not shown) made of high-speed signal wiring (155 of FIG. 1) and resistors and capacitors, which generate the most EMI and ESD, is connected to the upper and lower parts through ground wiring (159b and 159c of FIG. 1). Shielded.

In addition, the first copper foil layer 210a in which the power supply wiring part 153 of FIG. 1 is formed, and the EMI and ESD leaked to the upper side of the first copper foil layer 210a are connected to the second ground wire of the third copper foil layer 210c. Shielded through 159b of FIG. 1, EMI and ESD leaked to the lower side of the first copper foil layer 210a are shielded through the third ground line (159c of FIG. 1) of the fourth copper foil layer 210d. .

Therefore, the FPCB 100 of the present invention can shield EMI and ESD generated from the FPCB 100 from leaking to the outside. Through this, it is possible to prevent the problem that the function of the liquid crystal display device is degraded through EMI and ESD.

In addition, the FPCB 100 of the present invention allows the signal wiring unit 151 of FIG. 1 and the power wiring unit 153 of FIG. 1 to be formed on different layers, thereby allowing the complex power wiring unit 153 of FIG. It is also possible to minimize the generation of EMI and ESD due to the structure. In addition, the signal wiring unit 151 of FIG. 1 and the power wiring unit 153 of FIG. 1 maintain a constant distance, thereby causing electrical interference between the power wiring unit 153 of FIG. 1 and the signal wiring unit 151 of FIG. This can also be prevented.

In particular, the FPCB 100 of the present invention allows the ground reinforcing structure to be formed only in response to the second region where EMI and ESD are most likely to occur, so that the first region, the third region, and the fourth region are inherent to the FPCB 100. It is possible to maintain the bending property as it is.

That is, the FPCB 100 of the present invention can shield EMI and ESD from leaking through the ground reinforcing structure, and at the same time, bendability, which is an inherent characteristic of the FPCB 100, can be maintained.

In addition, the FPCB 100 of the present invention is formed to satisfy the impedance matching of the high speed signal wiring (155 of FIG. 1) and the power wiring (157 of FIG. 1), which is a serial interface such as MIPI wiring. It is characterized by.

Through this, it is possible to prevent the problem of degrading the performance of the product due to signal distortion due to the impedance difference.

3A to 3C are enlarged plan views showing a part of wiring of an FPCB according to an embodiment of the present invention, and FIGS. 4A to 4C are simulation results of FIGS. 3A to 3C.

Prior to the description, impedance matching is to prevent signal loss by reducing the reflection caused by the difference in impedance between two different connection stages when connecting different devices.

The FPCB (100 in FIG. 2) matches impedances of the high speed signal line 155 and the power line 157, which are serial interfaces, thereby preventing a problem of degrading the performance of the product due to signal distortion due to the impedance difference. Can be.

The power transmission characteristics of electromagnetic energy are best when the impedance is 50Ω, and the high-speed signal wiring (155 in FIG. 1) and the power wiring (157 in FIG. 1), which are serial interfaces such as MIPI wiring, are best when the impedance is 100Ω. good.

Accordingly, the FPCB (100 in FIG. 2) of the present invention has the widths d2 and d3 of the high speed signal wiring 155 and the spacings D2 and D3 between the high speed signal wiring 155 and the ground wiring 159 for each region. By setting the width d1 of the wiring 157 and the distance D1 between the power supply wiring 157 and the ground wiring 159 differently, the impedance of the entire FPCB (100 in FIG. 2) is maintained to be 100? It features.

The high speed signal wiring 155 extends from the OLB connection portion 130 of the FPCB (100 of FIG. 2) to the second body portion (120 of FIG. 1) via the first body portion (110 of FIG. 1), That is, it is formed over the first region, the second region and the third region.

In this case, as shown in FIG. 3A, the power line 155 formed in the first region corresponding to the OLB connection unit 130 (see FIG. 1) maintains the line width d1 of 230 μm, and the power line 155 and the ground. The interval D1 between the wirings 159 is maintained at 70 µm, so that the impedance of the first region is maintained at 100 Ω.

As shown in FIG. 3B, the high-speed signal wiring 155 formed in the second area corresponding to the first body part 110 (in FIG. 1) has a line width d2 of 70 μm, and the high-speed signal wiring ( The distance D2 between the 155 and the ground wiring 159 is maintained at 150 μm, thereby maintaining the impedance of the second region at 100 Ω.

In addition, as shown in FIG. 3C, the high-speed signal wiring 155 formed in the third and fourth regions corresponding to the second body portion 120 (FIG. 1) and the connector connection portion (140 of FIG. 1) has a line width d3. ) Maintains 230 占 퐉, and the distance D3 between the high-speed signal wiring 155 and the ground wiring 159 is maintained at 70 占 퐉, thereby maintaining the impedance of the third and fourth regions at 100?.

Thus, the FPCB (100 in FIG. 1) satisfies impedance matching. Through this, it is possible to prevent the problem of degrading the performance of the product due to signal distortion due to the impedance difference.

Figure 4a is to form a copper foil layer on the base layer, in the state that the coverlay film is attached to the upper portion of the copper foil layer through the adhesive layer, by measuring the impedance by varying the width and the interval between the power wiring and ground wiring to the copper foil layer As a result of the simulation, when the line width of the power supply wiring is formed to 230 mu m, and the distance between the power supply wiring and the ground wiring is maintained at 70 mu m, it can be seen that the impedance is maintained at 97.84 Ω.

Accordingly, the FPCB (100 in FIG. 2) of the present invention maintains the line width d1 of the power wiring 155 in the first region where the first copper foil layer (210a in FIG. The distance D1 between the 155 and the ground wiring 159 is maintained at 70 占 퐉, so that the impedance of the first region can be maintained at 100?.

 4B shows first and second copper foil layers formed on both sides of the base layer with an adhesive layer interposed therebetween, a third copper foil layer formed on an upper portion of the first copper foil layer, and a coverlay film below the second copper foil layer. After attaching the adhesive through the adhesive, in the state where the fourth copper foil layer is formed on the four sides of the coverlay film, the impedance is increased by varying the width of the high speed signal wiring and the distance between the high speed signal wiring and the ground wiring on the second copper foil layer. It is the measured simulation result.

Checking the simulation results, it can be seen that the impedance is maintained at 93.65Ω when the line width of the high speed signal wiring is formed to 70 μm and the interval between the high speed signal wiring and the ground wiring is maintained to 150 μm.

Therefore, in the FPCB (100 of FIG. 2) of the present invention, the first and second copper foil layers 210a and 210b of FIG. 2 are formed on both sides of the first base layer 201a of FIG. A second copper foil layer (210c in FIG. 2) is formed on the upper portion of 210a of FIG. 2, and a fourth copper foil layer (210d in FIG. 2) is formed on the second copper foil layer (210b of FIG. 2). The line width d2 of the high speed signal wiring 155 in the area is maintained at 70 占 퐉, and the distance D2 between the high speed signal wiring 155 and the ground wiring 159 is maintained at 150 占 퐉. The impedance can be maintained at 100Ω.

In addition, in FIG. 4C, the first and second copper foil layers are formed on both sides of the base layer with the adhesive layer interposed therebetween, and the second copper foil layer is formed on the first copper foil layer with the coverlay film attached through the adhesive layer. The impedance is measured by varying the width of the high-speed signal wiring and the distance between the high-speed signal wiring and the ground wiring.

Checking the simulation result, it can be seen that the impedance is maintained at 97.62Ω when the line width of the high speed signal wiring is formed to 70 mu m and the distance between the high speed signal wiring and the ground wiring is kept to 70 mu m.

Accordingly, in the FPCB (100 in FIG. 2) of the present invention, the third and fourth regions in which the first and second copper foil layers 210a and 210b of FIG. 2 are formed on both sides of the first base layer 201a of FIG. By maintaining the line width d3 of the high speed signal wiring 155 at 70 占 퐉, and maintaining the distance D3 between the high speed signal wiring 155 and the ground wiring 159 at 70 占 퐉, the third and fourth The impedance of the region can be maintained at 100Ω.

As described above, the FPCB (100 in FIG. 2) of the present invention further forms a ground reinforcing structure in the first body portion (110 in FIG. 1) where EMI and ESD are most generated, thereby increasing the FPCB (100 in FIG. 2). EMI and ESD can be shielded from leaking to the outside. Through this, it is possible to prevent the problem that the function of the liquid crystal display device is degraded through EMI and ESD.

In addition, the FPCB (100 of FIG. 2) of the present invention is to ensure that the ground reinforcing structure is formed only corresponding to the region where the most EMI and ESD is generated, so as to maintain the bending property which is inherent to the FPCB (100 of FIG. 2) as it is can do.

In addition, the FPCB (100 in FIG. 2) of the present invention has the widths d2 and d3 of the high speed signal wiring 155 and the intervals D2 and D3 between the high speed signal wiring 155 and the ground wiring 159 for each region. By setting the width d1 of the power supply wiring 157 and the interval D1 between the power supply wiring 157 and the ground wiring 159 differently, impedance matching is satisfied.

Through this, it is possible to prevent the problem of degrading the performance of the product due to signal distortion due to the impedance difference.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

201a, 201b, 201c: first to third base layers
203a, 203b, 203c, 203d, 213a, 213b, 213c, 213d: adhesive layer
210a, 210b, 210c, 210d: first to fourth copper foil layers
211a, 211b, 211c, and 211d: first to fourth plating layers
215a, 215b: first and second coverlay films
240a, 240b: first and second bonding sheets, 250a, 250b: first and second solder resin layers
260: reinforcement plate

Claims (12)

In a flexible printed circuit board comprising a first body portion, a second body portion extending from the first body portion, a connector connecting portion formed on one side of the second body portion, and a connecting portion formed on one side of the first body portion. ,
The first body portion includes a signal wiring portion, a power wiring portion, and first and second ground layers on both sides of the signal wiring portion and the power wiring portion,
Line widths of the signal wires formed in the first and second body parts, the connector connection part, and the connection part are different from each other, and a gap between the signal wire and the ground wire is also different from each other so that impedance is matched. Flexible printed circuit board).
The method of claim 1,
The plurality of signal wires of the first body part have a line width of 70 μm, respectively, and the distance between the plurality of signal wires and the plurality of ground wires is 150 μm, and the second body part and the connector connection part are maintained. The plurality of signal wires of each of the line width of 70㎛, the interval between the plurality of signal wires and a plurality of ground wiring to maintain a 70㎛, the plurality of signal wiring of the connection portion each made of a line width of 230㎛ And a spacing between the plurality of signal wires and the plurality of ground wires is 70 μm.
The method of claim 1,
The first body part is formed with a first copper foil layer forming the power supply wiring portion above the first base layer and the first base layer, and a second copper foil layer forming the signal wiring portion below the first base layer. Is formed, wherein the first ground layer is formed on the first copper foil layer, and the second ground layer is formed on the second copper foil layer.
The method of claim 3, wherein
The power supply wiring and the ground wiring are formed on the first copper foil layer, and the signal wiring is formed on the second copper foil layer.
The method of claim 3, wherein
A flexible printed circuit board having a first plating layer, a first coverlay film, a first bonding sheet, a second base layer, and a plurality of adhesive layers interposed between the first copper foil layer and the first ground layer.
The method of claim 3, wherein
A flexible printed circuit board comprising a second plating layer, a second coverlay film, a second bonding sheet, a third base layer, and a plurality of adhesive layers interposed between the second copper foil layer and the second ground layer.
The method of claim 3, wherein
And a first solder resin layer formed on the first ground layer, and a second solder resin layer formed on the second ground layer.
The method of claim 1,
The second body portion and the connector connection portion may have first and second copper foil layers formed on both sides of the first base layer and the first base layer, and the first plating layer and the first coverlay on the first copper foil layer. A film is formed, and a flexible printed circuit board having a second plating layer and a second coverlay film formed below the second copper foil layer.
The method of claim 8,
A portion of the first coverlay film of the connector connection portion is opened, the flexible printed circuit board to expose the first plating layer.
The method of claim 8,
And a reinforcing plate formed on an upper portion of the second coverlay film of the connector connection unit.
The method of claim 1,
The connection part is a flexible printed circuit board having a first copper foil layer is formed on one side of the first base layer and the first base layer, the first plating layer, the first coverlay film is formed on the first copper foil layer.
The method of claim 11,
A portion of the first coverlay film is opened to expose the first plating layer.

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