KR20120073825A

KR20120073825A - Measurement algorithm for characterics of field effect transistor

Info

Publication number: KR20120073825A
Application number: KR1020100135707A
Authority: KR
Inventors: 김성박
Original assignee: 엘지디스플레이 주식회사
Priority date: 2010-12-27
Filing date: 2010-12-27
Publication date: 2012-07-05

Abstract

PURPOSE: A property measurement algorithm of a field effect transistor is provided to accurately measure a current-voltage property of an active device by applying first and second voltages with a pulse type to the active device. CONSTITUTION: A first terminal of an active device(200) is electrically connected to a first power source(210). A ground voltage is applied to a second terminal of the active device. A third terminal of the active device is electrically connected to a second power source(220). The first power source supplies a gate voltage of a pulse type to the first terminal. The second power source supplies a drain voltage of the pulse type to the third terminal.

Description

Measurement algorithm for Characterics of Field Effect Transistor}

The present invention relates to a characteristic measurement algorithm of a field effect transistor that can accurately measure the current-voltage characteristics of the transistor by applying a voltage in the form of a pulse.

Recently, a liquid crystal display device having a high resolution, high contrast, high display quality, and high response speed while replacing a cathode ray tube has been developed.

The liquid crystal display includes a plurality of pixels defined by gate lines and data lines, and each pixel includes a thin film transistor (TFT) serving as a switch.

Before the thin film transistor TFT is formed on the liquid crystal display, the device characteristics of the thin film transistor TFT are measured and modeled.

In this case, a method of measuring device characteristics of the TFT may include a first voltage (hereinafter, referred to as a “gate voltage”) having a predetermined level at a first terminal of an active device such as a transistor TR or an amplifier. And a method of connecting a second terminal of the active element to ground (GND) and applying a second voltage having a constant level (hereinafter, referred to as a "drain voltage") to the third terminal.

That is, the current-voltage characteristic of the actual thin film transistor TFT formed on the liquid crystal display is measured by using one active element and a DC parameter that applies a constant level of voltage to the one active element for a predetermined time.

On the other hand, when the current-voltage characteristic is measured using the transistor TR having a large channel width, the transistor (T) as the gate voltage and the drain voltage of a constant level are continuously applied to the transistor TR having the large channel width. TR) itself generates heat.

When heat is generated inside the transistor TR, the current characteristic of the transistor TR is affected to such an extent that the current characteristic of the transistor TR cannot be measured. As a result, it is impossible to measure the desired current-voltage characteristics of the thin film transistor TFT formed in the actual liquid crystal display device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a characteristic measurement algorithm of a field effect transistor capable of measuring accurate current-voltage characteristics of the active element by applying first and second voltages having a pulse shape to the active element.

A characteristic measurement algorithm of a field effect transistor according to an embodiment of the present invention includes an active device and a power supply device for applying first and second power supplies to the active device. Applying the first power to a first terminal, applying the second power to a second terminal of the active device, applying a ground voltage to a third terminal of the active device, and applying a current-voltage to the active device. And measuring, wherein the power supply supplies pulsed first and second power supplies to the first and second terminals of the active element.

The characteristic measurement algorithm of the field effect transistor according to an embodiment of the present invention applies a gate voltage and a drain voltage having a pulse shape to the active element, respectively, to prevent heat from being generated in the active element itself, thereby accurately correcting the current of the active element. Voltage characteristics can be measured.

1 is a view showing a general liquid crystal display device.
FIG. 2 is a diagram illustrating a method of measuring device characteristics of the thin film transistor of FIG. 1.
3 is a diagram illustrating embodiments of voltages applied from the first and second power sources of FIG. 2.
4 is a diagram illustrating a current-voltage curve measured by the active device of FIG. 2.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

1 is a view showing a general liquid crystal display device.

As shown in FIG. 1, in a general liquid crystal display device, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm cross each other, and a thin film transistor for driving the liquid crystal cell Clc at an intersection thereof. A liquid crystal display panel 100 having a TFT, a gate driver 110 for supplying scan signals to the gate lines GL1 to GLn, and a data voltage for supplying data voltages to the data lines DL1 to DLm. And a timing controller 130 for controlling the data driver 120 and the gate driver 110 and the data driver 120.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates, and a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm are formed on the lower glass substrate. The thin film transistor TFT is formed at an intersection of the gate lines GL1 to GLn and the plurality of data lines DL1 to DLm.

The thin film transistor TFT supplies the data voltage from the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scan signal from the gate lines GL1 to GLn. To this end, the gate electrode of the thin film transistor TFT is connected to the gate lines GL1 to GLn, the source electrode is connected to the data lines DL1 to DLm, and the drain electrode is connected to the pixel electrode of the liquid crystal cell Clc. Connected.

In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 100 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate line, or may be formed between the liquid crystal cell Clc and a separate common line.

On the upper glass substrate of the liquid crystal display panel 100, color filters of R, G, and B colors corresponding to each pixel area in which the thin film transistors TFT are formed, and the gate lines GL1 to GLn are surrounded by each other. And a black matrix covering the data lines DL1 to DLm, the thin film transistor TFT, and the like.

The gate driver 110 supplies a plurality of scan signals to the plurality of gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 130. These plurality of scan signals cause the plurality of gate lines GL1 to GLn to be sequentially enabled for one horizontal synchronization signal. The gate driver 110 may include a plurality of gate integrated circuits.

The data driver 120 generates a data voltage whenever one of the plurality of gate lines GL1 to GLn is enabled in response to the data control signals DCS from the timing controller 130. The plurality of data lines DL1 to DLm of the liquid crystal display panel 100 are respectively supplied.

The timing controller 130 may enable data synchronization and synchronization signals Vsync and Hsync supplied from an external system (for example, a graphic module of a computer system or an image demodulation module of a television reception system, not shown). The gate control signal GCS for controlling the gate driver 110 and the data control signal DCCS for controlling the data driver 120 are generated using the signal DE and the clock signal CLK.

In addition, the timing controller 130 arranges the image data V-data input from an external system and supplies the sorted data to the data driver 120.

Meanwhile, the thin film transistor TFT is measured using an active device before being formed on the liquid crystal display panel 100.

FIG. 2 is a diagram illustrating a method of measuring device characteristics of the thin film transistor of FIG. 1.

As shown in FIG. 1 and FIG. 2, the thin film transistor TFT is measured using its active device 200 before being patterned on the liquid crystal display panel 100. The active element 200 includes first to third terminals, wherein the first terminal of the active element 200 is electrically connected to the first power source 210 and the second terminal of the active element 200. The ground GND voltage is applied, and the third terminal of the active element 200 is electrically connected to the second power supply 220.

The active element 200 may be formed of any one of a transistor or an amplifier such as a BJT, a TFT, a MOSFET, and a JFT.

The first power supply 210 supplies a gate voltage in the form of a pulse to the first terminal, and the second power supply 220 also supplies a drain voltage in the form of a pulse to the third terminal. In this case, the pulse widths of the gate voltage and the drain voltage may be varied by a measurer and may vary according to the minimum and maximum values allowed by the equipment to which the first and second power sources 210 and 220 are applied.

By applying the pulsed gate voltage and the drain voltage to the active element 200, the current-voltage characteristic of the active element 200 is measured. Even if the width of the active element 200 is large, the gate voltage and the drain voltage applied to the active element 200 are not continuously applied with a constant level voltage, but are applied as a pulse-shaped voltage for a specific time. The heat generated in the active device 200 itself may be minimized.

Therefore, even the wide active element 200 can accurately measure the current-voltage characteristic curve of the element.

3 is a diagram illustrating embodiments of voltages applied from the first and second power sources of FIG. 2.

As shown in mode 1 of FIGS. 2 and 3, a pulsed gate voltage VG is applied to the first terminal of the active element 200, and a drain voltage VD of a constant level is applied to the second terminal. The current-voltage (ID-VG) characteristics of the active device 200 may be measured. In addition, a DUX type drain voltage VD is applied to the second terminal, and a gate voltage VG of a constant level is applied to the first terminal, thereby improving current-voltage (ID-VD) characteristics of the active device 200. It can be specified.

As shown in mode 2 of FIG. 3, a gate voltage VG having a different voltage level in the form of a pulse is applied to the first terminal of the active element 200, and a drain voltage having a constant voltage level in the form of a pulse is applied to the second terminal. (VD) may be applied to measure current-voltage (ID-VG) characteristics of the active device 200. In addition, by applying a drain voltage (VD) of a different voltage level in the form of a pulse to the second terminal and a gate voltage (VG) of a constant voltage level in the form of a pulse to the first terminal by applying a current- of the active element 200- Voltage (IV-VD) characteristics can be measured.

As shown in mode 3 of FIG. 3, the gate voltage VG and the drain voltage VD in the form of pulses are applied to the first terminal and the second terminal of the active element 200, respectively. Even if the pulse width of is greater than the pulse width of the drain voltage VD, the current-voltage (ID-VG) characteristics of the active element 200 may be measured. In addition, a pulsed drain voltage VD and a gate voltage VG are applied to the second terminal and the first terminal, respectively, and the pulse width of the drain voltage VD is greater than the pulse width of the gate voltage VG. Although large, the current-voltage (ID-VD) characteristics of the active device 200 may be measured.

As shown in mode 4 of FIG. 3, the pulsed gate voltage VG is applied to the first terminal of the active device 200, and the drain voltage VD of a constant level is applied to the second terminal. The current-voltage (ID-VG) characteristics of the device 200 may be measured. In addition, a pulsed drain voltage VD and a gate voltage VG are applied to the second terminal and the first terminal, respectively, and the pulse width of the drain voltage VD is greater than the pulse width of the gate voltage VG. Although large, the current-voltage (ID-VD) characteristics of the active device 200 may be measured.

4 is a diagram illustrating a current-voltage curve measured by the active device of FIG. 2.

2 and 4, when the gate voltage and the drain voltage in the form of pulse are applied to the active element 200, the active element 200 has a current-voltage characteristic as shown in (a) and (b). This is measured. As such, when the gate voltage and the drain voltage in the form of pulse are applied to the active element 200, even if the width of the active element 200 is large, the current-voltage characteristics of the active element 200 are exactly as shown in the graph of FIG. 4. Can be measured.

As described above, the present invention can accurately measure the current-voltage characteristics of the active device by applying a gate voltage and a drain voltage having a pulse shape to the active device to prevent heat from being generated in the active device itself. have.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

100: liquid crystal display panel 110: gate driver
120: data driver 130: timing controller
200: active element 210: first power supply
220: second power

Claims

In the characteristic measurement algorithm of the field effect transistor comprising an active element and a power supply device for applying a first and a second power source to the active element,
Applying the first power to the first terminal of the active element, applying the second power to the second terminal of the active element, and applying a ground voltage to the third terminal of the active element; And
Measuring a current-voltage of the active device;
And the power supply device supplies pulsed first and second power supplies to the first and second terminals of the active element.

The method according to claim 1,
And the pulse-shaped first and second power supplies applied to the first and second terminals of the active element have the same pulse width.

The method according to claim 1,
And the pulse-shaped first and second power supplies applied to the first and second terminals of the active element have different pulse widths.

The method according to claim 1,
And one of the first and second power supplies applied to the first and second terminals of the active element has a pulse shape, and the other has a voltage level of a constant level.

The method according to claim 1,
The active device is a characteristic measurement algorithm of a field effect transistor, characterized in that any one of a transistor or an amplifier.

The method according to claim 1,
The pulse widths of the first and second power supplies are different depending on the minimum and maximum values allowed by the power supply equipment.