KR20120072440A - X-ray detector panel - Google Patents

Abstract

PURPOSE: An X-ray detector panel is provided to improve fill factor by increasing an X-ray sensing area. CONSTITUTION: A sensing pixel(PX) is arranged in a first direction(D1) and a second direction(D2). A first data wire(300A) is electrically connected to a thin film transistor of the sensing pixels of a first group. A second data wire(300B) is electrically connected to a thin film transistor of the sensing pixels of a second group. A first bias wire(500A) is electrically connected to a PIN diode of the sensing pixels of the first group. A second bias wire(500B) is electrically connected to the PIN diode of the sensing pixels of the second group.

Description

X-ray detector panel {X-RAY DETECTOR PANEL}

The present invention relates to an x-ray detector panel, and more particularly, to an x-ray detector panel that can detect the X-rays and to photograph the inside of the object.

In general, X-rays have a short wavelength and can easily penetrate an object. The amount of X-rays transmitted is determined by the degree of compactness inside the object. That is, the internal state of the object may be indirectly observed through the transmission amount of the X-ray that has passed through the object.

The X-ray detector panel is a device for detecting the amount of transmission of the X-rays transmitted through the object. The X-ray detector panel detects the amount of transmission of the X-ray, and displays the internal state of the object to the outside through a display device. The X-ray detector may generally be used as a medical inspection device, a non-destructive inspection device, and the like.

The X-ray detector panel generally includes a PIN diode that directly or indirectly senses the intensity of an X-ray applied from the outside, a thin film transistor electrically connected to the P-side electrode of the PIN diode, a gate wiring and data electrically connected to the thin film transistor. Wiring, and a bias wiring for applying a bias voltage to the N-side electrode of the PIN diode.

However, as the PIN diode is planarly spaced apart from the data wiring and the gate wiring so as not to overlap the thin film transistor, and the bias wiring is formed on the PIN diode to cover a portion of the PIN diode. The area of the PIN diode capable of sensing x-rays is reduced. That is, a fill factor, which is a ratio of an area capable of sensing X-rays in a unit pixel area, is deteriorated.

Accordingly, an object of the present invention is to solve such a problem, and an object of the present invention is to provide an X-ray detector panel capable of improving a fill factor by increasing an area capable of sensing X-rays.

The X-ray detector panel according to the exemplary embodiment of the present invention includes sensing pixels, gate lines, first data lines, and second data lines.

The sensing pixels are disposed along first and second directions crossing each other on a base substrate, and are divided into first and second groups adjacent to the second direction, wherein each of the sensing pixels is a thin film transistor and a PIN diode. It includes. The gate lines extend along the first direction and are electrically connected to the thin film transistors of each of the sensing pixels. The first data lines extend in the second direction and are electrically connected to the thin film transistors of each of the sensing pixels of the first group. The second data lines extend in the second direction and are electrically connected to the thin film transistors of each of the sensing pixels of the second group.

The X-ray detector panel may further include first bias wires and second bias wires. The first bias wires extend in the second direction to be electrically connected to the PIN diode of each of the sensing pixels of the first group. The second bias wires extend in the second direction and are electrically connected to the PIN diode of each of the sensing pixels of the second group.

The gate lines may be formed on the base substrate and covered by a gate insulating layer. Each of the thin film transistors is formed on the same layer as the gate line and is connected to the gate line, an active pattern formed on the gate insulating layer to overlap the gate electrode, a drain electrode overlapping a portion of the active pattern, and It may include a source electrode overlapping a portion of the active pattern to be spaced apart from the drain electrode. Each of the PIN diodes is formed of a P-side electrode formed on the gate insulating layer and electrically connected to the source electrode, a PIN semiconductor pattern formed on the P-side electrode, and a transparent conductive material formed on the PIN semiconductor pattern. It may include an N-side electrode.

The X-ray detector panel is formed on the gate insulating layer to cover the thin film transistors and the PIN diodes, the connection electrode upper holes and the N-side electrodes exposing at least a portion of the data connection of each of the drain electrodes. The display device may further include a first insulating layer having bias contact holes exposing each of the portions. The first and second data wires are formed on the first insulating layer and are electrically connected to the data connection parts through the connection electrode upper holes, respectively. The first and second bias wires are formed on the first insulating layer and are electrically connected to the N-side electrodes through the bias contact holes, respectively.

The drain electrodes, the source electrodes, and the P-side electrodes are made of a first metal material, and the first and second data wires and the first and second bias wires are lower in resistance than the first metal material. It may be made of a second metal material having a.

The X-ray detector panel may further include a second insulating layer formed on the first insulating layer to cover the first and second data wires and the first and second bias wires. In this case, the first and second insulating layers are made of an inorganic insulating material.

The X-ray detector panel further includes a data insulating layer formed between the gate insulating layer and the first insulating layer so as to cover the thin film transistors, and having a P-side electrode contact hole exposing a portion of each of the source electrodes. Can be. In this case, each of the P-side electrodes is formed on the data insulating layer and is electrically connected to the source electrode through the P-side electrode contact hole.

The thicknesses of the first and second data wires and the first and second bias wires may be 4500 kV to 5500 kW, and the widths of the first and second data wires and the first and second bias wires may be 5.5. May be in the range of 탆 to 6.5 탆.

Each of the PIN diodes may be formed in planar contact with or overlapping with the first data line or the second data line. In addition, each of the active patterns may extend toward the gate line to partially overlap the gate line.

The X-ray detector panel according to another embodiment of the present invention includes a gate wiring, a gate insulating layer, a thin film transistor, a PIN diode, a first insulating layer, a data wiring, and a bias wiring.

The gate wiring is formed in a first direction on the base substrate. The gate insulating layer is formed on the base substrate to cover the gate wiring. The thin film transistor is formed on the same layer as the gate line and is connected to the gate electrode, an active pattern formed on the gate insulating layer to overlap the gate electrode, a drain electrode overlapping a portion of the active pattern, and the A source electrode overlapping a portion of the active pattern to be spaced apart from the drain electrode. The PIN diode is formed on the gate insulating layer and electrically connected to the source electrode, the P side electrode, the PIN semiconductor pattern formed on the P side electrode, and the N side formed of the transparent conductive material formed on the PIN semiconductor pattern. An electrode. The first insulating layer is formed on the gate insulating layer to cover the thin film transistor and the PIN diode, and exposes a connection electrode upper hole and a portion of the N-side electrode to expose at least a portion of the data connection part of the drain electrode. To have a bias contact hole. The data line is formed in a second direction crossing the first direction on the first insulating layer, and is electrically connected to the data connection part through the connection hole upper hole. The bias wire is formed in the second direction on the first insulating layer, and is electrically connected to the N-side electrode through the bias contact hole. In this case, the PIN diode is formed to be in contact with or overlapping with the data line. The active pattern may be formed to extend toward the gate line to partially overlap the gate line.

The drain electrode, the source electrode and the P-side electrode may be made of a first metal material, and the data line and the bias line may be made of a second metal material having a lower resistance than the first metal material. In addition, the X-ray detector panel may further include a second insulating layer formed on the first insulating layer to cover the data line and the bias line, wherein the first and second insulating layers are made of an inorganic insulating material. Is done. The X-ray detector panel may further include a data insulating layer formed between the gate insulating layer and the first insulating layer to cover the thin film transistor and having a P-side electrode contact hole exposing a portion of the source electrode. Can be. In this case, the P-side electrode is formed on the data insulating layer and electrically connected to the source electrode through the P-side electrode contact hole.

The X-ray detector panel according to another embodiment of the present invention includes a gate wiring, a gate insulating layer, a thin film transistor, a PIN diode, a first insulating layer, a data wiring, and a bias wiring.

The gate wiring is formed in a first direction on the base substrate. The gate insulating layer is formed on the base substrate to cover the gate wiring. The thin film transistor is formed on the same layer as the gate line and is connected to the gate electrode, an active pattern formed on the gate insulating layer to overlap the gate electrode, a drain electrode overlapping a portion of the active pattern, and the A source electrode overlapping a portion of the active pattern to be spaced apart from the drain electrode. The PIN diode is formed on the gate insulating layer and electrically connected to the source electrode, the P side electrode, the PIN semiconductor pattern formed on the P side electrode, and the N side formed of the transparent conductive material formed on the PIN semiconductor pattern. An electrode. The first insulating layer is formed on the gate insulating layer to cover the thin film transistor and the PIN diode, and exposes a connection electrode upper hole and a portion of the N-side electrode to expose at least a portion of the data connection part of the drain electrode. To have a bias contact hole. The data line is formed in a second direction crossing the first direction on the first insulating layer, and is electrically connected to the data connection part through the connection hole upper hole. The bias wire is formed in the second direction on the first insulating layer, and is electrically connected to the N-side electrode through the bias contact hole. In this case, the active pattern extends toward the gate line and partially overlaps the gate line.

The drain electrode, the source electrode and the P-side electrode may be made of a first metal material, and the data line and the bias line may be made of a second metal material having a lower resistance than the first metal material. In addition, the X-ray detector panel may further include a second insulating layer formed on the first insulating layer to cover the data line and the bias line, wherein the first and second insulating layers are made of an inorganic insulating material. Is done. The X-ray detector panel may further include a data insulating layer formed between the gate insulating layer and the first insulating layer to cover the thin film transistor and having a P-side electrode contact hole exposing a portion of the source electrode. Can be. In this case, the P-side electrode is formed on the data insulating layer and electrically connected to the source electrode through the P-side electrode contact hole.

As described above, according to the X-ray detector panel, the existing data lines are divided into first data lines connected to the first pixels and second data lines connected to the second pixels. Since the total length of is reduced compared to the prior art, the electrical resistance felt when the charged charge in each of the PIN diodes 400 is moved can be reduced. Therefore, the width of the first and second data wires can be reduced as much as the electrical resistance due to the total length of the data wire is reduced, thereby increasing the area of each of the PIN diodes to improve the fill factor. .

In addition, as the existing one of the bias wires is separated into first bias wires connected with the sensing pixels of the first group and second bias wires connected with the sensing pixels of the second group, the bias transfer of the bias wiring is moved. The total length can be reduced than before, so that the electrical resistance felt by the bias voltage can be reduced. Thus, the width of the first and second bias wires can be reduced by the decrease in electrical resistance due to the total length of the bias wire, and thus the PIN diodes overlapping the first and second bias wires. By minimizing the area, the fill factor can be improved.

In addition, as the PIN diode is formed to contact or overlap the first and second data lines, an area of the PIN diode may be maximized toward the first and second data lines to improve the fill factor.

In addition, as the active region of the thin film transistor is moved to the gate wiring side than before, a portion of the active region overlaps with the gate wiring, thereby minimizing the reduction of the fill factor by the thin film transistor. That is, the thin film transistor may be formed by moving the thin film transistor toward the gate wiring side, and the fill factor may be improved by increasing the area of the PIN diode.

1 and 2 are circuit diagrams illustrating an X-ray detector panel according to a first exemplary embodiment of the present invention.
3 is an enlarged plan view of a part of the X-ray detector panel of FIG. 1 or 2.
4A, 4B, 4C, 4D, and 4E are cut along the lines I-I ', II-II', III-III ', IV-IV', and V-V 'of FIG. A cross section.
5A, 5B, 5C, and 5D are cross-sectional views illustrating a process of forming a thin film transistor in the method of manufacturing the X-ray detector panel of FIG. 3.
6A, 6B, 6C, and 6D are cross-sectional views illustrating a process of forming a first data metal layer in the method of manufacturing the X-ray detector panel of FIG. 3.
7A, 7B, 7C, and 7D are cross-sectional views illustrating a process of forming an N-side electrode in the method of manufacturing the X-ray detector panel of FIG. 3.
8A, 8B, 8C, and 8D are cross-sectional views illustrating a process of forming a PIN diode in the method of manufacturing the X-ray detector panel of FIG. 3.
9A, 9B, 9C, and 9D are cross-sectional views illustrating a process of forming a first insulating layer in the method of manufacturing the X-ray detector panel of FIG. 3.
10A, 10B, 10C, and 10D are cross-sectional views illustrating a process of forming a lower bias wire or the like in the method of manufacturing the X-ray detector panel of FIG. 3.
FIG. 11 is a cross-sectional view illustrating a process of forming a bias upper wiring on a bias lower wiring in the method of manufacturing the X-ray detector panel of FIG. 3.
12 is an enlarged plan view of a portion of an X-ray detector panel according to a second exemplary embodiment of the present invention.
13A, 13B, 13C, and 13D are cross-sectional views taken along lines VI-VI ', VII-VII', VII-VII ', and VII-VII' of FIG. 12.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text.

It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and that one or more other features It should be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, actions, components, parts or combinations thereof.

In the drawings, the thickness of each device or film (layer) and regions has been exaggerated for clarity of the invention, and each device may have a variety of additional devices not described herein. When (layer) is mentioned as being located on another film (layer) or substrate, an additional film (layer) may be formed directly on or between the other film (layer) or substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

≪ Example 1 >

1 and 2 are circuit diagrams illustrating an X-ray detector panel according to a first exemplary embodiment of the present invention.

1 and 2, the X-ray detector panel according to the present exemplary embodiment includes sensing pixels PX, gate lines 200, gate pad parts 210, first data lines 300A, and first Data pad parts 310A, second data wires 300B, second data pad parts 310B, first bias wires 500A, at least one first bias pad part 510A, and first bias connection The wire 520A, the second bias wires 500B, at least one second bias pad part 510B, and the second bias connection wire 520B are included.

The sensing pixels PX are disposed in a matrix form along a first direction D1 and a second direction D2 crossing the first direction D1. The sensing pixels PX are divided into first and second groups G1 and G2 which are adjacent to each other in the second direction D2 and composed of the same number of pixels. The first and second directions D1 and D2 may be perpendicular to each other.

Each of the sensing pixels PX includes a thin film transistor TFT and a PIN diode 400 electrically connected to the thin film transistor TFT. In this case, the PIN diode 400 directly senses the X-rays applied from the outside to charge the charge according to the intensity of the X-rays, or after the X-rays applied from the outside is primarily changed to visible light, and then senses the visible light The intensity of the x-rays can be measured indirectly.

The gate lines 200 are spaced apart from each other in parallel so as to extend in the first direction D1 and electrically connected to the thin film transistors TFT of the sensing pixels PX. The gate pad parts 210 are disposed at one end of the gate wires 200 to be electrically connected to each of the gate wires 200.

The first data wires 300A are spaced apart from each other in parallel so as to extend in the second direction D2, and each thin film transistor TFT of the sensing pixels PX of the first group G1 is disposed. Is electrically connected to the The first data pad parts 310A are disposed at one end of the first data wires 300A and electrically connected to the first data wires 300A, respectively.

The second data lines 300B are spaced apart from each other so as to extend in the second direction D2 in parallel to each other, so that each thin film transistor TFT of the sensing pixels PX of the second group G2 is disposed. Is electrically connected to the The second data pad parts 310B are disposed at one end of the second data wires 300B and electrically connected to the second data wires 300B, respectively. Here, the second data wires 300B and the second data pad parts 310B may be connected to the first data wires based on a virtual center line that divides the first and second groups G1 and G2. 300A) and the first data pad parts 310A may be symmetrically disposed.

The first bias wires 500A are disposed in parallel with each other so as to be spaced apart from each other and extend in the second direction D2 between the first data wires 300A, and the sensing pixels of the first group G1 are disposed. Are electrically connected to each PIN diode 400 of the field PX. The first bias pad part 510A is disposed at one end of the first bias wires 500A and electrically connected to the first bias wires 500A. The first bias connection wire 520A is disposed at one end of the first bias wires 500A to connect between the first bias wires 500A, and the first bias wires 500A and the The first bias pad portions 510A are electrically connected to each other.

The first bias connection wiring 520A is disposed between the first data pad portions 310A and the outermost wiring adjacent to the first data pad portions 310A of the gate lines 200. For example, it extends in the first direction D1. In addition, although the first bias pad part 510A may be disposed on the first bias connection line 520A and the first data pad parts 310A, the first data pad parts as shown in FIG. 1 or 2. It may be disposed at an outer side in the second direction D2 more than 310A.

The second bias wires 500B are disposed in parallel to each other so as to be spaced apart from each other and extend in the second direction D2 between the second data wires 300B, and the sensing pixels of the second group G2 are disposed. Are electrically connected to each PIN diode 400 of the field PX. The second bias pad part 510B is disposed at one end of the second bias wires 500B and electrically connected to the second bias wires 500B. The second bias connection wire 520B is disposed at one end of the second bias wires 500B to connect between the second bias wires 500B, and the second bias wires 500B and the second bias wires 500B. The second bias pad portions 510B are electrically connected to each other.

Here, the second bias wires 500B, the second bias pad part 510B, and the second bias connection wire 520B may form the center line that divides the first and second groups G1 and G2. As a reference, the first bias wires 500A, the first bias pad part 510A, and the first bias connection wire 520A may be symmetrically disposed.

In the present exemplary embodiment, only one first and second bias connection wires 520A and 520B and one first and second bias pad parts 510A and 510B may be formed, respectively, as shown in FIG. 1. As described above, two first and second bias connection wires 520A and 520B and two first and second bias pad parts 510A and 510B may be formed. In this case, different bias voltages may be applied to the two first bias pad portions 510A or the two second bias pad portions 510B.

Meanwhile, the driving process of the X-ray detector panel will be briefly described with reference to FIG. 1 or 2 as follows. First, a bias voltage is applied to the first and second bias pad parts 510A and 510B such that a reverse bias is applied to each PIN diode 400 of the sensing pixels PX. Thereafter, each of the PIN diodes 400 of the sensing pixels PX directly or indirectly senses an X-ray applied from the outside to charge a charge according to the intensity of the X-ray. Subsequently, gate signals are sequentially applied to the gate pad part 210 to turn on each of the thin film transistors TFTs of the sensing pixels PX, thereby turning on the PIN diodes 400. Charges are transferred to the first data pad portions 310A or the second data pad portions 310B through the first data wires 300A or the second data wires 300B. . These charges are converted into sensing signals through an output circuit (not shown) electrically connected to the first data pad portions 310A and the second data pad portions 310B to be displayed on an external display device (not shown). Or stored in a memory (not shown).

3 is an enlarged plan view of a part of the X-ray detector panel of FIG. 1 or FIG. 2, and FIGS. 4A, 4B, 4C, 4D, and 4E are lines II ′ and II-II ′ of FIG. 3. Sections cut along the lines, III-III ', IV-IV' and V-V '.

In the present exemplary embodiment, the first data wires 300A, the first data pad parts 310A, the first bias wires 500A, the first bias pad part 510A, and the first bias connection. The wiring 520A is connected to the second data wires 300B, the second data pad parts 310B, the second bias wires 500B, the second bias pad part 510B, and the second bias connection. Since they are substantially the same as the wirings 520B, the second data wires 300B, the second data pad parts 310B, the second bias wires 500B, and the second bias pad part 510B. A detailed description of the second bias connection wiring 520B will be omitted.

3, 4A, 4B, 4C, 4D, and 4E, the X-ray detector panel may include a base substrate 100, a gate insulation layer 110, a data insulation layer 120, and a first insulation layer. 130, the second insulating layer 140 and the third insulating layer 150 are further included.

Each of the first data wires 300A includes a data lower wire 302 and a data upper wire 304, and each of the first bias wires 500A includes a bias lower wire 502 and a bias upper wire ( 504). Each of the first gate pad portions 210 may include a gate lower pad 212, a gate upper pad 214, and a gate transparent pad 216. Each of the first data pad portions 310A may include a data lower pad ( 312) and a data upper pad 314, wherein the first bias pad portion 510A includes a bias lower pad 512, a bias upper pad 514, and a bias transparent pad 516.

In addition, each of the TFTs includes a gate electrode 10, an active pattern 20, a drain electrode 30, and a source electrode 40, and each of the PIN diodes 400 includes a P-side electrode. 410, a PIN semiconductor pattern 420, and an N-side electrode 430.

The base substrate 100 has a plate shape and may be made of a transparent material, for example, glass, quartz, synthetic resin, or the like. The gate lines 200 are formed in the first direction D1 on the base substrate 100, and the gate lower pads 212 are connected to one ends of the gate lines 200, respectively. The gate electrodes 10 branch from the gate lines 200.

The gate insulating layer 110 is formed on the base substrate 100 to cover the gate lines 200, the gate electrodes 10, and the gate lower pads 212. In this case, the gate insulating layer 110 may be made of an inorganic material, for example, silicon nitride (SiNx), and may have a thickness of about 4500 μs, for example.

Each of the active patterns 20 is formed on the gate insulating layer 110 to overlap each of the gate electrodes 10. Each of the active patterns 20 may be formed of, for example, a double layer of amorphous silicon (a-Si) having a thickness of about 2200 μs and ion doped amorphous silicon (N + a-Si) having a thickness of about 500 μs. On the other hand, the active patterns 20 are formed to extend toward the gate lines 200, respectively, so that a part of the active patterns 20 overlap the gate lines 200. That is, the active patterns 20 are formed to move toward the gate lines 200 than in the prior art, so that some of the active patterns 20 overlap the gate lines 200.

The drain electrodes 30 are formed on the gate insulating layer 110 to extend in the first direction D1, and a portion of the drain electrodes 30 overlap the active patterns 20, respectively. In this case, a part of the drain electrodes 30 overlapping the active patterns 20 may have a shape protruding along the second direction D2 to overlap each of the gate lines 200.

The source electrodes 40 are formed on the gate insulating layer 110 so as to face each of the drain electrodes 30 so as to extend along the first direction D1, and a part of the drain electrodes 30. Each of the active patterns 20 overlaps with each other. In this case, a portion of the source electrodes 40 overlapping the active patterns 20 may have a shape protruding along the second direction D2 to overlap each of the gate lines 200. Unlike the FIG. 3, the source electrodes 40 may be formed in unit regions formed by the gate lines 200 and the first data lines 300A so as not to be connected to the drain electrodes 30. It may be formed wide.

The bias lower pad 512 is formed on the gate insulating layer 110, and a part of the bias lower pad 512 extends along the second direction D2 to be electrically connected to the bias line 500. The first bias connection line 520A is formed on the gate insulating layer 110 to be electrically connected to an extended portion of the bias lower pad 512.

The data insulating layer 120 may connect the drain electrodes 30, the active patterns 20, the source electrodes 40, the bias lower pad 512, and the first bias connection wiring 520A. It is formed on the gate insulating layer 110 to cover. The data insulating layer 120 may be made of an inorganic material, for example, silicon nitride (SiNx), and may have a thickness of about 1000 GPa, for example.

P-side electrode contact holes PH for exposing portions of the source electrodes 40 and connection electrodes for exposing portions of data connection portions that are part of the drain electrodes 30 are exposed in the data insulating layer 120. Extending along the second direction D2 from the bias pad lower hole IH1 and the bias lower pad 512 to expose the lower holes CH1, part or all of the bias lower pad 512. Bias connection bottom holes SH1 are formed to expose a portion of the bias contact portion that is part of the portion. In addition, gate pad lower holes GH1 are formed in the gate insulating layer 110 and the data insulating layer 120 to expose some or all of the gate lower pads 212. That is, each of the gate pad lower holes GH1 is formed in the data insulating layer 120 so as to correspond to the first gate pad lower hole formed in the gate insulating layer 110 and the first gate pad lower hole. It is composed of a gate pad lower hole.

The P-side electrodes 410 are formed on the data insulating layer 120 and are electrically connected to each of the source electrodes 40 through the P-side electrode contact holes PH. The gate upper pads 214 are formed on the data insulating layer 120 so as to overlap the gate lower pads 212, respectively, and the gate lower pads 212 through the gate pad lower hole GH1. Are electrically connected to each other. Meanwhile, data connection electrodes 330 may be formed on the data insulating layer 120 so as to overlap each data connection part of the drain electrodes 30. In this case, the data connection electrodes 330 are electrically connected to the data connection portions of the drain electrodes 30 through the connection electrode lower holes CH1.

The bias upper pad 514 is formed on the data insulating layer 120 to overlap the bias lower pad 512, and is electrically connected to the bias lower pad 512 through the bias pad lower hole IH1. Connected. On the other hand, a bias pad connection is formed to overlap a portion of the bias contact portion of the bias lower pad 512, and electrically connected to the bias contact portion of the bias lower pad 512 through the bias connection lower holes SH1. Electrodes 514a may be further formed.

The PIN semiconductor patterns 420 are formed on the P-side electrode 410, respectively, and charge the electric charge by directly or indirectly sensing X-rays applied from the outside. Each of the PIN semiconductor patterns 420 may include an N-type semiconductor pattern formed on the P-side electrode 410, an intrinsic semiconductor pattern formed on the N-type semiconductor pattern, and a P-type semiconductor pattern formed on the intrinsic semiconductor pattern. Include. For example, the P-type semiconductor pattern may be formed to a thickness of about 100 GPa, the intrinsic semiconductor pattern may be formed to a thickness of about 10000 GPa, and the N-type semiconductor pattern may be formed to a thickness of about 500 GPa.

The N-side electrodes 430 are formed on the PIN semiconductor pattern 420. The N-side electrodes 430 may be made of a transparent conductive material, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like. In this case, the N-side electrodes 430 may be formed to a thickness of about 400Å.

The first insulating layer 130 may include the PIN diodes 400, the gate upper pads 214, the data connection electrodes 330, the bias upper pad 514, and the bias pad connection electrodes ( It is formed on the data insulating layer 120 to cover the 514a. Here, the first insulating layer 130 may be an organic insulating film that can flatten the surface as shown in the figure, or alternatively, may be an inorganic insulating film that can be bent on the surface. The inorganic insulating layer may be made of silicon oxide (SiOx) or silicon nitride (SiNx), and may be, for example, formed to a thickness of about 6000 to 8000 Å. Therefore, the first insulating layer 130 may prevent corrosion of the PIN diodes 400 as well as the thin film transistors TFT by external chemical penetrants. On the other hand, the inorganic insulating film may also be formed relatively thick to have a flat surface as shown in the figure.

Bias contact holes BH for exposing a portion of the N-side electrodes 430 and connection electrode upper holes for exposing a portion of the data connection electrodes 330 are formed in the first insulating layer 130. (CH2), gate pad upper holes GH2 for exposing some or all of the gate upper pads 214, bias pad upper holes IH2 for exposing some or all of the bias upper pads 514. ) And bias connection top holes SH2 for exposing a portion of the bias pad connection electrodes 514a.

The data lower interconnections 302 are formed along the second direction D2 on the first insulating layer 130 to overlap the data connection electrodes 330, so that the connection electrode upper holes CH2 are formed. ) Is electrically connected to the data connection electrodes 330. The data lower pads 312 are formed on the first insulating layer 130 and connected to one ends of the data lower wires 302. The gate transparent pads 216 are formed on the first insulating layer 130 so as to overlap the gate upper pads 214, respectively, so that the gate upper pads are formed through the gate pad upper holes GH2. And electrically connected to 214.

The bias lower wirings 502 are formed in the second direction D2 on the first insulating layer 130, and each of the N-side electrodes 430 through the bias contact holes BH. Electrically connected. In addition, the bias lower wires 502 extend to overlap the bias pad connection electrodes 514a and are electrically connected to the bias pad connection electrodes 514a through the bias connection upper holes SH2. do. The bias transparent pad 516 is formed on the first insulating layer 130 to overlap the bias upper pad 514, and is electrically connected to the bias upper pad 514 through the bias pad upper hole IH2. Is connected. Here, the data lower wirings 302, the data lower pads 312, the gate transparent pads 216, the bias lower wirings 502, and the bias transparent pad 516 are all transparent conductive materials. For example, it is made of indium tin oxide (ITO), indium zinc oxide (IZO), or the like, and may be formed to a thickness of about 700 μs.

The data upper wires 304 are formed on the data lower wires 302, respectively, and the data upper pads 314 are formed on the data lower pads 312, respectively. The bias upper wirings 504 are formed on the bias lower wirings 502, respectively. In the present embodiment, the data upper pads 314 may be omitted. The first bias lines 500A may be formed in the second direction D2 while covering all or part of each of the thin film transistors TFT of the first group G1. Alternatively, separate blocking portions spaced apart from the first bias lines 500A may be formed to cover all or part of each of the thin film transistors TFT.

The second insulating layer 140 covers the first data wires 300A, the second data wires 300B, the first bias wires 500A, and the second bias wires 500B. Is formed on the first insulating layer 140. The second insulating layer 140 may be an organic insulating film or an inorganic insulating film. The inorganic insulating layer may be made of silicon nitride (SiNx), and may be, for example, formed to a thickness of about 4000 GPa. Here, when the second insulating layer 140 is formed of an inorganic insulating film, the first data wires 300A, the second data wires 300B, the first bias wires 500A, and the first electrode The two bias lines 500B may be prevented from being corroded by external chemical penetrants. In this case, the second insulating layer 140 is disposed on the first insulating layer 140 to expose the gate transparent pads 216, the data upper pads 314, and the bias transparent pad 516. Is formed.

The third insulating layer 150 may be formed on the second insulating layer 140 and may be formed of an organic material to planarize the surface. On the other hand, the X-ray detector panel is formed on the third insulating layer 150, the X-ray applied from the outside can be changed into light that can be sensed by the PIN diodes 400, for example, green light It may further include a radar unit (not shown). In this case, the scintillator unit may be attached to the third insulating layer 150 in the form of a film, but may be formed on the third insulating layer 150 through a separate growth process.

On the other hand, in the present embodiment, as the data wires, which are conventionally extended in one length along the second direction D2, are separated into the first data wires 300A and the second data wires 300B, Since the total length of the data line is reduced compared to the related art, the electrical resistance felt when the charged charge in each of the PIN diodes 400 is moved may be reduced. Therefore, the width of the first and second data wires 300A and 300B may be reduced by the decrease in the electrical resistance due to the total length of the data wires, thereby reducing the area of each of the PIN diodes 400. You can increase the fill factor by increasing.

In addition, as the bias wires, which have been conventionally extended in one along the second direction D2, are separated into the first bias wires 500A and the second bias wires 500B, the bias transfer moves. The total length of the bias wiring can be reduced than before, so that the electrical resistance felt by the bias voltage can be reduced. Accordingly, the widths of the first and second bias wires 500A and 500B may be reduced by the decrease in the electrical resistance due to the total length of the bias wires, and thus the first and second bias wires ( The fill factor may be improved by minimizing the area of the PIN diodes 400 overlapping with 500A and 500B.

Specifically, the width of the conventional data wires was about 10 μm, and the width of the conventional bias wires was about 8 μm. However, in the present embodiment, the conventional data wires and the conventional bias wires are respectively divided into two parts, so that the electrical resistance by the length is reduced in half, so that the first and second data are reduced by the decrease of the resistance. The widths of the wires 300A and 300B and the first and second bias wires 500A and 500B can be reduced to about 6 μm, that is, the minimum width of the process that will not be disconnected, that is, between 5.5 μm and 6.5 μm. have. In addition, the thicknesses of the first and second data wires 300A and 300B and the first and second bias wires 500A and 500B may be up to about 5000 kW (ie, 4500 kW), which is a minimum thickness in a process that will not be disconnected. It can also be reduced to a range between -5500 kHz.

In the present embodiment, referring again to FIG. 4E, the area of the PIN diodes 400 is extended along the first direction D1 in each of the unit regions, so that the first data wires (see FIG. 4E) may be expanded. Each of the first data wires 300A may be formed to be in contact with each of the first and second data lines 300A. As the area of the PIN diodes 400 extends in the first direction D1, the fill factor may be further improved.

3, referring to FIG. 3 again, the active pattern 20 of each of the TFTs may be moved toward the gate line 200 than before, so that a part of each of the active patterns 20 may be formed. As the gate lines 200 overlap each other, the reduction of the fill factor by the thin film transistors TFT may be minimized. That is, the thin film transistors TFT may be formed by moving the thin film transistors toward the gate lines 200, thereby increasing the area of the PIN diodes 400, thereby improving the fill factor.

Meanwhile, in the present exemplary embodiment, the data insulating layer 120, the data connection electrodes 330, the gate upper pads 214, the bias upper pad 514, and the bias pad connecting electrodes 514a. May be omitted in some cases. Therefore, the data lower interconnections 302 are electrically connected to the data connection portions of the drain electrode 30 through the connection electrode upper holes CH2, respectively, and the bias lower interconnections 502 are connected to the bias. It may be electrically connected to the bias contact portion of the bias lower pad 512 through the connection upper hole SH2. In addition, the gate transparent pads 216 may be electrically connected to the gate lower pads 212 through first gate pad lower holes and the gate pad upper hole GH2 formed in the gate insulating layer 110, respectively. The bias transparent pad 516 may be electrically connected to the bias lower pad 512 through the bias pad upper hole IH2. In addition, when the source electrodes 40 are broadly formed in each unit region, the PIN semiconductor patterns 420 may be formed on the source electrodes 40, respectively.

Hereinafter, a method of manufacturing the X-ray detector panel will be described using separate drawings.

5A, 5B, 5C, and 5D are cross-sectional views illustrating a process of forming a thin film transistor in the method of manufacturing the X-ray detector panel of FIG. 3.

5A, 5B, 5C, and 5D, first, a gate metal layer is formed on the base substrate 100, and the gate metal layer is patterned to form the gate wires 200 and the gate lower pads ( 212 and the gate electrodes 10 are formed. In this case, the gate metal layer may include, for example, a double layer made of aluminum neodymium compound (AlNd) and chromium (Cr) or a triple layer made of aluminum neodymium compound (AlNd), chromium (Cr) and chromium nitride (CrNx). Can be. In this case, the aluminum neodymium compound (AlNd) may be formed to a thickness of about 2500 kPa, the chromium (Cr) to a thickness of about 500 kPa, and the chromium nitride (CrNx) may be formed to a thickness of about 100 kPa.

Subsequently, the gate insulating layer 110 is formed on the base substrate 100 to cover the gate lines 200, the gate lower pads 212, and the gate electrodes 10. In this case, the gate insulating layer 110 may be made of an inorganic material, for example, silicon nitride (SiNx), and may have a thickness of about 4500 μs, for example.

Subsequently, an active layer is formed on the gate insulating layer 110 and the active layer is patterned to form the active patterns 20. In this case, the active layer may be formed of, for example, a double layer including an amorphous silicon layer having a thickness of about 2200 μs and an ion doped amorphous silicon layer having a thickness of about 500 μs.

Subsequently, after forming a first data metal layer on the gate insulating layer 110 to cover the active patterns 20, the first data metal layer is patterned to form the drain electrodes 30 and the source electrodes. 40, the bias lower pad 512 and the bias connection wiring 520 are formed. In this case, the first data metal layer may include, for example, chromium (Cr) and may be formed to a thickness of about 1500 GPa. Meanwhile, when patterning the first data metal layer, some of the active patterns 20 may also be etched. As a result, the ion doped amorphous silicon layer in each of the active patterns 20 may be separated into two parts.

6A, 6B, 6C, and 6D are cross-sectional views illustrating a process of forming a first data metal layer in the method of manufacturing the X-ray detector panel of FIG. 3.

6A, 6B, 6C, and 6D, after patterning the first data metal layer, the drain electrodes 30, the source electrodes 40, the bias lower pad 512, and the The date insulating layer 120 is formed on the gate insulating layer 110 to cover the bias connection wiring 520. The data insulating layer 120 may be made of an inorganic material, for example, silicon nitride (SiNx), and may have a thickness of about 1000 GPa, for example. Subsequently, a portion of the data insulating layer 120 is etched to form the connection electrode lower holes CH1, the P-side electrode contact holes PH, the gate pad lower holes GH1, and the bias pad lower. A hole IH1 and the bias connection lower holes SH1 are formed. Here, the gate pad lower holes GH1 are formed by etching part of the data insulating layer 120 and part of the gate insulating layer 110 at the same time.

Subsequently, a second data metal layer 160 is formed on the data insulating layer 130. In this case, the second data metal layer 160 may include, for example, chromium (Cr) and have a thickness of about 1500 μs.

7A, 7B, 7C, and 7D are cross-sectional views illustrating a process of forming an N-side electrode in the method of manufacturing the X-ray detector panel of FIG. 3.

7A, 7B, 7C, and 7D, after forming the second data metal layer 160, a PIN semiconductor layer 170 is formed on the second data metal layer 160. The PIN semiconductor layer 170 includes a P-type semiconductor layer, an intrinsic semiconductor layer, and an N-type semiconductor layer, wherein the P-type semiconductor layer is about 100 GPa thick, the intrinsic semiconductor layer is about 10000 GPa thick, and The N-type semiconductor layer may be formed to a thickness of about 500 GPa.

Subsequently, after forming a first transparent electrode layer on the PIN semiconductor layer 170, the first transparent electrode layer is patterned to form the N-side electrodes 430. In this case, the first transparent electrode layer may be formed of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like, and may be formed to a thickness of about 400 μs.

8A, 8B, 8C, and 8D are cross-sectional views illustrating a process of forming a PIN diode in the method of manufacturing the X-ray detector panel of FIG. 3.

8A, 8B, 8C, and 8D, after patterning the first transparent electrode layer, the PIN semiconductor layer 170 is patterned to form the PIN semiconductor patterns 420. Subsequently, the second data metal layer 160 is patterned to form the data connection electrodes 330, the P-side electrodes 410, the gate upper pads 214, the bias upper pad 514, and the Bias pad connection electrodes 514a are formed.

9A, 9B, 9C, and 9D are cross-sectional views illustrating a process of forming a first insulating layer in the method of manufacturing the X-ray detector panel of FIG. 3.

9A, 9B, 9C, 9D, and 4E, after patterning the second data metal layer 160, the data connection electrodes 330, the PIN diodes 400, and the gates. The first insulating layer 130 is formed on the data insulating layer 120 to cover the upper pads 214, the bias upper pad 514, and the bias pad connecting electrodes 514a. The first insulating layer 130 is formed of an organic insulating film or an inorganic insulating film. When the first insulating layer 130 is an inorganic insulating layer, the first insulating layer 130 may be made of silicon oxide (SiOx) or silicon nitride (SiNx), and may be, for example, formed to a thickness of about 6000 to 8000 Å. Subsequently, a portion of the first insulating layer 130 is etched to form the connection electrode upper holes CH2, the bias contact holes BH, the gate pad upper holes GH2, and the bias pad upper holes. IH2 and the bias connection upper holes SH2 are formed.

10A, 10B, 10C, and 10D are cross-sectional views illustrating a process of forming a lower bias wire or the like in the method of manufacturing the X-ray detector panel of FIG. 3.

10A, 10B, 10C, 10D, and 4E, after etching a portion of the first insulating layer 130, a second transparent electrode layer is formed on the first insulating layer 130. . In this case, the second transparent electrode layer may be formed of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like, and may be formed to a thickness of about 700 μs. Afterwards, the second transparent electrode layer is patterned to form the data lower interconnections 302, the bias lower interconnections 502, the gate transparent pads 216, the bias transparent pads 516, and the data lower pads. Form 312.

FIG. 11 is a cross-sectional view illustrating a process of forming a bias upper wiring on a bias lower wiring in the method of manufacturing the X-ray detector panel of FIG. 3.

Referring to FIG. 11, after patterning the second transparent electrode layer, the data lower wirings 302, the bias lower wirings 502, the gate transparent pads 216, and the bias transparent pads 516. And a bias metal layer on the first insulating layer 130 to cover the data lower pad 312. In this case, the bias metal layer may be formed of, for example, a double layer of molybdenum (Mo) and aluminum (Al), the molybdenum (Mo) to a thickness of about 500 kPa, and the aluminum (Al) to a thickness of about 2500 kPa Can be formed. Afterwards, the bias metal layer is patterned to form the data upper interconnections 304, the bias upper interconnections 504, and the data upper pads 314.

4A, 4B, 4C, 4D, and 4E, after patterning the bias metal layer, the first data lines 300A, the first bias lines 500A, and the data pads. The second insulating layer 140 is formed on the first insulating layer 130 to cover the parts 310. In this case, the second insulating layer 140 is formed of an organic insulating film or an inorganic insulating film. Here, when the second insulating layer 140 is an inorganic insulating film, it may be made of silicon nitride (SiNx), for example, may be formed to a thickness of about 4000 kPa. Here, the second insulating layer 140 may expose the gate transparent pads 216, the bias transparent pad 516, and the data upper pads 314. The bias transparent pad 516 and the data top pads 314 are not formed.

Subsequently, the third insulating layer 150 is formed on the second insulating layer 140, and then the scintillator part is formed on the third insulating layer 150. In this case, the scintillator unit may be attached to the third insulating layer 150 in the form of a film, but may be formed on the third insulating layer 150 through a separate growth process.

As described above, according to the present exemplary embodiment, the first data lines 300A and the second data lines 300B have the same process as the first bias lines 500A and the second bias lines 500B. And formed of the same structure and material as the first bias lines 500A and the second bias lines 500B. For example, the first data wires 300A and the second data wires 300B may be formed of an ITO layer having a thickness of about 700 μs, a molybdenum (Mo) layer having a thickness of about 500 μs, and an aluminum having a thickness of about 2500 μs ( Al) layer.

On the other hand, the conventional data wires are formed of the first data metal layer for forming the drain electrode 30 and the source electrode 40. That is, after the first data metal layer is patterned, the conventional data wires are formed. In this case, the first data metal layer is formed of a material having a higher resistance value than the first bias wires 500A and the second bias wires 500B. For example, chromium (Cr) having a thickness of about 1500 μs It can be formed in layers.

Accordingly, the first bias wires 500A and the second bias wires have a lower resistance value than that of the first data metal layer in the first data wires 300A and the second data wires 300B. As formed by the same process as that of 500B, charges charged in the PIN diodes 500 are turned on so that the thin film transistors TFT are turned on, so that the first data lines 300A and the When moving through the second data lines 300B, the signal transmission efficiency may be further improved by the first data lines 300A and the second data lines 300B.

The first bias connection line 520A electrically connecting the first bias wires 500A and the first bias pad portion 510A, the second bias wires 500B, and the first bias wires 500B. The second bias connection line 520B, which electrically connects between the second bias pad portions 510B, is formed when the first data metal layer is patterned, so that the first data lines 300A and the first data lines 300A and the first bias line 520B are formed. The electrical connection with the two data lines 300B can be prevented.

<Example 2>

12 is an enlarged plan view of a part of the X-ray detector panel according to the second exemplary embodiment of the present invention, and FIGS. 13A, 13B, 13C, and 13D are lines V-V 'and VI-VI' of FIG. 12. These are cross-sectional views cut along the line, Ⅶ-Ⅶ 'line and Ⅷ-Ⅷ' line.

The X-ray detector panel according to the present exemplary embodiment is except for the first data pad parts 310A, the first bias pad part 510A, and the first bias connection wiring 520A, and the X-ray detector according to the first embodiment. Since it is substantially the same as the panel, detailed description of the same components as those of the first embodiment will be omitted, and the same reference numerals will be given to the same components as the first embodiment. In addition, the second data pad parts, the second bias pad part, and the second bias connection wiring may be connected to the first data pad parts 310A, the first bias pad part 510A, and the first bias connection wiring 520A. Since it is substantially the same, a detailed description thereof will be omitted.

12, 13A, 13B, 13C, and 13D, each of the first data pad portions 310A includes a data lower pad 312, a data upper pad 314, and a data transparent pad 316. Include. In addition, data contact parts 312a extending from the data lower pads 312 toward the first data wires 300A are formed.

The data lower pads 312 and the data contact portions 312a are formed on the gate insulating layer 110 and covered by the data insulating layer 120. In this case, the data insulating layer 120 has data pad lower holes DH1 exposing a part or all of the data lower pads 312 and a connection wiring exposing at least a part of the data contact parts 312a. Lower holes KH1 are formed.

The data upper pads 314 are formed on the data insulating layer 120 to overlap each of the data lower pads 312, and are covered by the first insulating layer 130. The data upper pads 314 are electrically connected to the data lower pads 312 through the data pad lower holes DH1, respectively. In the present exemplary embodiment, the data contact portions are formed between the data insulating layer 120 and the first insulating layer 130 to overlap the data contact portions 312a through the connection wiring lower holes KH1. Data pad connection electrodes 314a are electrically connected to the 312a, respectively. Here, data pad upper holes DH2 exposing a part or all of the data upper pads 312 and at least a portion of the data pad connecting electrodes 314a are exposed in the first insulating layer 130. Connecting wiring upper holes KH2 are formed.

The data transparent pads 316 are formed on the first insulating layer 130 to overlap the data upper pads 314, and the data upper pads (DH2) through the data pad upper holes DH2. 314) and each electrically connected. In this case, the data transparent pads 316 are not covered by the second insulating layer 140 and the third insulating layer 150. In addition, the data lower interconnections 302 are formed in the first insulating layer 130 and are electrically connected to the data pad connection electrodes 314a through the connection interconnection upper holes KH2, respectively.

The first bias pad portion 510A includes a bias lower pad 512 and a bias upper pad 514, and the first bias connection wiring 520A includes a connection lower wiring 522 and a connection upper wiring 524. It includes.

The bias lower pad 512 and the connection lower wiring 522 are connected to each other on the first insulating layer 130 in the same manner as the bias lower wirings 502. The connection lower wiring 522 is connected to one end of the bias lower wirings 502. That is, the connection lower wiring 522 electrically connects between the bias lower wirings 502 and the bias lower pad 512. The bias upper pad 514 is formed on the bias lower pad 512, and the connection upper wiring 524 is formed on the connection lower wiring 522 so that one end of the bias upper wiring 504 is formed. Connected with. In this case, the bias upper pad 514 may be omitted.

Meanwhile, in the present embodiment, the data insulating layer 120, the data upper pads 314, and the data pad connecting electrodes 314a may be omitted in some cases. Therefore, the data transparent pads 316 are electrically connected to the data lower pads 312 through the data pad upper hole DH2, respectively, and the data lower wires 302 are on the connection wiring. The holes KH2 may be electrically connected to the data contact portions of the data lower pads 312, respectively.

In addition, the method of manufacturing the X-ray detector panel according to the present exemplary embodiment may include the first data pad parts 310A, the first bias pad part 510A, and the first bias connection wiring 520A. Since it is substantially the same as the method of manufacturing the X-ray detector panel according to the first embodiment, detailed description thereof will be omitted.

In the present exemplary embodiment, the data lower pads 312 and the data contact portions 312a are formed when the first data metal layer is patterned, and the data upper pads 314 are formed on the second data metal layer 160. ) Is formed when patterning, and the data transparent pads 316 are formed when the second transparent electrode layer is patterned. In addition, the bias lower pad 512 and the connection lower interconnection 522 are formed when the second transparent electrode layer is patterned, and the bias upper pad 514 and the connection upper interconnection 524 are formed by the bias electrode layer. It is formed when patterned.

As such, according to the present exemplary embodiment, the first data lines 300A may be electrically connected to the first data pad portions 310A through the data contact portions 312a formed on the gate insulating layer 110. As the first contact wires 520A cross the data contact parts 312a, the first bias connection wires 520A formed by the same process as the first data wires 300A may be connected to each other. It can be placed on top. Therefore, it is possible to prevent the first bias connection line 520A from being electrically connected to the first data lines 300A.

In the detailed description of the present invention described above with reference to the preferred embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary skill in the art will be described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

100: base substrate 110: gate insulating layer
120: data insulating layer 130: first insulating layer
140: second insulating layer 150: third insulating layer
200: gate wiring 210: gate pad portion
300A: first data wiring 310A: first data pad portion
312a: data contact 330: data connection electrode
300B: second data wire 310B: first data pad portion
400: PIN diode 410: P side electrode
420: PIN semiconductor pattern 430: N-side electrode
TFT: thin film transistor 500A: first bias wiring
510A: first bias pad portion 520A: first bias connection wiring
500B: second bias wiring 510B: second bias pad portion
520B: second bias connection wiring

Claims (16)

Sensing pixels disposed along first and second directions crossing each other on a base substrate, divided into first and second groups adjacent to the second direction, each sensing pixel including a thin film transistor and a PIN diode;
Gate wires extending along the first direction and electrically connected to the thin film transistors of each of the sensing pixels;
First data wires extending in the second direction and electrically connected to the thin film transistors of the sensing pixels of the first group; And
And second data wires extending along the second direction and electrically connected to the thin film transistors of each of the second group of sensing pixels. The display device of claim 1, further comprising: first bias wires extending in the second direction and electrically connected to a PIN diode of each of the first group of sensing pixels; And
And second bias wires extending along the second direction and electrically connected to the PIN diode of each of the second group of sensing pixels. The semiconductor device of claim 2, wherein the gate lines are formed on the base substrate and covered by a gate insulating layer.
Each of the thin film transistors is formed on the same layer as the gate line and is connected to the gate line, an active pattern formed on the gate insulating layer to overlap the gate electrode, a drain electrode overlapping a portion of the active pattern, and A source electrode overlapping a portion of the active pattern to be spaced apart from the drain electrode;
Each of the PIN diodes is formed of a P-side electrode formed on the gate insulating layer and electrically connected to the source electrode, a PIN semiconductor pattern formed on the P-side electrode, and a transparent conductive material formed on the PIN semiconductor pattern. And an N-side electrode. 4. The N-side electrode and the connection electrode upper holes formed on the gate insulating layer to cover the thin film transistors and the PIN diodes, and expose at least a portion of the data connection of each of the drain electrodes. Further comprising a first insulating layer having bias contact holes exposing a portion of each of the two,
The first and second data wires are formed on the first insulating layer and are electrically connected to the data connection parts through the connection electrode upper holes, respectively.
And the first and second bias wires are formed on the first insulating layer and electrically connected to the N-side electrodes through the bias contact holes, respectively. The method of claim 4, wherein the drain electrodes, the source electrodes and the P-side electrode are made of a first metal material.
And the first and second data lines and the first and second bias lines are made of a second metal material having a lower resistance than the first metal material. The semiconductor device of claim 4, further comprising a second insulating layer formed on the first insulating layer to cover the first and second data wires and the first and second bias wires.
And the first and second insulating layers are made of an inorganic insulating material. The semiconductor device of claim 4, further comprising a data insulating layer formed between the gate insulating layer and the first insulating layer so as to cover the thin film transistors and having P-side electrode contact holes exposing a portion of each of the source electrodes. and,
Each of the P-side electrodes is formed on the data insulating layer to be electrically connected to the source electrode through the P-side electrode contact hole. The method of claim 4, wherein the first and second data lines and the first and second bias wires have a thickness of 4500 ns to 5500 ns.
The width of the first and second data lines and the first and second bias lines is 5.5㎛ ~ 6.5㎛ characterized in that the X-ray detector panel. The method of claim 4, wherein each of the PIN diodes are
And the first data line or the second data line in planar contact with or overlapping with the second data line. The method of claim 4 or 9, wherein each of the active patterns
The X-ray detector panel, characterized in that extending to the gate wiring side is partially overlapped with the gate wiring. A gate wiring formed on the base substrate in a first direction;
A gate insulating layer formed on the base substrate to cover the gate wiring;
A gate electrode formed on the same layer as the gate line and connected to the gate line, an active pattern formed on the gate insulating layer to overlap the gate electrode, a drain electrode overlapping a portion of the active pattern, and spaced apart from the drain electrode A thin film transistor including a source electrode overlapping a portion of the active pattern so as to be overlapped;
A P-side electrode formed on the gate insulating layer and electrically connected to the source electrode, a PIN semiconductor pattern formed on the P-side electrode, and an N-side electrode formed on the PIN semiconductor pattern and made of a transparent conductive material. PIN diodes;
A connection electrode upper hole formed on the gate insulating layer to cover the thin film transistor and the PIN diode, and having a connection contact upper hole exposing at least a portion of the data connection part of the drain electrode and a bias contact hole exposing a portion of the N-side electrode; A first insulating layer;
A data line formed on the first insulating layer in a second direction crossing the first direction and electrically connected to the data connection part through the connection electrode upper hole;
A bias line formed on the first insulating layer in the second direction and electrically connected to the N-side electrode through the bias contact hole;
And the PIN diode is formed to be in contact with or overlapping with the data line in plan view. The method of claim 11, wherein the active pattern is
The X-ray detector panel, characterized in that extending to the gate wiring side is partially overlapped with the gate wiring. A gate wiring formed on the base substrate in a first direction;
A gate insulating layer formed on the base substrate to cover the gate wiring;
A gate electrode formed on the same layer as the gate line and connected to the gate line, an active pattern formed on the gate insulating layer to overlap the gate electrode, a drain electrode overlapping a portion of the active pattern, and spaced apart from the drain electrode A thin film transistor including a source electrode overlapping a portion of the active pattern so as to be overlapped;
A P-side electrode formed on the gate insulating layer and electrically connected to the source electrode, a PIN semiconductor pattern formed on the P-side electrode, and an N-side electrode formed on the PIN semiconductor pattern and made of a transparent conductive material. PIN diodes;
A connection electrode upper hole formed on the gate insulating layer to cover the thin film transistor and the PIN diode, and having a connection contact upper hole exposing at least a portion of the data connection part of the drain electrode and a bias contact hole exposing a portion of the N-side electrode; A first insulating layer;
A data line formed on the first insulating layer in a second direction crossing the first direction and electrically connected to the data connection part through the connection electrode upper hole;
A bias line formed on the first insulating layer in the second direction and electrically connected to the N-side electrode through the bias contact hole;
And the active pattern extends toward the gate line to partially overlap the gate line. The method of claim 11 or 13, wherein the drain electrode, the source electrode and the P-side electrode is made of a first metal material,
The data line and the bias line are X-ray detector panel, characterized in that made of a second metal material having a lower resistance than the first metal material. 15. The method of claim 11 or 13, further comprising a second insulating layer formed on the first insulating layer to cover the data wiring and the bias wiring,
And the first and second insulating layers are made of an inorganic insulating material. The data insulating layer of claim 11 or 13, further comprising a data insulating layer formed between the gate insulating layer and the first insulating layer so as to cover the thin film transistor and having a P-side electrode contact hole exposing a portion of the source electrode. Including more,
And the P-side electrode is formed on the data insulation layer and electrically connected to the source electrode through the P-side electrode contact hole.

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