KR20120069943A - Data input apparatus of semiconductor integrated circuit - Google Patents

Data input apparatus of semiconductor integrated circuit Download PDF

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Publication number
KR20120069943A
KR20120069943A KR1020100131288A KR20100131288A KR20120069943A KR 20120069943 A KR20120069943 A KR 20120069943A KR 1020100131288 A KR1020100131288 A KR 1020100131288A KR 20100131288 A KR20100131288 A KR 20100131288A KR 20120069943 A KR20120069943 A KR 20120069943A
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KR
South Korea
Prior art keywords
data input
semiconductor integrated
integrated circuit
level
unit
Prior art date
Application number
KR1020100131288A
Other languages
Korean (ko)
Inventor
임상국
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100131288A priority Critical patent/KR20120069943A/en
Publication of KR20120069943A publication Critical patent/KR20120069943A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects

Abstract

PURPOSE: A data input device of a semiconductor integrated circuit is provided to reduce current consumption of the semiconductor integrated circuit by simultaneously latching and amplifying a signal using a latch unit without a level shifter. CONSTITUTION: A data input unit(210) receives a data strobe signal from the outside. A delay unit(220) controls timing for synchronizing the data strobe signal from the data input unit with a clock inputted from the outside. A latch unit(230) simultaneously latches the data strobe signal outputted from the delay unit and amplifies a voltage level.

Description

DATA INPUT APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a data input device for semiconductor integrated circuits that can reduce layout size and current consumption of semiconductor integrated circuits.

In a semiconductor integrated circuit, data is input or stored in each cell having a structure of one transistor and one capacitor, or output stored data. The input / output operation of data, which is a basic function of the semiconductor integrated circuit, is performed by turning on / off a word line serving as a gate input of a transistor in a cell.

Among such semiconductor integrated circuits, a data input device mainly receives an address signal or data and delivers the same to an internal memory core region.

1 is a block diagram illustrating a data input device of a conventional semiconductor integrated circuit.

Referring to FIG. 1, a data input device 100 of a conventional semiconductor integrated circuit includes a data input buffer 110 for receiving an input signal from an external level, and a level for amplifying a level of a signal input to the input buffer 110. The shifter 120, a delay unit 130 delaying an input signal amplified by the level shifter 120 and a latch unit receiving a signal output from the delay unit 130 and a clock input from the outside ( 140).

Here, the data input buffer 110 and the level shifter 120 are driven by receiving the level of the output power supply voltage VDDQ, but the delay unit 130 and the latch unit 140 input the level of the power supply voltage VDD. Is driven.

However, the conventional semiconductor integrated circuit includes a plurality of level shifters 120, and the level shifters 120 are composed of a plurality of PMOS transistors, so that a large amount of current capacitance causes a large current consumption. There is a problem that occurs.

In addition, the conventional semiconductor integrated circuit includes a level shifter 120 for each input pad, thereby increasing the layout size.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data input device of a semiconductor integrated circuit which eliminates the level shifter, thereby reducing the current consumption and reducing the layout size of the semiconductor device.

The data input device of a semiconductor integrated circuit according to the present invention adjusts a timing for synchronizing a clock inputted from a data input unit for receiving a data strobe signal input from the outside and the data strobe signal output from the data input unit. And a latch unit for latching the data strobe signal output from the delay unit and amplifying a voltage level.

The data input device of the semiconductor integrated circuit according to the present invention can reduce the current consumption of the semiconductor integrated circuit by eliminating the level shifter that is conventionally provided and simultaneously performing the latching and amplifying operation of the signal using the latch unit.

In addition, since the data input device of the semiconductor integrated circuit according to the present invention does not need to include a level shifter provided for each input pad, the layout size of the semiconductor integrated circuit can be reduced.

1 is a block diagram showing a data input device of a conventional semiconductor integrated circuit;
2 is a block diagram illustrating a data input device of a semiconductor device according to an embodiment of the present invention; and
3 is a circuit diagram illustrating a latch unit in a data input device of a semiconductor integrated circuit according to an exemplary embodiment of the present invention.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a data input device of a semiconductor device according to an embodiment of the present invention.

2, a data input device 200 of a semiconductor device according to an embodiment of the present invention may include a data input unit 210, a delay unit 220, and a latch unit 230.

The data input unit 210 is an input buffer that receives a data strobe signal DQS from the outside. In this case, the data input unit 210 receives and drives the level of the output power voltage VDDQ.

The delay unit 220 is a timing for synchronizing the data strobe signal DQS output from the data input unit 210 with a clock, that is, to set up a setup time or a hold time. will be. At this time, the delay unit 220 is also driven to receive the level of the output power supply voltage (VDDQ).

The latch unit 230 receives and latches the clock input from the outside and the data strobe signal DQS output from the delay unit 220, and amplifies the level of the output power voltage VDDQ to supply the power voltage VDD. Amplify to the level of.

Here, unlike the related art, since the data input device 200 according to the exemplary embodiment of the present invention is driven by receiving the level of the output power voltage VDDQ up to the delay unit 220, current consumption may be reduced.

Looking at the operation characteristics of the latch unit 230 in detail as shown in FIG.

3 is a circuit diagram illustrating a latch unit in a data input device of a semiconductor integrated circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 3, in the data input device 200 of a semiconductor integrated circuit in accordance with an embodiment of the present invention, the latch unit 230 has a structure in which the input levels of the input signals in and inb are differentially amplified. .

Referring to the operation characteristics of the latch unit 230 having the above structure, when the data strobe signal DQS output from the delay unit 220 is input to the fifth NMOS transistor N5, the latch unit 230 is in. It is enabled.

Here, when the data strobe signal DQS is input and the latch unit 230 is enabled, the fifth NMOS transistor N5 is turned on and the input levels of the first input signal in and the second input signal inb are turned on. By comparing this, the level of the output power supply voltage VDDQ is amplified to the level of the power supply voltage VDD. That is, when the first input signal in is at a high level, the second input signal inb has a low level, and when the third NMOS transistor N3 is turned on, when the first input signal in is at a low level, the second input signal inb has a low level. The second input signal inb has a high level and the fourth NMOS transistor N3 is turned on.

As described above, when the first input signal in is at the high level, the third transistor N3 is turned on and when the first NMOS transistor N1 is also turned on to pull down the first node n1, the second PMOS is turned on. Transistor P2 is also turned on. When the second PMOS transistor P2 is turned on to increase the amount of current flowing through the second node n2, the second NMOS transistor N2 is also turned on so that the output out is pulled up to the level of the power supply voltage VDD. do. In addition, when the first input signal in is at the low level, the fourth transistor N4 is turned on so that the output out is pulled down to the level of the ground voltage VSS.

As a result, the latch unit 230 receives a level of the output power supply voltage VDDQ and outputs a signal that transitions the level of the output power supply voltage VDDQ to the level of the power supply voltage VDD and the ground voltage VSS level. . That is, the latch unit 230 amplifies the swing width of the signal.

The data input device 200 of the semiconductor integrated circuit according to the embodiment of the present invention eliminates the level shifter that is conventionally provided and performs the voltage level shifting operation in the latch unit 230 to reduce current consumption of the semiconductor integrated circuit. Can be saved.

In addition, since the data input device 200 of the semiconductor integrated circuit according to the exemplary embodiment of the present invention does not need to separately provide a level shifter for each input pad, the layout size of the semiconductor integrated circuit can be reduced.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

200: data input device 210: data input buffer unit
220: delay unit 230: buffer unit

Claims (4)

A data input unit receiving a data strobe signal input from the outside;
A delay unit for adjusting a timing for receiving the data strobe signal output from the data input unit and synchronizing with a clock input from the outside; And
A latch unit for latching the data strobe signal output from the delay unit and amplifying a voltage level;
Data input device of a semiconductor integrated circuit comprising a. The method of claim 1, wherein the data input unit and the delay unit,
A data input device of a semiconductor integrated circuit, which is driven by receiving a level of an output power supply voltage. The method of claim 1, wherein the latch unit,
A data input device of a semiconductor integrated circuit, which is driven by receiving a level of a power supply voltage. The method of claim 3, wherein the latch unit,
And amplifying and outputting a level of an output power supply voltage to a level of the power supply voltage.
KR1020100131288A 2010-12-21 2010-12-21 Data input apparatus of semiconductor integrated circuit KR20120069943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100131288A KR20120069943A (en) 2010-12-21 2010-12-21 Data input apparatus of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100131288A KR20120069943A (en) 2010-12-21 2010-12-21 Data input apparatus of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
KR20120069943A true KR20120069943A (en) 2012-06-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100131288A KR20120069943A (en) 2010-12-21 2010-12-21 Data input apparatus of semiconductor integrated circuit

Country Status (1)

Country Link
KR (1) KR20120069943A (en)

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