JP2013236157A - Input circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver circuit that allows reducing the consumption current and circuit area compared to the background art, and to provide a semiconductor device having the same.SOLUTION: An input circuit comparing a reference voltage and an input signal and detecting whether the input signal is in a high level or a low level includes: a receiver circuit having a first input buffer receiving the input signal, a first transistor interposed between the first input buffer and a first power-supply potential, and a second transistor interposed between the first input buffer and a second power-supply potential lower than the first power-supply potential; and a current control circuit controlling the amount of current flowing through the first and second transistors on the basis of the reference voltage.

Description

  The present invention relates to an input circuit that receives a signal and a semiconductor device including the same.

  A semiconductor device, in particular, a DRAM (Dynamic RAM) is used as a main memory of an information processing device such as a personal computer or a server, and therefore, faster data writing and reading are required.

  Therefore, for example, in a DDR-SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory), a SSTL (Stub Series Termination Logic), which is a small amplitude interface, is used to transmit and receive data signals, DQS (data strobe) signals, and the like at high speed. Is adopted.

  In SSTL, in order to receive a signal having a small amplitude, a differential single input for receiving a signal by a differential circuit is employed. A receiver circuit that receives data receives a predetermined reference voltage VREF (for example, a voltage that is ½ of the power supply voltage VDDI of the receiver circuit) and a data signal, and the high level or low level of the data signal is compared with the reference voltage VREF. Is detected.

  A receiver circuit corresponding to such SSTL is also proposed in Patent Document 1, for example.

  FIG. 13 is a circuit diagram showing a configuration of a receiver circuit described in Patent Document 1. In FIG.

  As shown in FIG. 13, the receiver circuit described in Patent Document 1 receives a data signal DIN and a reference voltage VREF by a PMOS transistor and an NMOS transistor connected to each other by a totem pole connection, amplifies the difference voltage, and internally The data is output as data (iDIN). The receiver circuit is provided corresponding to a plurality of data input / output (DQ) terminals. FIG. 13 shows a configuration example including two receiver circuits corresponding to data signals DIN0 and DIN1 input from DQ0 and DQ1 terminals (not shown).

Japanese Patent Laid-Open No. 11-266152

  The receiver circuit corresponding to the SSTL described above requires a comparison circuit (differential circuit) for comparing the reference voltage VREF with the voltage of the received data signal. For this reason, for example, the number of transistors increases as compared with a CMOS (Complementary Metal Oxide Semiconductor) input, that is, a receiver circuit that receives data by an inverter circuit, resulting in an increase in current consumption. Further, the provision of the differential circuit increases the circuit area.

  Therefore, in a semiconductor device provided with a receiver circuit corresponding to SSTL, particularly a semiconductor memory device such as a DDR-SDRAM, a receiver circuit having a differential circuit for each DQ terminal by providing a large number of data input / output (DQ) terminals. Is provided, current consumption and circuit area increase in proportion to the number of DQ terminals.

  On the other hand, when data is received by a general inverter circuit, there is a wide dead zone because the threshold voltage of the receiver circuit is determined by the threshold voltage of the PMOS transistor and NMOS transistor connected to totem pole. Therefore, it is difficult to reduce the amplitude of the transmission signal, and high-speed data transmission becomes difficult. In addition, when a signal having a large amplitude is transmitted, current consumption necessary for signal transmission also increases.

An input circuit according to the present invention is an input circuit that compares a reference voltage with an input signal and detects whether the input signal is at a high level or a low level,
A first input buffer for receiving the input signal;
A first transistor inserted between the first input buffer and a first power supply potential; and a second transistor inserted between the first input buffer and a second power supply potential lower than the first power supply potential. A receiver circuit including a plurality of transistors;
A current control circuit for controlling the amount of current flowing through the first and second transistors based on the reference voltage;
Have

On the other hand, the semiconductor device of the present invention is
The input circuit;
A data terminal connected to the input circuit and receiving the input signal from the outside;
A voltage terminal connected to the input circuit and supplied with the reference voltage from the outside;
Is provided.

Alternatively, the current control circuit is
A second input buffer to which the reference voltage is input;
A third transistor inserted between the second input buffer and the first power supply potential;
A fourth transistor inserted between the second input buffer and the second power supply potential;
The output voltage of the second input buffer is compared with a predetermined internal voltage, and the current flowing through the third and fourth transistors is controlled so that the output voltage of the second input buffer becomes equal to the internal voltage. A comparison circuit to
A semiconductor device to which a first external power supply voltage and a second external power supply voltage lower than the first external power supply voltage are supplied from the outside,
The current control circuit includes an internal power supply voltage generation circuit that is supplied with the first external power supply voltage, compares the reference voltage with the internal voltage, and outputs the first power supply potential;
The reference voltage is generated based on the second external power supply voltage.

  According to the present invention, current consumption and circuit area can be reduced as compared with the receiver circuit of the background art.

FIG. 11 is a block diagram illustrating a configuration example of a semiconductor device. 1 is a circuit diagram illustrating a configuration example of an input circuit according to a first embodiment. FIG. FIG. 3 is a circuit diagram illustrating a configuration example of a comparison circuit illustrated in FIG. 2. FIG. 2 is a circuit diagram illustrating a configuration example of an input circuit and a WRITE FIFO circuit illustrated in FIG. 1. It is a wave form diagram which shows the simulation result of the setup time and hold time of a FIFO circuit in Slow conditions. It is a wave form diagram which shows the simulation result of the setup time and hold time of a FIFO circuit in MAX conditions. It is a graph which shows the comparison result of the linearity with respect to the reference voltage of the conventional receiver circuit and the receiver circuit of this invention. It is a wave form diagram which shows the simulation result of the setup time and hold time in a FIFO circuit when changing the deviation | shift amount of the reference voltage VREF and VDDI / 2. It is a wave form diagram which shows the simulation result of the setup time and hold time in a FIFO circuit when changing the deviation | shift amount of the reference voltage VREF and VDDI / 2. It is a circuit diagram which shows the example of 1 structure of the input circuit of 2nd Embodiment. It is a circuit diagram which shows one structural example of the input circuit of 3rd Embodiment. It is a schematic diagram which shows an example of terminal arrangement | positioning in a semiconductor device. 10 is a circuit diagram showing a configuration of a receiver circuit described in Patent Document 1. FIG.

Next, the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. FIG. 1 shows a configuration example of an SDRAM (Synchronous Dynamic RAM) as a semiconductor device. The present invention is not limited to SDRAM, but can be applied to other semiconductor devices such as SRAM (Static RAM), PRAM, and flash memory.

  A semiconductor device 1 shown in FIG. 1 includes a memory cell array 11, an X decoder 12, a Y decoder 13, an address input circuit 14, a command decoder 15, a WRITE FIFO circuit 16, a READ FIFO circuit 17, an input circuit 18, an output circuit 19, and an internal voltage generation circuit. 20

  The memory cell array 11 includes a large number of memory cells that hold data (stored information).

  The input circuit 18 includes data DIN0 to n input from an external semiconductor device or the like via a plurality of data input / output (DQ0 to n) terminals, and an external semiconductor device or the like via a data strobe (DQS / B) terminal. Are provided with a plurality of receiver circuits for receiving the data strobe signal input from the. The input circuit 18 is supplied with the external power supply voltage VDD as the power supply voltage VDDI and is supplied with the external power supply voltage VSS as the power supply voltage VSSI. Further, the reference voltage VREF is supplied to the input circuit 18. The reference voltage VREF is, for example, a voltage ((VDD−VSS) / 2) that is ½ of the power supply voltage VDDI of the receiver circuit.

  The output circuit 19 includes a plurality of output buffer circuits that transmit data to an external semiconductor device or the like via a plurality of data input / output (DQ0 to n) terminals. The external power supply voltage VDD is supplied to the output circuit 19 as the power supply voltage VDDQ, and the external power supply voltage VSS is supplied as the power supply voltage VSSQ. For example, 1.5 V is supplied as the external power supply voltage VDD, for example, and the external power supply voltage VSS is set to 0 V (ground potential) lower than the external power supply voltage VDD, for example.

  The WRITE FIFO circuit 16 includes a first in first out (FIFO) circuit that latches data received from the input circuit 18 and is written in synchronization with an external clock.

  The READFIFO circuit 17 includes a FIFO circuit that latches data read from the memory cell and supplies the data to the output circuit 19 in synchronization with an external clock.

  The address input circuit 14 includes an input buffer circuit that receives an address signal ADD supplied from the outside.

  The command decoder 15 decodes externally supplied control signals (chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WEN, etc.), X decoder 12, Y decoder 13. A command signal for operating the WRITE FIFO circuit 16, the READ FIFO circuit 17, the input circuit 18, the output circuit 19, and the like is output.

  The X decoder 13 decodes the X address (row address) supplied from the address input circuit 14, and the Y decoder 12 decodes the Y address (column address) supplied from the address input circuit 14. A memory cell from which data is read or a memory cell to which data is written is specified by signals after decoding by the X decoder 13 and the Y decoder 12.

  The internal power supply generation circuit 25 generates predetermined internal power supply voltages VODPP, VARY, VPERI, and the like used in the semiconductor device from the external power supply voltages VDD and VSS, and supplies the generated internal power supply voltages to a required internal circuit. The internal power supply voltages VODPP, VARY, VPERI, etc. can be generated by a known step-down circuit or step-up circuit.

  FIG. 2 is a circuit diagram illustrating a configuration example of the input circuit according to the first embodiment.

As shown in FIG. 2, the input circuit 18 according to the first embodiment includes a plurality of receiver circuits 181 _{0 to} 181 _n provided corresponding to the DQ0 to _n terminals provided in the semiconductor device 1 shown in FIG. And a current control circuit 182.

The receiver circuits 181 _{0 to} 181 _n have a plurality of inverter circuits (first input buffers) INV _{0 to n} that receive data (input signals) DIN _{0 to n} input via the DQ _{0 to n} terminals, and a power supply voltage VDDI ( P-type transistors (first transistors) DP0 to DPn inserted between nodes supplied with the first power supply potential) and inverter circuits INV0 to INVn, and a power supply voltage VSSI (second power supply potential) are supplied. And N-type transistors (second transistors) DN0 to DNn inserted between the inverter circuits INV0 to INV, respectively. The PMOS transistors and NMOS transistors constituting the inverter circuits INV0 to INVn are formed, for example, such that the respective threshold voltages are VDDI / 2.

The current control circuit 182 includes a replica circuit 183 and a comparison circuit 184. The replica circuit 183 is inserted between the inverter circuit (second input buffer) INVa that receives the reference voltage VREF and outputs the adjusted reference voltage VREFINB, the node to which the power supply voltage VDDI is supplied, and the inverter circuit INVa. And a P-type transistor (third transistor) TP, a node to which the power supply voltage VSSI is supplied, and an N-type transistor (fourth transistor) TN inserted between the inverter circuit INVa. As shown in FIG. 2, the replica circuit 183 includes the same circuit as each of the receiver circuits 181 _{0 to} 181 _n .

  The comparison circuit 184 compares the reference voltage VREFINB output from the replica circuit 183 with the internal voltage iVREF, and currents flowing through the P-type transistor TP and the N-type transistor TN so that the reference voltage VREFINB and the internal voltage iVREF are equal. A current control signal ING for controlling the amount is output. The internal voltage iVREF is generated by, for example, dividing the power supply voltage VDDI supplied to the input circuit 18 (VDDI / 2) by a voltage generation circuit including two resistors having the same resistance value.

That is, the comparison circuit 184 is output from the inverter circuit INVa even if the reference voltage VREF fluctuates due to noise or the like, or the logical threshold value of the PMOS transistor and NMOS transistor of the inverter circuit INVa is shifted due to process variation or the like. The amount of current flowing through the P-type transistor TP and the N-type transistor TN is controlled so that the reference voltage VREFINB becomes equal to the ideal internal voltage iVERF, and the logical threshold value of the inverter circuit INVa is corrected. The current control signal ING output from the comparison circuit 184 is also input to the P-type transistors DP0 to DPn and the N-type transistors DN0 to DNn included in the receiver circuits 181 _{0 to} 181 _n . The wiring for transmitting the current control signal ING to the P-type transistors DP0 to DPn and the N-type transistors DN0 to DN0 to n is connected with a compensation capacitor of about 100 pF, for example, in order to reduce potential fluctuation during circuit operation. ing.

  Hereinafter, for example, the current control circuit 182 under the conditions of the power supply voltage VDDI = 1.2V, the reference voltage VREF = 0.6V, the logic threshold value of the P-type transistor TP and the N-type transistor TN = 0.6V, and the internal voltage iVREF = VDDI / 2. Will be described.

  Under the above conditions, when the reference voltage VREFINB output from the inverter circuit INVa is about VDDI / 2 which is an ideal value, the current control signal ING output from the comparison circuit 184 is also about VDDI / 2.

  On the other hand, when the reference voltage VREFINB output from the inverter circuit INVa is lower than VDDI / 2 under the above conditions, the comparison circuit 184 adjusts the current control signal ING so that the reference voltage VREFINB becomes VDDI / 2. Specifically, the comparison circuit 184 lowers the current control signal ING lower than VDDI / 2 to increase the amount of current flowing through the P-type transistor TP and decrease the amount of current flowing through the N-type transistor TN, so that VREFINB = Adjust to VDDI / 2.

  In the above condition, when the reference voltage VREFINB output from the inverter circuit INVa is higher than VDDI / 2, the comparison circuit 184 adjusts the current control signal ING so that the reference voltage VREFINB becomes VDDI / 2. Specifically, the comparison circuit 184 increases the current control signal ING higher than VDDI / 2 to reduce the amount of current flowing through the P-type transistor TP and increase the amount of current flowing through the N-type transistor TN, so that VREFINB = Adjust to VDDI / 2.

  As described above, the comparison circuit 184 corrects the logical threshold value of each transistor of the inverter circuit INVa.

Here, the current control signals ING output from the comparison circuit 184, since the input to the P-type transistor DP0~n and N-type transistor DN0~n included in the receiver circuit 181 ₀ ～181 _n, the receiver circuit 181 ₀ ~ Similarly to the P-type transistor TP and the N-type transistor TN of the replica circuit 183, the logic threshold values of the P-type transistors DP0- _n and the N-type transistors DN0- _n of 181n are corrected by the current control signal ING.

That is, if the level of the data signal DIN0 to _n input to the inverter circuits INV0 to _n of the receiver circuits 181 _{0 to} 181 _n and the reference voltage VREF input to the inverter circuit INVa of the replica circuit 183 are the same voltage, In the inverter circuits INV0 to INVa, similarly to the inverter circuit INVa, the amount of current flowing through the P-type transistors DP0 to DPn and the N-type transistors DN0 to DNn is controlled so that the voltage of the internal data signals iDIN0 to n becomes VDDI / 2. The

As a result, the inverter circuits INV0 to INn of the receiver circuits 181 _{0 to} 181 _n are input based on the amount of current flowing through the P-type transistors DP0 to DPn and the N-type transistors DN0 to DNn, that is, based on the reference voltage VREF. It is determined whether the data signal DIN is at a high level or a low level.

  For example, when the data signal DIN0 input to the inverter circuit INV0 is higher than the reference voltage VREF, the amount of current flowing through the N-type transistor DN0 increases, so that the inverter circuit INV0 outputs a low level as the internal data signal iDIN0. When the level of the data signal DIN0 is lower than the reference voltage VREF, the amount of current flowing through the P-type transistor DP0 increases, so that the inverter circuit INV0 outputs a high level as the internal data signal iDIN0. The operation of other inverter circuits INV1 to INVn is the same.

According to the present embodiment, each of the receiver circuits 181 _{0 to} 181 _n includes the inverter circuits INV0 to INVn, and the P-type transistors DP0 to DPn and the N-type transistors inserted between the inverter circuits INV0 to INVn and the power supply voltage. By controlling the amount of current flowing through the transistors DN0 to DN by the current control circuit 182, the receiver circuits 181 _{0 to} 181 _n have the input data signal DIN at the high level or the low level with reference to the reference voltage VREF. Can be determined. Therefore, it is not necessary to provide a differential circuit for each of the receiver circuits 181 _{0 to} 181 _n . Therefore, current consumption and circuit area of the semiconductor device including the receiver circuits 181 _{0 to} 181 _n can be reduced.

  FIG. 3 is a circuit diagram showing a configuration example of the comparison circuit shown in FIG.

  As shown in FIG. 3, the comparison circuit 184 is realized by a differential amplifier circuit that amplifies and outputs the difference voltage between the reference voltage VREFINB output from the replica circuit 183 and the internal voltage VDDI / 2.

  When the reference voltage VREFINB = VDDI / 2, the comparison circuit 184 outputs a voltage of about VDDI / 2 as the current control signal ING. At this time, the P-type transistors DP0 to DPn, the P-type transistor TP, the N-type transistors DN0 to DNn, and the N-type transistor TN are substantially in the ON state, and substantially equal current flows through them.

  When the reference voltage VREFINB <VDDI / 2, the comparison circuit 184 outputs a current control signal ING lower than VDDI / 2. At this time, the amount of current flowing through the P-type transistor TP increases according to the current control signal ING, and the amount of current flowing through the N-type transistor TN decreases, so that the reference voltage VREFINB increases. This control is continued until the reference voltage VREFINB = VDDI / 2.

  When the reference voltage VREFINB> VDDI / 2, the comparison circuit 184 outputs a current control signal ING higher than VDDI / 2. At this time, the amount of current flowing through the P-type transistor TP decreases according to the current control signal ING, and the amount of current flowing through the N-type transistor TN increases, so that the reference voltage VREFINB decreases. This control is continued until the reference voltage VREFINB = VDDI / 2.

  FIG. 4 is a circuit diagram showing a configuration example of the input circuit and the WRITE FIFO circuit shown in FIG.

  Although not shown in FIG. 2, the semiconductor device of this embodiment receives the data strobe signals DQS and DQSB by the receiver circuit 181 similar to that for the data signals DIN0 to DIN shown in FIG. 2, as shown in FIG. In addition, the amount of current flowing through the P-type transistor and the N-type transistor is controlled by the current control signal ING received from the current control circuit 182.

The internal signals iDQS, iDQSB, and iDIN0 to n output from the receiver circuit 181 are input to the corresponding FIFO circuits 186 _{0 to} 186 _n via the level conversion circuit 185. As shown in FIG. 4, the receiver circuit 181 and the level conversion circuit 185, and the level conversion circuit 185 and the FIFO circuits 186 _{0 to} 186 _n may include an intermediate buffer. The level conversion circuit 185 may be included in the input circuit 18 illustrated in FIG. 1 or may be included in the WRITE FIFO circuit 16.

  Since the power supply voltages VDDI (= VDD) and VSSI (= VSS) are supplied to the input circuit 18 shown in FIG. 1, the internal power supply voltage VPERI supplied to another peripheral circuit, for example, the FIFO circuit 186, is supplied. And the voltage may be different (for example, VPERI <VDDI). In that case, the level conversion circuit 185 is used to convert the signal amplitude from VDDI to VPERI. Internal power supply voltage VPERI is generated by a step-down circuit included in internal voltage generation circuit 20 shown in FIG. When the power supply voltage used in the peripheral circuit is equal to VDDI, the level conversion circuit 185 is not necessary.

  5 and 6 illustrate a receiver circuit 181 including a differential circuit (see FIG. 12) described in Patent Document 1 (hereinafter sometimes abbreviated as QCR) and an inverter circuit of the present invention. The result of simulating the setup time and hold time of the FIFO circuit 186 in the provided configuration (hereinafter sometimes abbreviated as INV) is shown. FIG. 5 shows the FIFO when the external power supply voltage VDD (VDD = VDDI = 1.5 V) supplied to the semiconductor device becomes VDDI = 1.35 V (hereinafter referred to as the Slow condition) within the guaranteed operating range. The simulation results of the setup time and hold time of the circuit 186 are shown. FIG. 6 shows a FIFO circuit 186 when the external power supply voltage VDD (VDD = VDDI = 1.5 V) of the semiconductor device becomes VDDI = 1.6 V (hereinafter referred to as “MAX condition”) within the guaranteed operating range. The simulation results of setup time and hold time are shown. FIG. 5 shows a simulation result when VDDI = 1.35V, VREF = 0.7, VIH = 0.7V ± 0.15V, and tCK = 1.2 ns as Slow conditions. FIG. 6 shows the simulation result when VDDI = 1.6V, VREF = 0.7, VIH = 0.7V ± 0.15V, and tCK = 1.2 ns as MAX conditions.

  For example, in a semiconductor device in which terminals (PAD) such as a power supply, DQ, DQS, DQSB, and DML are arranged as shown in FIG. 12, the wiring length from each DQ terminal to the FIFO circuit 186, and the DQS terminal to the FIFO circuit The wiring lengths up to 186 are not necessarily equal to each other.

For example, in the DQ7 terminal farthest from the DQS terminal and the DQ2 terminal closest to the DQS terminal, there is a difference in delay time until the DQS and DQSB signals reach the FIFO circuit 186 ₇ and the FIFO circuit 186 ₂ corresponding to the respective terminals. Arise. The WFIFO shown in FIGS. 5 and 6 is the WRITE FIFO circuit 16 shown in FIG. 1, and DQ2 and DQ7 show the FIFO circuit corresponding to the DQ2 terminal and the FIFO circuit corresponding to the DQ7 terminal. The ISSI shown in FIGS. 5 and 6 indicates current consumption.

  Since the receiver circuit 181 of the present invention is configured not to directly compare the reference voltage VREF and the data signal DIN but indirectly using the replica circuit 183, each receiver circuit described in Patent Document 1 is provided for each receiver circuit. As compared with the configuration including the differential circuit, there is a slight difference in the delay time to the FIFO circuit 186. However, as shown in FIG. 5, the difference is as small as 70 ps, which does not affect the operation.

  Further, as shown in FIGS. 5 and 6, the current described in Patent Document 1 in which the current flowing in the receiver circuit includes the QCR in both the Slow condition (VDDI = 1.35 V) and the MAX condition (VDDI = 1.6 V). However, the configuration with INV of the present invention is lower, and the difference is particularly remarkable (about 1/5) under the MAX condition, and the receiver circuit of the present invention is more effective in reducing current consumption than the conventional one. I understand that.

  FIG. 7 is a graph showing a comparison result of linearity with respect to the reference voltage of the conventional receiver circuit and the receiver circuit of the present invention.

Logical Vt (V) indicated by the vertical axis in FIG. 7 indicates a determination voltage for determining whether the data signal input to the receiver circuit is at a low level or a high level. That is, Logical Vt (V) on the vertical axis in FIG. 7 corresponds to a threshold for determining whether the data signal DIN is at a low level or a high level with respect to the reference voltage VREF, and the reference voltage VREF. It is shown that it can be detected more accurately if it matches.

As shown in FIG. 7, in the conventional receiver circuit, when the reference voltage VREF approaches VSS, the resistance value of the NMOS transistor to which the reference voltage VREF is input is seen and the potential rises. When DIN = VREF, the data signal DIN Since the resistance ground value of the NMOS transistor to which is inputted is also increased, the logical Vt (V) is shifted from the reference voltage VREF. The same applies when the reference voltage VREF approaches VDDI.

On the other hand, in the receiver circuit 181 of the present invention, the logical Vt (V) almost coincides with the reference voltage VREF in a wide range, and it can be seen that the determination can be made accurately.

  Note that the receiver circuit 181 of the present invention includes P-type transistors DP0 to DPn inserted between the inverter circuits INV0 to INV and the power supply voltage VDDI or the inverter circuits INV0 to INV0 according to the amount of deviation between the reference voltage VREF and VDDI / 2. Since the amount of current flowing through one of the N-type transistors DN0 to DN0 inserted between n and the power supply voltage VSSI is small, there is a possibility that the delay amount of the signal output to the next stage circuit is large. For example, FIG. 8 shows a case where the deviation amount between the reference voltage VREF and VDDI / 2 is changed in the configuration described in Patent Document 1 including QCR and the configuration including INV of the present invention (VREF = VDDI × 45%, VDDI (× 49%, VDDI × 50%, VDDI × 51%, VDDI × 55%) The simulation results of the setup time and hold time in the FIFO circuit are shown. Note that VDDI = 1.35V, VREF = 0.7, VIH = 0.7V ± 0.15V, and tCK = 1.2 ns (Slow condition). FIG. 9 described later also has the same conditions.

  As shown in FIG. 8, there is no problem when the deviation amount between the reference voltages VREF and VDDI / 2 is 50%, but when the deviation amount is 45%, the timing is not completely met.

Therefore, when the transistor size of the inverter circuits INV0 to INVn is changed from W = 3u to W = 6u (transistor size is doubled), the failure of the duty ratio can be suppressed as shown in FIG. This is because by increasing the transistor size and increasing the amount of current flowing through the inverter circuits INV0 to INV, the drive capability of the transistors is increased, and the inverter circuits INV0 to INVn are driven at a higher speed. Thus, by increasing the transistor size of the inverter circuits INV0 to INVn, the setup time and hold time in the subsequent FIFO circuit can be secured.
(Second Embodiment)
FIG. 10 is a circuit diagram illustrating a configuration example of the input circuit according to the second embodiment.

  As shown in FIG. 10, the semiconductor device according to the second embodiment has two types of external power supply voltages (for example, a first external power supply voltage VDD1 = 1.8V and a second external power supply voltage VDD2 = 1). .2V) is supplied. As the reference voltage VREF, for example, the voltage VDD2 / 2 is supplied from the outside. As such a semiconductor device to which two types of external power supply voltages are supplied, there is, for example, Mobile DRA / DDR4.

The current control circuit 188 included in the input circuit according to the second embodiment includes the replica circuit 183, the receiver circuits 181 _{0 to} 181 _n and the voltage generation circuit that generates the internal voltage iVREF shown in FIG. In this configuration, the voltage 2VREF is supplied. Therefore, the current control circuit 188 includes an internal power supply voltage generation circuit 189 that generates the internal power supply voltage 2VREF. Note that the voltage generation circuit included in the current control circuit 188 of the present embodiment generates 2VREF / 2 as the internal voltage iVREF.

  The internal power supply voltage generation circuit 189 includes, for example, a differential amplifier and a transistor that amplifies the output current of the differential amplifier, and a reference voltage VREF (= VDD2 / 2) supplied from the outside to the positive input terminal of the differential amplifier. A constant internal power supply voltage 2VREF is output from the transistor by inputting and negatively feeding back the internal voltage 2VREF / 2 generated by the voltage generation circuit to the negative input terminal. Since other configurations of the input circuit and the configuration of the semiconductor device are the same as those of the first embodiment, description thereof is omitted.

Even with the configuration as shown in FIG. 10, the same effect as when the input circuit 18 shown in FIG. 2 is used can be obtained. Further, the input circuit 18 of the present embodiment can suppress variations in the reference voltage VREF supplied from the outside and the internal voltage iVREF (= 2VREF / 2) generated by the voltage generation circuit.
(Third embodiment)
FIG. 11 is a circuit diagram illustrating a configuration example of the input circuit according to the third embodiment.

  The input circuit of the third embodiment shown in FIG. 11 has a configuration corresponding to the specification in which the reference voltage VREF is not supplied from the outside like the input circuit of the first embodiment shown in FIG. That is, the current control circuit 187 is configured to supply the internal voltage iVREF generated by the voltage generation circuit to the inverter circuit INVa as the reference voltage VREF. The other configuration is the same as that of the current control circuit 182 shown in FIG. Even with the configuration as shown in FIG. 11, the same effect as when the input circuit 18 shown in FIG. 2 is used can be obtained.

1 semiconductor device 11 memory cell array 12 X decoder 13 Y decoder 14 address input circuit 15 a command decoder 16 WRITEFIFO circuit 17 READFIFO circuit 18 input circuit 19 output circuit 20 the internal voltage generating circuit 181,181 ₀ ~181 _n receiver circuits 182,187,188 Current control circuit 183 Replica circuit 184 Comparison circuit 185 Level conversion circuit 186, 186 _{0 to} 186 _n FIFO circuit 189 Internal power supply voltage generation circuit

Claims (9)

An input circuit that compares a reference voltage with an input signal and detects whether the input signal is at a high level or a low level,
A first input buffer for receiving the input signal;
A first transistor inserted between the first input buffer and a first power supply potential; and a second transistor inserted between the first input buffer and a second power supply potential lower than the first power supply potential. A receiver circuit including a plurality of transistors;
A current control circuit for controlling the amount of current flowing through the first and second transistors based on the reference voltage;
An input circuit. The current control circuit is
A second input buffer to which the reference voltage is input;
A third transistor inserted between the second input buffer and the first power supply potential;
A fourth transistor inserted between the second input buffer and the second power supply potential;
The output voltage of the second input buffer is compared with a predetermined internal voltage, and the current flowing through the third and fourth transistors is controlled so that the output voltage of the second input buffer becomes equal to the internal voltage. A comparison circuit to
The input circuit according to claim 1.   The input circuit according to claim 1, wherein the first input buffer and the second input buffer are inverter circuits. The comparison circuit is
The current control signal for controlling the current amount of the first, second, third, and fourth transistors is commonly output to the first, second, third, and fourth transistors. 3. The input circuit according to 3. The reference voltage is
5. The input circuit according to claim 1, wherein the input circuit is (first power supply potential−second power supply potential) / 2. The current control circuit is
The input circuit according to claim 1, further comprising a voltage generation circuit that generates the reference voltage. An input circuit according to any one of claims 1 to 5,
A data terminal connected to the input circuit and receiving the input signal from the outside;
A voltage terminal connected to the input circuit and supplied with the reference voltage from the outside;
A semiconductor device comprising: A semiconductor device comprising the input circuit according to claim 2, wherein a first external power supply voltage and a second external power supply voltage lower than the first external power supply voltage are supplied from the outside,
The current control circuit includes an internal power supply voltage generation circuit that is supplied with the first external power supply voltage, compares the reference voltage with the internal voltage, and outputs the first power supply potential;
The semiconductor device according to claim 1, wherein the reference voltage is generated based on the second external power supply voltage.   The semiconductor device according to claim 8, wherein the reference voltage is the second external power supply voltage / 2, and the internal voltage is (first power supply potential−second power supply potential) / 2.

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