KR20120066526A - Method for testing of semiconductor memory device - Google Patents

Method for testing of semiconductor memory device Download PDF

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Publication number
KR20120066526A
KR20120066526A KR1020100127901A KR20100127901A KR20120066526A KR 20120066526 A KR20120066526 A KR 20120066526A KR 1020100127901 A KR1020100127901 A KR 1020100127901A KR 20100127901 A KR20100127901 A KR 20100127901A KR 20120066526 A KR20120066526 A KR 20120066526A
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KR
South Korea
Prior art keywords
data
cell
voltage
test
column line
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KR1020100127901A
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Korean (ko)
Inventor
이원희
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020100127901A priority Critical patent/KR20120066526A/en
Publication of KR20120066526A publication Critical patent/KR20120066526A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing

Abstract

PURPOSE: A method for testing a semiconductor memory device is provided to prevent faults and extend write recovery time to be close to a specification of a DRAM. CONSTITUTION: The first data is written in all cells and an amount of charges of the first data is increased by bumping up a reference voltage. The second data is written in a first column line among all cells. A test operation is repeated by increasing a cell plate voltage supplied to the first column line to a first voltage level. The second data written in the first column line is read and the sensing margin of the second data is decreased by bumping up the cell plate voltage in the entry of a bump up test mode.

Description

Method for testing of semiconductor memory device

Embodiments of the present invention relate to a test method for a semiconductor memory device, and more particularly, to a technology for effectively screening a write recovery time (tWR) failure of a semiconductor memory device.

BACKGROUND With the development of technology in computer systems and electronic communication fields, semiconductor memory devices used for storing information are gradually becoming lower in cost, smaller in size, and larger in capacity. In addition, the demand for energy efficiency is also increasing, and the development of technology for semiconductor devices is being made in the direction of suppressing unnecessary current consumption.

In general, a cell array that stores data of a DRAM device has a structure in which many cells each consisting of one NMOS transistor and a capacitor are connected to word lines and bit lines connected in a mesh shape.

The operation of a typical DRAM device will be briefly described.

First, an address signal input to a row address buffer is input while a ras (/ RAS) signal, which is a main signal for operating a DRAM device, is changed to an active state (low level). At this time, a row decoding operation of decoding one of the row address signals and selecting one of the word lines of the cell array is performed.

At this time, data of the cells connected to the selected word line is loaded on the bit line pair BL // BL consisting of the bit line and the complementary bit line. Then, the sense amplifier enable signal indicating the operation time of the sense amplifier is enabled to drive the sense amplifier driving circuit of the cell block selected by the row address.

The sense amplifier bias potential is shifted to the core potential Vcore and the ground potential Vss by the sense amplifier driving circuit to drive the sense amplifier. When the sense amplifier starts to operate, the bit line pairs BL and / BL, which have kept a small potential difference between them, transition to a large potential difference.

After that, the column decoder turns on the column transfer transistor that transfers the data of the bit line to the data bus line in response to the column address, thereby transferring the data transferred to the bit line pair BL // BL to the data bus. It is delivered to the line (DB, / DB) to be output to the outside of the device.

On the other hand, in such a semiconductor memory device, after a write command is input, a write operation must be completed until a precharge command is generated. This operation section is referred to as a write recovery time (tWR).

In particular, when writing data of '0' during such write operation, and then writing data of inversion level, that is, data of '1' again, the sensing speed is disadvantageous for the sense amplifier operating at the internal voltage level VCORE. can do. For this reason, the margin of tWR which is a write operation characteristic may fall.

1A to 1D are diagrams for describing a test method of a conventional semiconductor memory device.

First, as shown in FIG. 1A, data of '1' is written to all cells formed in a lattice form on a row (X) line and a column (Y) line.

Thereafter, as shown in FIG. 1B, data of '0' is written in units of columns. And, when writing data in column unit, tWR is applied.

For example, when writing data of '0' for (X, Y) in the column unit, cells with (0,0) through (Xmax, 3) in row (X) and column (Y) lines Up to '0' data is written in one column line.

Then, data of '0' written in the cell is read for (X, Y) in the column unit.

As shown in FIG. 1C, the data of '1' is rewritten to the same column line that reads the data of '0'. After increasing the column unit, the data of '0' is written in the next column line, and the data of '1' is rewritten in the same column line after the data of '0' is read.

Next, as shown in FIG. 1D, the above process is repeated by increasing the column unit to Ymax.

However, the conventional test method of the semiconductor memory device is to overwrite the conventional tWR time excessively in order to screen the tWR (write recovery time) failure continuously occurs during mounting and customer stages. Over screen may occur.

In addition, in the conventional tWR screen test, the write or read operation is performed under the environment in which the patterns of the memory cells are formed in columns, and the tWR performance of the cells is poor by inserting up to tWR while using a pattern that makes the noise vulnerable. And sensing related defects are screened at the same time.

Here, when the tWR is inserted during a bad test, the cell's threshold voltage (Vt) window margin is gradually decreasing due to technology shrink.

An embodiment of the present invention is characterized in that it is possible to effectively screen the failure while increasing the write recovery time (tWR) as close as possible to the specification of the DRAM.

A test method of a semiconductor memory device according to an embodiment of the present invention includes: writing first data in all cells and bumping up a reference voltage to increase an amount of charge of the first data; Writing second data to a first column line of all cells; Repeating the test operation by increasing the cell plate voltage supplied to the first column line to a first voltage level; Bumping up the cell plate voltage upon entering the bump up test mode to reduce sensing margin of the second data; And reading second data written to the first column line.

The embodiment of the present invention provides an effect of effectively screening the defect while increasing the write recovery time (tWR) as close as possible to the specification of the DRAM.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1A to 1D are diagrams for explaining a test method of a conventional semiconductor memory device.
2A to 2D are diagrams for describing a test method of a semiconductor memory device according to an embodiment of the present invention.
3 to 5 illustrate each control operation in detail in a test method of a semiconductor memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are diagrams for describing a test method of a semiconductor memory device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, data of '1' is written to all cells formed in a lattice form on the row (X) line and the column (Y) line. At this time, a bump of the reference voltage Vrefc is used to create an environment in which data is difficult to be inverted in the cell.

That is, during the test operation, the reference voltage Vrefc is bumped up to write '1' data to the cell. In this case, the data '1' is pre-written in the cell, and afterwards, it is difficult to invert the data in a cell in which the write property of the data '0' is poor.

For example, in the embodiment of the present invention, an example of increasing the level of the reference voltage Vrefc by 0.1V during the bump up operation of the reference voltage Vrefc will be described.

Thereafter, as shown in FIG. 2B, the bump operation of the reference voltage Vrefc is terminated, and data of '0' is written to the cell in units of columns. In this case, tWR is applied when data is written to a cell in column units.

For example, when writing data of '0' for (X, Y) in the column unit, cells with (0,0) through (Xmax, 3) in row (X) and column (Y) lines Up to '0' data is written in one column line.

Subsequently, upon entering the test mode, the cell plate voltage VCP is bumped up to supply the core voltage VCORE, and the entry and exit of the test mode are repeated. Here, the cell plate voltage VCP corresponds to a plate voltage applied to one end of a capacitor included in the unit cell.

That is, after the data '0' is written to the cell when the test mode is entered, the bump up and bump down operations of the cell plate voltage VCP are repeated before the read data '0' is read.

Accordingly, the sensing margin ΔV of the cell data may be reduced during the test operation. That is, the operation of bumping up and bumping down the cell plate voltage VCP is repeated to maximize the response to the difference between the sensing margin (ΔV) of the normal cell and the fail cell.

Next, a test mode bumping up the cell plate voltage VCP is entered, and data of '0' written in the cell is read for (X, Y) in column units.

Subsequently, the test mode of bumping up the cell plate voltage VCP is terminated and the reference voltage Vrefc is bumped up.

For example, in the embodiment of the present invention, an example of increasing the level of the reference voltage Vrefc by 0.1V during the bump up operation of the reference voltage Vrefc will be described.

In addition, in the embodiment of the present invention, during bump up operation of the reference voltage Vrefc or during bump up operation of the cell plate voltage VCP, the level is set such that there is no problem in operation for each device and the level is increased.

As shown in FIG. 2C, the data of '1' is rewritten to the same column line that reads the data of '0'. In addition, after writing the data of '0' in the next column line by increasing the column unit, the test process described in FIG. 2B is repeated for the corresponding column line.

Next, as shown in Figure 2d, the above process is repeated by increasing the unit of the column line to Ymax.

The embodiment of the present invention having such an operation process can effectively screen tWR cell defects while increasing tWR as close as possible to the specifications of the DRAM and increase the upper limit of the threshold voltage of the cell to increase the threshold of the cell threshold voltage (Vt). The window can be obtained.

To this end, an embodiment of the present invention 1) bumping up the reference voltage Vrefc during the write operation of the data '1', and 2) cell plate voltage when the cell data is read after the write operation of the data '0'. And bumping up the VCP, and 3) repeating the operation of entering and exiting the test mode by setting the cell plate voltage VCP to the core voltage VCORE level after writing the data '0'.

These three operation processes will be described in detail with reference to FIGS. 3 to 5 as follows.

First, FIG. 3 is a diagram for describing an operation process of bumping up the reference voltage Vrefc during a write operation of data '1'.

Referring to FIG. 3, a write voltage is supplied to a cell as shown in (A) during a normal write operation of data '1'. In the write operation of the normal data '0', the write voltage is not supplied to the cell as in (B).

On the other hand, in the test process according to the embodiment of the present invention, in order to bump up the reference voltage Vrefc, the amount of write voltage supplied to the cell is increased as in (C) to increase the amount of charge stored in the cell. At this time, the amount of voltage that is increased in the test mode is greater than ΔVrefc than the amount of write voltage supplied to the cell when the normal data '1' is stored.

Subsequently, data '0' may not be completely written to a cell in which the write characteristic of the data '0' is poor, as in (D). That is, the data '1' is pre-written in the cell, and afterwards, an environment in which data is hard to be inverted is created in the cell in which the write property of the data '0' is poor.

The test mode according to an exemplary embodiment of the present invention is for testing tWR of data '0' based on the bit line BL among the bit line BL and the bit line bar BLB.

FIG. 4 is a diagram for describing an operation process of bumping up the cell plate voltage VCP when the cell data is read after the write operation of data '0'.

Referring to FIG. 4, before the read of data '0', the potential of the cell plate voltage VCP has the bit line precharge voltage VBLP level as in (E).

Subsequently, when bumping up the cell plate voltage VCP, the potential of the cell plate voltage VCP increases to be increased by ΔVCP than the bit line precharge voltage VBLP. Accordingly, the sensing margin ΔV of the cell data '0' may be reduced during the test operation.

FIG. 5 is a diagram for describing an operation of repeating an operation of entering and exiting a test mode by setting a cell plate voltage VCP to a core voltage VCORE level after writing data '0'.

Referring to FIG. 5, it can be seen that the potential of the cell maintains a normal state as in the ideal case (G). In other words, even if the cell plate voltage VCP repeatedly performs the bump-up operation in the ideal case, it can be seen that there is almost no change in the cell potential.

At this time, when data '0' is written to the cell, the cell plate voltage VCP maintains the bit line precharge voltage VBLP.

After the data '0' is written in the cell, the test is performed by setting the cell plate voltage VCP to the core voltage VORE level. Then, the test mode is repeatedly entered and exited.

On the other hand, when performing the test operation as in the embodiment of the present invention, the normal cell changes the cell potential as shown in (H), and the cell vulnerable to write changes the potential of the cell as shown in (I).

That is, in the test mode, the potential of the cell plate voltage VCP varies differently according to the amount of charge remaining in the cell during the bump up operation of the cell plate voltage VCP. Accordingly, even if the potential of the cell changes by ΔV ', the sensing margin is further reduced in a cell that is more susceptible to light such as (I) than a normal cell such as (H).

In a cell vulnerable to light, such as (I), the sensing margin decreases as the bump up test operation of the cell plate voltage VCP is repeated.

Claims (10)

Writing first data to all cells and bumping up a reference voltage to increase the amount of charge of the first data;
Writing second data on a first column line of all the cells;
Repeating a test operation by increasing the cell plate voltage supplied to the first column line to a first voltage level;
Reducing the sensing margin of the second data by bumping up the cell plate voltage upon entering a bump up test mode; And
And reading the second data written to the first column line. The method of claim 1, wherein the first data is data '1'. The test method of claim 1, wherein the second data is data '0'. The test method of claim 1, wherein the first voltage is at a core voltage level. The method of claim 1, further comprising: reading out the second data
And bumping up the reference voltage with respect to the second column line adjacent to the first column line. The method of claim 5, wherein the writing of the second data line to the second column line, repeating the test operation, bumping up the cell plate voltage, and reading the second data are performed. The test method of the semiconductor memory device further comprises. The method of claim 1, further comprising: reading out the second data
And writing the first data to the first column line. The method of claim 1, wherein each step is performed while increasing column lines for all the cells. The method of claim 1, wherein the cell plate voltage has a level higher than a bit line precharge voltage during a bump up operation of the cell plate voltage. The method of claim 1, wherein the test operation is to test a write recovery time (tWR) of the second data with respect to the bit lines of all the cells.
KR1020100127901A 2010-12-14 2010-12-14 Method for testing of semiconductor memory device KR20120066526A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114187955A (en) * 2022-01-10 2022-03-15 长鑫存储技术有限公司 Method, device and equipment for testing memory array and storage medium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114187955A (en) * 2022-01-10 2022-03-15 长鑫存储技术有限公司 Method, device and equipment for testing memory array and storage medium
CN114187955B (en) * 2022-01-10 2023-09-05 长鑫存储技术有限公司 Method, device, equipment and storage medium for testing memory array

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