KR20120065257A - Semiconductor test device - Google Patents

Abstract

PURPOSE: A semiconductor testing device is provided to match the timing of low speed side pattern data with the timing of high speed side pattern data in a hold release process by simply controlling hardware. CONSTITUTION: A high speed block(120) generates pattern data by executing a test program with a hold state command according to a relatively high speed rate signal. A low speed block(130) generates pattern data by executing the test program with the hold state command according to a relatively low speed rate signal. A controller(112) transmits a hold release signal to only the low speed block. A hold control circuit(140) transmits the hold release signal to only the high speed block by delaying the preset timing from the transmission timing of the hold release signal to the low speed block.

Description

Semiconductor Test Equipment {SEMICONDUCTOR TEST DEVICE}

TECHNICAL FIELD This invention relates to the semiconductor test apparatus which performs predetermined pattern data and performs an electrical test of a device under test.

The semiconductor test apparatus applies a test signal to a device under test (hereinafter referred to as a device under test (DUT)) and compares a signal obtained from the DUT with a predetermined expected value to perform a test. Such a test signal and an expected value are generated based on predetermined pattern data. The pattern data is output from the TG at a predetermined timing by outputting the pattern address by executing a test program in the PG (Pattern Generator), and inputting the pattern address into the TG (Timing Generator).

In patent document 1, the semiconductor test apparatus provided with said PG and TG is described. As shown in Patent Literature 1, TG is provided in a PE (Pin Electronics) card. The PE card is detachable from the slot of the test apparatus main body, and a plurality of PE cards can be mounted.

In addition, in recent years, the speed of DUT, high functionalization, and the number of pins have increased, so that the number of outputs is insufficient in the existing test apparatus. In such a case, the entire test apparatus may be newly manufactured. However, the semiconductor test apparatus cannot be easily created because it is a large scale apparatus and a high price. In such a case, it is conceivable to add PG and TG. However, since the manufacturing time of the test apparatus body and the technology level at the time of adding the circuit are different, the added circuit is often faster than the existing circuit. Or, in some cases, you might want to add circuitry that runs at high speed to test a highly functional DUT. The semiconductor test apparatus then includes a circuit for generating pattern data at different operating speeds. Hereinafter, a circuit including PG and TG operating at high speed is referred to as a high speed block, and a circuit including PG and TG operating at low speed is referred to as a low speed block.

Since the pattern data must be input to the DUT at the same timing, it is necessary to synchronize the timing of outputting the pattern data in the high speed block and the low speed block. However, in the high speed block and the low speed block, the number of stages of the pipeline is different, and the base clock and the rate (the timing at which the processing elements of the pipeline are operated) are also different. A pipeline is a circuit structure in which processing elements are connected in series and sequentially performs processing for each rate. In the high-speed block, the gate between the pipelines can be increased at the high speed of the base clock. Therefore, if the processing contents are the same, the number of stages of the pipeline can be reduced compared to the low-speed block.

In simple terms, the output of the pattern address by the PG and the output of the pattern data by the TG take the number of stages x rate of the pipelines constituting them. As a result, a difference occurs in the processing time between the high speed block and the low speed block. Therefore, the test program for the PG on the high speed side and the low speed side sets the output of the low speed side pattern address as quickly as the minute corresponding to the difference in the processing time. It is.

Japanese Unexamined Patent Publication No. 2010-133886

However, the test of the DUT has a process called hold. The hold is a process of stopping the progress of the elapsed time of the control operation and holding the outputted pattern data (continue outputting the same pattern data). The operator is configured to release the hold state at an arbitrary timing.

Here, it is necessary to synchronize the high speed side and the low speed side pattern data with respect to the DUT even when it is in the hold state and when the hold state is released. The timing to be in the hold state is set in the test program together with the pattern address, and the hold state can be simultaneously set in the same manner as synchronizing the pattern data.

However, the timing for releasing the hold state cannot be programmed in advance because it is caused by the operator's operation. When the signal for canceling the hold state is input to the high speed block and the low speed block, it takes a time of the number of stages x each rate of the pipeline until the pattern data whose hold is released is output from the timing. In order to synchronize the hold-released pattern data, it is necessary to delay the timing of inputting the release signal to the high speed block and the low speed block by a minute corresponding to the difference in processing time, and a complicated circuit is required to realize this by hardware control. Done.

Therefore, an object of the present invention is to provide a semiconductor test apparatus capable of matching the timing of the high speed side pattern data and the low speed side pattern data at the time of hold release by simple hardware control.

In order to solve the above problems, a representative configuration of a semiconductor test apparatus according to the present invention is a fast block for generating pattern data by executing a test program including a command to be in a hold state according to a relatively high rate signal, and a hold. A low speed block for generating pattern data by executing a test program including a command to be in a state according to a relatively low rate signal, a controller for transmitting a signal for releasing the hold state only to the low speed block, and a hold state with the low speed block And a hold control circuit for delaying a predetermined timing from the timing at which the signal for releasing the signal is transmitted, for transmitting a signal for releasing the hold state in the fast block.

According to the above configuration, the hold release signal is input only to the low speed block, and the hold release signal is input to the high speed block by delaying a predetermined timing based on this. This makes it possible to synchronize the high speed side pattern data and the low speed side pattern data at the time of hold release by simple hardware control.

The hold control circuit is capable of writing a first delay circuit for delaying a predetermined timing, a signal for releasing a hold state from a low speed block, and an asynchronous FIFO for reading out a signal for releasing a hold state from a high speed block. It is preferable that either the low speed block or the high speed block performs a write or read input to the asynchronous FIFO via the first delay circuit.

This makes it possible to read and write in parallel in the high speed block and the low speed block in which the base clocks are different. Then, by performing write or read input via the first delay circuit, the pattern data can be synchronized with a very simple configuration.

The hold control circuit writes a write enable signal to the asynchronous FIFO at a timing at which a test program issues a command to be held in a low speed block, and then delays a predetermined timing to output pattern data of the held state from the low speed block. Read enable to the asynchronous FIFO at a timing at which a predetermined timing is delayed and the pattern data in the held state is outputted from the fast block by issuing a command for which the test program is to be held in the fast block. Preferably, a third delay circuit for recording a signal is provided.

According to the above configuration, the timing of starting writing from the low speed block and the timing of starting reading output from the high speed block can be synchronized with respect to the asynchronous FIFO. This prevents malfunction by reading out and outputting unexpected data.

The first delay circuit is a suspension circuit that waits for a specified number of rates, and the first delay circuit designates a difference between the pipeline stage when passing through the low speed block and the pipeline stage when passing through the high speed block as a suspension value. It is desirable to. In this way, it is possible to synchronize the pattern data by absorbing the difference in processing time between the low speed block and the high speed block by simple hardware control without strictly controlling the time.

According to the present invention, the high speed side pattern data and the low speed side pattern data at the time of hold release can be synchronized by simple hardware control.

BRIEF DESCRIPTION OF THE DRAWINGS The figure explaining the principal part of the semiconductor test apparatus which concerns on this embodiment.
2 is a timing chart of pattern addresses and pattern data on the high speed side and the low speed side;
3 is a schematic configuration diagram illustrating the inside of the hold control circuit.
4 is a time chart illustrating an operation at the start of hold.
5 is a time chart of the suspension.
6 is a time chart at the time of hold release.
7 is a diagram illustrating the number of stages of a pipeline.

EMBODIMENT OF THE INVENTION Preferred embodiment of this invention is described in detail, referring an accompanying drawing below. Dimensions, materials, and other specific numerical values and the like shown in these embodiments are merely examples for facilitating understanding of the invention, and the present invention is not limited except as specifically mentioned. In addition, in this specification and drawing, the same code | symbol is attached | subjected about the element which has the substantially same function and structure, and the overlapping description is abbreviate | omitted and the illustration which is not directly related to this invention omits illustration.

FIG. 1: is a figure explaining the principal part of the semiconductor test apparatus 110 which concerns on this embodiment. The semiconductor test apparatus 110 shown in FIG. 1 applies predetermined pattern data to the DUT 100, and compares the signal obtained from the DUT 100 with a predetermined expected value, and performs a test.

The tester controller 112 starts and ends the test and controls the hold release signal described later. The trigger (signal) of the start and end of the test is transmitted to the start trigger control circuit 114. The hold release signal is transmitted only to the low speed block 130 described later. In addition, the tester controller 112 can operate a command by sending a command from an operation interface (not shown).

When the start trigger control circuit 114 receives the trigger of the test start from the tester controller 112, the start trigger control circuit 114 sends a start trigger for starting the test for the high speed block 120 and the low speed block 130, respectively. At this time, the start trigger control circuit 114 delays the timing so that the pattern data from both sides is input in synchronization with the DUT 100 in consideration of the difference in the processing time of the low speed block and the high speed block, and sends out the start trigger.

The fast block 120 includes PG (hereinafter referred to as high speed PG 122) and TG (hereinafter referred to as high speed TG 124). The high speed PG 122 and the high speed TG 124 are input with a relatively high speed base clock and rate (timing at which the processing elements of the pipe line operate).

The high speed PG 122 is provided with the memory | storage part 122a by which the predetermined | prescribed test program was previously stored. When the high speed PG 122 receives the high speed side start trigger from the start trigger control circuit 114, the high speed PG 122 reads out and executes the test program from the storage 122a. When the test program is executed, a pattern address (hereinafter referred to as a high speed side pattern address) is generated, and this is transmitted to the high speed TG 124 in accordance with a high speed rate signal.

The high speed TG 124 is provided with the memory | storage part 124a by which predetermined test pattern was previously stored. When the high speed TG 124 receives the high speed side address from the high speed PG 122, the high speed TG 124 reads out the pattern data from the storage unit 124a and applies it to the DUT 100.

The low speed block 130 also basically has the same configuration as the high speed block 120 and includes a low speed PG 132 and a low speed TG 134. The low speed PG 132 has a storage unit 132a in which a test program is stored in advance, and the low speed TG 134 has a storage unit 134a in which a test pattern is stored in advance. A relatively low base clock and rate are input to the low speed PG 132 and the low speed TG 134, and processing proceeds according to the low rate signal.

In addition, in the high speed block 120 and the low speed block 130, the number of stages of the pipeline is different, and there is a difference in processing time (the number of rates required for processing). A pipeline is a process that connects processing elements in series and executes internal processing (typically fetching, decoding, executing operations, memory access, writeback, etc.) in parallel. Each processing element operates in units of a rate that is an integer multiple of the base clock (rate is in process time).

2 is a timing chart of pattern addresses and pattern data on the high speed side and the low speed side, and shows outputs of the high speed PG 122, the high speed TG 124, the low speed PG 132, and the low speed TG 134.

Since the outputs of the high speed TG 124 and the low speed TG 134 are inputs to the DUT 100, that is, the output timings t2 and t3 need to be matched. Here, the time difference from the output timing ta1 of the high speed PG 122 to the output timing t2 of the high speed TG 124 is set to d1. Similarly, let the time difference from the output timing tb1 of the low speed PG 132 to the output timing t2 of the low speed TG 134 (consistent with the output timing of the high speed TG 124) be d2. Then, the time difference d1 on the high speed side is shorter than the time difference d2 on the low speed side. For this reason, as described above, the start trigger control circuit 114 transmits the high speed side start trigger at the timing ta1 that has risen from the timing t2 by d1, and the timing tb1 that has risen by the d2 from the timing t2. Transmit a low-speed start trigger.

After receiving the start trigger and starting the high speed block 120 and the low speed block 130 with an appropriate time difference, the synchronized pattern data is continuously output from the high speed TG 124 and the low speed TG 134. This is realized by having the test program executed in the high speed PG 122 and the low speed PG 132 be configured to output synchronized pattern data. In addition, in FIG. 2, while the pattern data b1 is output from the low speed TG 134, three pattern data a1, a2, a3 are output from the high speed TG 124 (of the high speed block 120). The rate length is one third of the rate length of the slow block 130). In this manner, the high speed side can be subdivided from the low speed side to switch the pattern data. However, the start timing of the high speed side pattern a4 is synchronized with the start timing t3 of the low speed side pattern b2.

The timing of starting the hold state is defined in the test program as a command to be in the hold state. Specifically, the pattern address to be held is set in the test program of the high speed PG 122 and the low speed PG 132. These test programs are individual, but are set so that the hold state is simultaneously started on the high speed side and the low speed side (each is set so as to be a hold state in the pattern data started at the same time). In the example of FIG. 2, the hold state is started from the pattern data a4 on the high speed side and the pattern data b2 on the low speed side starting from the timing t3, and the same pattern data is continued until it is explicitly stopped. Output The rate length in the hold state is the same on the high speed side and the low speed side.

Next, the hold control circuit 140, which is a feature of the present embodiment, will be described. The hold control circuit 140 transmits a signal for releasing the hold state to the high speed block 120 by delaying a predetermined timing from the timing at which the signal for releasing the hold state is transmitted to the low speed block 130.

As shown in FIG. 1, a high speed base clock and a rate are input to the hold control circuit 140 from a high speed block 120, and a low speed base clock and a rate are input from a low speed block 130. As described above, the hold release signal is input from the tester controller 112 only to the low speed block 130.

3 is a schematic configuration diagram illustrating the inside of the hold control circuit 140. The hold control circuit 140 has an asynchronous FIFO 142. The asynchronous FIFO 142 is a storage module capable of writing and reading output at different clocks. This makes it possible to read out and write in parallel (at the same time) in the high speed block 120 and the low speed block 130 in which the base clocks are different. In this embodiment, the asynchronous FIFO 142 can record the hold release signal from the low speed PG 132 of the low speed block 130, and read out the hold release signal from the high speed PG 122 of the high speed block 120. You can print However, in the state that is not yet held, the asynchronous FIFO has neither the write nor the read output enabled.

The low speed PG 132 of the low speed block 130 outputs a hold status signal (a signal of being a hold) to the hold control circuit 140 when the test program issues a command to be in the hold state. The hold status signal is written as a write enable signal to the asynchronous FIFO 142 after delaying the predetermined timing in the second delay circuit 148. The second delay circuit 148 is a suspension circuit that waits for a specified number of rates.

4 is a time chart illustrating the operation at the start of the hold, and FIG. 5 is a time chart of the suspension. As shown in Fig. 4, a predetermined processing time is required until the low speed TG 134 outputs the pattern data after the low speed PG 132 outputs the pattern address. This processing time corresponds to the number of stages x the slow rate of a pipeline. The second delay circuit 148 is input with a low speed rate similarly to the low speed block 130. For this reason, as shown in FIG. 5, the suspension value B input to the 2nd delay circuit 148 sets the number of rates to wait, ie, the number of pipeline stages later than the low speed PG 132. As shown in FIG. In other words, the second delay circuit 148 writes the write enable signal to the asynchronous FIFO at the timing of outputting the pattern data in the hold state from the low speed block 130.

In the high-speed PG 122, similarly, when the test program issues a command to be in a hold state, a hold status signal is output to the hold control circuit 140. The hold status signal is written as a read enable signal to the asynchronous FIFO 142 after delaying the predetermined timing in the third delay circuit 150. The third delay circuit 150 is a suspension circuit, which waits for a specified number of rates.

As shown in Fig. 4, a predetermined processing time is required until the high speed TG 124 outputs the pattern data after the high speed PG 122 outputs the pattern address. This processing time corresponds to the stage x high speed of the pipeline. Since the high speed rate is input to the third delay circuit 150, the suspension value C input to the third delay circuit 150 sets the number of pipeline stages later than the high speed PG 122. Usually, since the high speed block 120 has fewer pipeline stages than the low speed block 130, the suspension value C becomes smaller than the suspension value B. FIG. That is, the third delay circuit 150 writes the read enable signal to the asynchronous FIFO 142 at the timing of outputting the pattern data in the hold state from the fast block 120.

Here, since the timing of outputting the pattern data in the hold state from the high speed block 120 and the low speed block 130 is synchronized, the timing of starting recording from the low speed block 130 with respect to the asynchronous FIFO 142, and the high speed. The timing of starting the read output from block 120 can be synchronized. This prevents malfunction by reading and outputting unexpected data.

In the hold state, the high speed PG 122 continuously reads (monitors) data from the asynchronous FIFO 142. The hold status signal output by the low speed PG 132 is monitored by the hold release detection circuit 144.

6 is a time chart at the time of hold release. Since the rate lengths in the hold state are the same on the high speed side and the low speed side, the pattern data on the low speed side and the high speed side are synchronized and have the same length.

When a hold release signal is sent from the tester controller 112 to the low speed PG 132 (timing indicated by broken lines in FIG. 6), the low speed PG 132 finally releases the hold state, and the elapsed time of the test program. Resume progress. At this time, the hold status on the low speed side is also released. The hold release detection circuit 144 outputs a hold release detection signal to the first delay circuit 146 when it detects that the hold status signal has been released.

The first delay circuit 146 is a suspension circuit similar to the second delay circuit 148 or the third delay circuit 150, and writes a hold release detection signal to the asynchronous FIFO 142 after waiting for a specified number of rates. do. Since the asynchronous FIFO 142 is enabled for write and read input, the high speed PG 122 reads out the hold release detection signal from the asynchronous FIFO 142. The high speed PG 122 then releases the hold state last at that rate and resumes the progress of the elapsed time of the test program.

The 1st delay circuit 146 needs to set the suspension value A so that the pattern data of a high speed side and a low speed side may advance and resume simultaneously. Here, the first delay circuit 146 specifies the difference between the number of pipeline stages via the low speed block 130 and the number of pipeline stages via the high speed block 120 as the suspension value (A).

7 is a diagram illustrating the number of stages of a pipeline. In addition, in FIG. 7, PG and TG are not distinguished. First, the hold release signal is inputted to the low speed PG 132, and then there are two stages of pipelines until it is output to the hold release detection circuit 144, so that the number of pipeline stages of the entire low speed block 130 is 20. Shall be. On the other hand, the number of pipa line stages in the high speed block 120 shall be 10 stages. Since it is the first stage in the asynchronous FIFO 142, if the first delay circuit 146 delays the seven stages, the number of stages on the high speed side and the low speed side becomes the same. Therefore, the suspension value A specified as the parameter to the first delay circuit 146 may be set to seven.

Thus, referring to Fig. 6, the hold release signal is provided between the rates of the pattern addresses corresponding to the pattern data (which becomes the last pattern data in the suspended state) output at the same timing on both the low speed side and the high speed side. Therefore, there is no fear of deviation occurring at the low speed side and the high speed side, and the hold state can be released easily and reliably at the same time.

That is, the first delay circuit 146 is composed of a suspension circuit, and the suspension time (A) specifies the difference in the number of stages of the pipeline, so that the processing time of the low speed block and the high speed block is controlled by simple hardware control without strict time control. By absorbing the difference, the pattern data can be synchronized. In addition, this uses the thing with the same rate on a high speed side and a low speed side in a hold state.

As described above, according to the present invention, only the low speed block 130 inputs the hold release signal, and based on this, the hold release signal is input to the high speed block 120 by delaying a predetermined timing. As a result, the high speed side pattern data and the low speed side pattern data at the time of hold release can be synchronized.

As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to this example. Those skilled in the art will be able to conceive various modifications or modifications within the scope described in the claims, and they are naturally understood to belong to the technical scope of the present invention.

The present invention can be used as a semiconductor test apparatus that performs predetermined pattern data to perform an electrical test of a device under test.

100: DUT
110: semiconductor test device
112: Tester Controller
114: Start Trigger Control Circuit
120: high speed block
122: high speed PG
122a: memory
124: high speed TG
124a: memory
130: low speed block
132: low speed PG
132a: memory
134: low speed TG
134a: memory
140: hold control circuit
142: asynchronous FIFO
144: hold release detection circuit
146: first delay circuit
148: second delay circuit
150: third delay circuit

Claims (4)

A high speed block for generating pattern data by executing a test program including a command to be in a hold state according to a relatively high rate signal;
A low speed block for generating pattern data by executing a test program including a command to be in a hold state according to a relatively low rate signal;
A controller for transmitting a signal for releasing a hold state only to the low speed block;
And a hold control circuit for delaying a predetermined timing from the timing at which the signal for releasing the hold state is transmitted to the low speed block and transmitting a signal for releasing the hold state to the high speed block. . The method of claim 1,
The hold control circuit,
A first delay circuit for delaying the predetermined timing;
Has an asynchronous FIFO capable of recording a signal for releasing the hold state from the low speed block, and capable of reading out the signal for releasing the hold state from the high speed block,
Any one of the low speed block or the high speed block performs a write or read input to the asynchronous FIFO via a first delay circuit. The method of claim 2,
The hold control circuit,
Writing a write enable signal to the asynchronous FIFO at a timing at which a test program issues a command to be in a hold state in the low speed block, and then delays a predetermined timing to output pattern data in a hold state from the low speed block. A second delay circuit for
After the test program issues a command for entering the hold state in the high speed block, delaying a predetermined timing to write a read enable signal to the asynchronous FIFO at the timing of outputting the pattern data in the hold state from the high speed block. And a third delay circuit for the semiconductor test apparatus. The method according to claim 2 or 3,
The first delay circuit is a suspension circuit that waits for a specified number of rates,
In the first delay circuit, a difference between the number of pipeline stages passing through the low-speed block and the number of pipeline stages passing through the high-speed block is specified as a suspension value.

Images