KR20120057714A - Cordic processor and method for cordic processing using the same - Google Patents

Abstract

PURPOSE: A cordic processor and a cordic processing method using the same are provided to increase the processing speed of a cordic apparatus by performing each operation of a processor which performs a vectoring process and a rotation process. CONSTITUTION: N processors(510, 520, 530, 540) performs each iteration of input data. An additional processor(570) performs shift process and complement process of the input data. N-1 processing units perform vectoring process or vectoring calculation. The last processing unit performs rotation process or rotation calculation.

Description

CORDIC PROCESSOR AND METHOD FOR CORDIC PROCESSING USING THE SAME}

The present invention relates to a Codic processor that can be used for trigonometric function operations and a codic processing method using the same.

Recently, with the development of various digital devices, research on digital signal processing technology has been actively conducted. Digital signal processing technology has a large application field in various devices that handle audio signals and video signals. The fields of digital signal processing technology include the fields of digital wireless communication, adaptive signal processing, embedded systems, robotics, and animation.

The CORDIC algorithm, which is widely used in such a digital signal processing technology, is an algorithm used for calculating trigonometric functions in various fields of digital signal processing technology. Cordic algorithms can be classified into two types according to their operation. First, a method of calculating a magnitude and a declination of a vector with respect to a given input vector is called a vectoring method. On the other hand, the method of calculating the sign value and the cosine value for a given input declination is called a rotation method.

Jack in 1959. Since proposed by E. Volder, the Codic algorithm has been widely used in the calculation of trigonometric functions. The codec algorithm has the advantage that the area occupied by hardware can be reduced because trigonometric functions can be calculated only by addition and shift operations. However, it is composed of several iterations, and there is a limit to speed improvement due to the characteristics that depend on the result of the previous step in order to perform the result of the next step.

Later, the proposed Lookahead CORDIC algorithm solved the result dependency of the previous step. In the rotation mode, the look-ahead Coddick algorithm performs a comparison operation on the input angle, and finds and applies a set of rotation direction decision bit bits using a lookup table. However, this structure has a disadvantage in that it is limited to the rotation mode, and it also takes a lot of time to compare the input angles to find the lookup table value.

In the present invention, an effective high performance codec structure that can be applied to not only the rotation mode but also the vectoring mode is proposed.

Some embodiments of the present invention provide a Codic device and a Codic operation method using the same that can simultaneously perform a vectoring process and a rotation process while minimizing the result dependency of the previous step.

As a technical means for achieving the above-described technical problem, the processor for performing the codic processing according to the first aspect of the present invention, the input data, the compensation for the input data, the shift value of the input data and the N vectoring processing units and rotation input data (N is a natural number) for performing one or more vectoring processes for one or more of the complements of the shift values of the input data, the complement of the rotation input data, the shift value of the rotation input data, and the rotation And a rotation processing unit for performing a rotation process on the complement of the shift value of the input data and outputting a trigonometric function output value for the input data, wherein the vectoring processing unit and the rotation processing unit are connected in parallel to each vectoring process or the rotation process. The rotation processing unit On the basis of the sign value of the input data and the sign value of the output data of the N vectoring processing of the output value of the rotation processing, and outputs the selected output to the trigonometric function.

In addition, the processor for performing the codic processing according to the second aspect of the present invention, one of the input data, the complement of the input data, the shift value of the input data and the complement of the shift value of the input data Read declination data corresponding to data output from the first vectoring processing unit to the Nth vectoring process (N is a natural number) and the first vectoring processing unit to the N-1 vectoring processing unit among the vectoring processing units. And a declination calculator for outputting the data, wherein the vectoring processing units are connected in parallel to perform respective vectoring processes, and the N-th vectoring processing unit is a code value of the input data and the first vectoring processing unit to the N-1 vectoring processing unit. Any one of the output values of the vectoring process is selected and output based on the sign value of the output data.

In addition, the codic processing method according to the third aspect of the present invention uses a codic processor including a parallel processing rotation processor and a plurality of vectoring processors, and transmits the input data to the first vectoring processor and Y of the input data. Passing the code value of the coordinates to the remaining vectoring processing unit and the rotation processing unit, a shift operation on the input data and the rotation input data, a shift operation on the input data and the rotation input data, and the shift operation Performing a complementary operation on the shift value, transferring a result value of each operation to the remaining vectoring processing unit or the rotation processing unit, and performing the vectoring process based on the input data in the first vectoring processing unit; One or more of the results of the computed operation Performing a vectoring process in the remaining vectoring processor based on the vector and a vectoring process in the first vectoring processor based on the input data, and based on at least one of the result values of the transferred operation. And performing a rotation process, wherein the performing of the rotation process includes a trigonometric function output value among the output values of the plurality of rotation processes based on the sign values of the input data and the sign values of the output data of the vectoring processor. Select to print.

According to the above-described problem solving means of the present invention, by using the look-ahead algorithm, it is possible to resolve the previous step result dependency. Further, in calculating the sine bit, the operations of the processing unit performing the vectoring process and the rotation process are performed in parallel at substantially the same time, thereby improving the processing speed of the Codic device.

According to the experimental results, it can be seen that the codec device of the present invention has a minimum computation time compared to the basic codec device and the compact codec device. In particular, it can be seen that the increase rate of operation time is minimal despite the increase in the bit width, and when the bit width is 24 bits, the performance improvement of 28.1% can be achieved compared to the compact cordic structure.

1 is a diagram for explaining a conventional Codic algorithm.
2 is a view for explaining the operation of the vectoring mode in the Codic algorithm.
3 is a view for explaining the operation of the rotation mode in the Codic algorithm.
FIG. 4 is a view for explaining an embodiment of a lookahead codic structure.
5 is a view showing a cordic apparatus according to an embodiment of the present invention.
6 is a view showing a cordic apparatus according to an embodiment of the present invention.
7A and 7B are diagrams showing the detailed configuration of the Codic device according to an embodiment of the present invention.
8 is a view showing a cordic device according to another embodiment of the present invention.
FIG. 9 is a diagram illustrating equations processed in each iteration step in the Codic device.
10 is a flowchart illustrating a codic operation processing method performed in a codic device according to an embodiment of the present invention.
FIG. 11 illustrates experimental data comparing operation time of a cordial apparatus and another conventional cordic apparatus according to an embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated.

1 is a diagram for explaining a conventional Codic algorithm.

The codec device 100 includes a vectoring unit 110 and a rotation unit 120. The vectoring unit 110 calculates the declination angle and magnitude of the input vector from the input vectors X and Y, and the rotation unit 120 has a sinusoidal value sin θ with respect to the declination calculated by the vectoring unit 110. And the cosine value (cos θ).

The algorithm used by the cordic apparatus 100 may be represented by Equation 1 below.

[Equation 1]

The vectoring unit 110 repeats the operation of rotating the given input vector at a predetermined angle according to a preset condition.

2 is a view for explaining the operation of the vectoring mode in the Codic algorithm.

In the vectoring mode, when the Y component of the input vector is positive, that is, when MSB = 0, the sine bit is set to '-1' and the input vector is rotated by a predetermined angle clockwise. If the Y component of the input vector is negative, that is, MSB = 1, the sine bit σ is set to '1' and the input vector is rotated a predetermined angle in the counterclockwise direction.

As shown, for example, when the input vector is (1, 4), since the Y component is positive, MSB = 0, the sine bit (σ1) is set to '-1', and the input vector is clockwise. Rotate 90 °. Accordingly, the calculated first vector is (4, -1).

Next, since the Y component of the first vector is negative, MSB = 1, and the sine bit sigma 2 is set to '1' and rotates 45 ° clockwise. When the above-described step is multiplied by a preset factor to the X-coordinate value in a repeated state until Y becomes 0, the size of the input vector is calculated. In addition, by adding up the product of the angle rotated in each step and the sine bit, it is possible to calculate the declination angle θ of the input vector.

3 is a view for explaining the operation of the rotation mode in the Codic algorithm.

With the initial vector set to (1,0), if the input declination (θ) is greater than the accumulated angle (Z), the sine bit (σ1) is set to '-1' and the initial vector is counterclockwise. Direction by a predetermined angle. If the input declination θ is smaller than the accumulated angle Z, the sine bit σ 1 is set to '1', and the initial vector is rotated by a predetermined angle clockwise.

As shown, for example, when the input declination θ is 70 °, since there is no accumulated angle Z, the sine bit σ1 is set to '-1', and the initial vector is counterclockwise. Rotate 90 ° in the direction. Next, since the accumulated angle Z is larger than 70 °, the sine bit sigma 1 is set to '1' and rotates the initial vector 45 ° clockwise. By repeating the above operation, multiplying the X and Y coordinates by a preset factor at a point where the inputted declination angle θ is equal to the accumulated angle Z, the sine value of the input declination angle θ and The cosine value can be calculated.

However, in order to calculate the result of the next step using this conventional Codic algorithm, the speed improvement is limited due to the dependency that the result of the previous step must be calculated first to know the direction of rotation (σ, sign bit).

In order to solve this problem, the proposed lookahead CORDIC algorithm performs a comparison operation on the input angle in the rotation mode and finds a corresponding set of direction decision sign bits using a lookup table. Take out and apply.

The lookahead codec structure applies a lookahead codec algorithm that expresses the result of the final vector rotation as an equation for the input vector by substituting the equation of the previous iteration step into the equation of the next step. Equation 2 shows a four-step lookahead vector rotation determinant.

[Equation 2]

4 is a view for explaining an embodiment of the look-ahead codic structure.

As shown, it can be seen that different angles are set for a total of 16 kinds of sign bit bundles ((1,1,1,1) to (0,0,0,0)). However, this structure has a disadvantage in that it is limited to the rotation mode, and it also takes a lot of time to compare the input angles to find the lookup table value.

Meanwhile, the compact CORDIC structure uses a method in which the vectoring and rotation modes share rotation direction sine bits in each iteration step. Therefore, the sine value sin θ and the cosine value cos θ may be directly calculated without separately calculating the declination angle θ. However, since the compact codec algorithm also uses the basic codec algorithm, the result dependency problem of the previous step arises.

FIG. 5 is a diagram illustrating a codic device according to an embodiment of the present invention, and FIG. 9 is a diagram illustrating equations processed by each iteration step in the codic device.

The codec device 500 includes n processing units 510, 520, 530, and 540 which perform respective iterations on the input data X0 and Y0, and shift processing and repair of the input data ( 부가, an additional processing unit 570 for performing complementary processing. The n-1 processing units 510, 520, and 530 of the double front end operate as a vectoring processing unit that performs a vectoring process or a vectoring operation, and the final processing unit 540 operates as a rotation processing unit that performs a rotation process or a rotation operation. .

가 된다. 이때, 제 1 사인 비트(σ1)는 입력 데이터(Y0)의 입력 부호값(MSB0)에 의하여 결정된다. 즉, 입력 부호값(MSB0)이 0인 경우, 사인 비트(σ1)를 ‘-1’로 설정하고, 입력 부호값(MSB0)이 1인 경우, 제 1 사인 비트(σ1)를 ‘1’로 설정한다. 한편, 출력 데이터(Y1)의 부호를 나타내는 제 1 부호값(MSB1)은 이후 단계의 처리부(520, 530, 540)로 전달된다.First, the first processor 510 performs the first iteration of FIG. 9. That is, the output data Y1 of the first processing unit 510 is

Becomes At this time, the first sine bit sigma 1 is determined by the input code value MSB0 of the input data Y0. That is, when the input code value MSB0 is 0, the sine bit σ1 is set to '-1', and when the input code value MSB0 is 1, the first sine bit σ1 is set to '1'. Set it. On the other hand, the first code value MSB1 indicating the sign of the output data Y1 is transferred to the processing units 520, 530, and 540 in a later step.

The additional processor 570 performs the input data, the complement operation on the rotation input data, the shift operation on the input data and the rotation input data, and the complement operation on the shift value calculated through the shift operation. The detailed configuration will be described later.

The second processor 520 performs the second iteration of FIG. 9. To this end, the data selector 524 which selects and outputs any one of an adder 522 for adding up the input data and the input data processed by the additional processor 570 and a plurality of data output from the adder 522. ).

가 되므로, 이러한 연산을 수행하기 위해, 입력 데이터(X0, Y0)에 대한 보수를 사용한다. 한편, 제 1 사인비트(σ1)와 제 2 사인비트(σ2)의 값에 따라 총 4 가지의 출력값이 출력될 수 있으므로, 가산부(522)는 각 경우의 출력값을 산출할 수 있는 총 4개의 가산기를 포함하도록 구성된다.In the second iteration, the output data Y2 of the second processor 520 is

In order to perform this operation, the complement of the input data (X0, Y0) is used. On the other hand, since a total of four output values can be output according to the values of the first sine bit sigma 1 and the second sine bit sigma 2, the adder 522 can calculate the total of four output values for each case. It is configured to include an adder.

The data selector 524 is configured of a multiplexer which selects and outputs specific data among the output values of the four adders according to the input code value MSB0 and the first code value MSB1. Also, the second code value MSB2 indicating the sign of the output data Y2 selected by the data selector 524 is transmitted to the processing units 530 and 540 in a later step. The third sign bit sigma 3 to be used in a later step is determined by the second code value MSB2 of the output data Y2. That is, when the second code value MSB2 is 0, the third sine bit σ3 is set to '-1', and when the second code value MSB2 is 1, the third sine bit σ3 is set. Set to '1'.

The third processor 530 performs the third iteration of FIG. 9. To this end, the data selecting unit 534 which selects and outputs any one of an adder 532 for adding up the input data and the input data processed by the additional processor 570 and a plurality of data output from the adder 532. ).

가 되므로, 이러한 연산을 수행하기 위해, 입력 데이터(X0, Y0)에 대한 보수를 사용한다. 또한, 2^{- 1}성분을 계산하기 위해 부가 처리부(570)의 쉬프터를 통해 쉬프팅된 값을 사용한다. In the third iteration, the output data Y3 of the third processor 530 is

In order to perform this operation, the complement of the input data (X0, Y0) is used. In addition, 2 ^- uses the value through the shifter shifting the additional processing unit (570) for calculating the ^first component.

Meanwhile, since a total of eight output values can be output according to the values of the first sine bit sigma 1, the second sine bit sigma 2, and the third sine bit sigma 3, the adder 532 outputs the output values in each case. It is configured to include a total of eight adders that can be calculated.

The data selector 534 is composed of a multiplexer that selects and outputs specific data among the output values of eight adders according to the input code value MSB0, the first code value MSB1, and the second code value MSB2. . In addition, the third code value MSB3 indicating the sign of the output data Y3 selected by the data selector 534 is transferred to the processing unit 540 in a later step. The fourth sine bit sigma 4 to be used in a later step is determined by the third code value MSB3 of the output data Y3. That is, when the third code value MSB3 is 0, the fourth sine bit σ4 is set to '-1', and when the third code value MSB3 is 1, the fourth sine bit σ4 is set. Set to '1'.

As such, the processor that performs each iteration performs a preset operation. In addition, the sign bit and the sign value generated during the operation are transferred to and used by the processor that performs the next iteration. The processing unit up to just before the nth processing unit 540 is configured to perform an operation according to the vectoring mode.

The n-th processing unit 540 performs n-th iteration. For example, in the case of the Codic device including four processing units, the fourth iteration of FIG. 9 may be performed. To this end, of the plurality of data output from the first adder 542, the second adder 546, and the first adder 542, which add up the input data and the input data processed by the additional processor 570. The first data selector 544 which selects one to output the first output data Xn, and the second output data Yn by selecting any one of a plurality of data output from the second adder 546. It includes a second data selection unit 548 for outputting the.

The n-th processing unit 540 is configured to operate in the rotation mode, similar to the compact cordial structure described above. That is, the processing units in the previous stage operate in the vectoring mode, and the nth processing unit 540 operates in the rotation mode.

To perform this operation, we use complement to the rotation input data. In addition, a value shifted through the shifter of the additional processor 570 is used.

Meanwhile, since the number of sine bits used is n, a total of 2 ^ n output values can be output, and the first adder 542 and the second adder 546 can calculate the output value in each case. It is configured to include a total of 2 ^ n adders.

The first data selector 544 and the second data selector 548 select and output specific data from the output values of 2 ^ n adders according to a total of n code values MSB0, MSB1, ..., MSBn-1. It consists of a multiplexer.

At this time, the output data Xn selected by the first data selector 544 and the output data Yn selected by the second data selector 548 are multiplied by a preset factor, and the input data X0 and Y0. The sine or cosine of) may be represented, respectively.

Now, the present invention will be described in more detail through an embodiment of performing a total of four iterations. However, the present embodiment is only an example for description, and the number of iterations may be sufficiently changed according to a user's selection. For example, two or three unit circuits for performing four iterations illustrated in FIG. 6 to be described later may be connected in series to perform eight or twelve iterations.

6 is a view showing a cordic device according to an embodiment of the present invention, Figures 7a and 7b is a diagram showing a detailed configuration of the cordic device according to an embodiment of the present invention.

The codec device 600 performs four processing units 610, 620, 630, and 640 that perform respective iterations on the input data X0 and Y0, and perform a shift and complement processing on the input data. An additional processing unit 670 is included.

The first to third processing units 610, 620, and 630 are configured to operate according to the vectoring mode, and the fourth processing unit 640 is configured to operate according to the rotation mode.

The first processing unit 710 checks the XOR gate 711 for inputting a value obtained by inverting the MSBs of the first input data X0 and the second input data Y0, and the MSB of the second input data Y0. Inverter 713 for butting and inputting to XOR gate 711, and adder 715 for outputting the output data (Y1) by summing the output of the inverter and the output of the XOR gate 711.

In this case, although one illustrated XOR gate is shown, the number of XOR gates may vary depending on the number of bits of the input data. In other words, if the number of bits of the input data is n, the number of XOR gates connected thereto is also configured.

Meanwhile, the MSB values inverted through the inverter 713 are respectively input to XOR gates provided with the number of input data. This configuration is commonly applied to both the XOR gate and the inverter of FIG. 7 to be described later.

For example, if the first input data X0 is '1101' and the second input data Y0 is '0110', the MSB of the second input data Y0 is '0', so the inverted MSB is Becomes '1'. On the other hand, since the input data is 4 bits, there are four XOR gates, and the XOR result of the MSB inverted with the first input data X0 is' 0010 ', and the addition result of the XOR result and the inverted MSB is' 0011 ', and its MSB value is passed to the next processing unit.

The additional processor 770 includes an XOR gate 771 for generating a 1's complement for the first input data X0, an XOR gate 772 for generating a 1's complement for the second input data Y0, and a first The shifter 780 shifts the input data X0 to the right by 1, the shifter 781 shifts the second input data Y0 to the right by 1, and the shifter 780 to the right through the shifter 780. An XOR gate 773 that generates a one's complement to, and an XOR gate 774 that generates a one's complement to a value shifted by one to the right through the shifter 781.

The additional processor 770 also includes a shifter 782 for shifting the rotation input data Xin r to the right by 1, a shifter 783 to shift the right by 2, and a shifter 784 to shift the right by 3. do. Also included are XOR gates 775, 776, 777, 778 that generate a one's complement of the shifted input data Xin r and shifted values through shifters 782, 783, 784, respectively.

In this case, the rotation input data Xin r represents an input value in the rotation mode described with reference to FIG. 3, and in general, (1,0) enters the input in the rotation mode, so the rotation input data xin r becomes 1. . In the rotation mode, since the Y component is 0, logic logic thereof may be omitted.

The second processor 720 includes four adders 721, 722, 723, and 724. In this case, when the value to be added is three or more, a carry save adder or a compressor adder is included. Can be used to solve the delay problem in carry delivery.

The adder 721 has an output of the XOR gate 771, an output of the XOR gate 772, and a constant 2, and the adder 722 has an output of the XOR gate 771, a second input data Y0 and a constant. 1 is input, adder 723 receives first input data X0 and second input data Y0, and adder 724 outputs the XOR gate 772. The first input data X0 and the constant 1 are input.

That is, the adder 721 receives the complement of the first input data X0, the complement of the second input data Y0, and the constant 2, and the adder 722 is the complement of the first input data X0, and the first. 2 input data Y0 and a constant 1 as inputs, adder 723 takes first input data X0 and second input data Y0 as inputs, and adder 724 receives first input data X0. ) And the complement of the second input data Y0 and the constant 1 are input.

The reason for adding a constant is as follows. In the present invention, the two's complement system is used as a basis. For example, in the case of 4 bits, 0111 represents +7 and 1001 represents -7. In the two's complement system, the? Value is +1, which is 011 (+7), and then +1. That is, 1000 is +1 to 1001 (-7). In this case, 1000 is a one's complement system, and in this case, -7 is 1000. However, if you calculate -7-5-6, it becomes 1001 + 1011 + 1010 with +1 added to 0111, 0101, and 0110, which are bars, 1000, 1010, and 1001, respectively.

In this case, if you calculate as (1000 + 1) + (1010 + 1) + (1001 + 1), you will have 6 terms, so add them in the form of 1's complement and add one for each +1 at a time to add 1000 + 1010 + It can be calculated as 1001 + 3 and treated as four terms. In this way, the constants can be added to implement the two's complement system.

The data selector 725 selects any one of the values output from each of the adders 721, 722, 723, and 724 and transmits the selected one to the processing units 730 and 740 of the next step.

The third processing unit 730 includes a total of eight adders 731, 732, 733, 734, 735, 736, 737, and 738, in which case the carry save adder or the compressor adder is greater than two values. Can be used.

The adder 731 is an output of the XOR gate 773, an output of the XOR gate 772, and a constant 3, and the adder 732 is an output of the XOR gate 771, an output of the XOR gate 773, and an XOR. The output of the gate 774 and the constant 3 are input, the adder 733 is the output of the XOR gate 771, the output of the XOR gate 773 and the constant 2 is input, and the adder 734 is the XOR gate ( The output of the 773, the second input data Y0, the output of the shifter 781 and the constant 1 are input, and the adder 735 is the second input data Y0, the output of the shifter 780 and the shifter 781. ), The adder 736 receives the output of the shifter 781, the first input data X0, and the output of the shifter 780, and the adder 737 of the XOR gate 774. The output, the first input data X0, the output of the shifter 780 and the constant 1 are input, and the adder 738 is an output of the XOR gate 774, an output of the shifter 780, and an output of the XOR gate 772. Output and Take the constant 2 as input.

That is, the adder 731 shifts the value of the first input data X0 shifted to the right by 1, the complement of the second input data Y0, and the value shifted to the right by the second input data Y0. And complement 3, the adder 732 is the complement of the first input data X0, the complement of the value shifted by the first input data X0 to the right by one, and the second input data Y0. Is the complement of the value shifted to the right by 1 and the constant 3 is input, and the adder 733 is the complement of the value shifted to the right by the first input data X0 by 1 and the complement of the second input data Y0. The second input data Y0 is shifted to the right by 1 and the constant 2 is input. The adder 734 shifts the first input data X0 to the right by 1 and the complement of the second input. Shifts the data Y0, the second input data Y0 to the right by 1, and the constant 1 as the input. The adder 735 inputs the value obtained by shifting the second input data Y0, the first input data X0 by 1 to the right, and the value shifted by the second input data Y0 by 1 to the right. The adder 736 inputs a value obtained by shifting the second input data Y0 to the right by one, a value shifted by the first input data X0 and the first input data X0 to the right by one, The adder 737 inputs a complement of a value obtained by shifting the second input data Y0 by 1 to the right, a value obtained by shifting the first input data X0 and the first input data X0 by 1 to the right. The adder 738 is a complement of a value shifted by the second input data Y0 to the right by 1, a value shifted by the first input data X0 by 1 to the right, a complement of the second input data Y0, and Take the constant 2 as input.

The data selector 739 selects one of the values output from each of the adders 731, 732, 733, 734, 735, 736, 737, and 738 and transfers the selected one to the processor 740 of the next step.

The fourth processing unit 740 includes fourteen adders 741, 742, 743, 744, 745, 746, 747, 751, 752, 753, 754, 75, 756, 757, where the sum is 2. If more than one, a carry save adder or a compressor adder can be used. It can also be configured using 16 adders, and two adders are omitted through the optimization process.

The adder 741 compensates for the rotation input data Xin r, the complement of the value shifted by the rotation input data Xin r by 1 to the right, and the complement of the value shifted by the rotation input data Xin r by 3 to the right. And the constant 3 is input, and the adder 742 performs the complement of the rotation input data Xin r, the complement of the value obtained by shifting the rotation input data Xin r to the right by 2, and the rotation input data Xin r to the right. The complement of the value shifted by 3 and the constant 3 are input, and the adder 743 performs the complement of the rotation input data Xin r and the complement and the constant of the value shifted by the rotation input data Xin r by 3 to the right. 1 is input, and the adder 744 inputs the complement and the constant 1 of the value which shifted the rotation input data Xin r by 3 to the right, and the adder 745 receives the rotation input data Xin r and rotation. Input day Compensator for the value shifted by Xin r to the right by 3 and a constant 1 are input, and the adder 746 shifts the rotation input data (Xin r) and rotation input data (Xin r) by 2 to the right. A value obtained by shifting the value and rotation input data Xin r by 3 to the right is input, and the adder 747 shifts the rotation input data Xin r and the rotation input data Xin r by 1 to the right. And a value obtained by shifting the rotation input data Xin r by 3 to the right.

In addition, a value obtained by shifting the rotation input data Xin r by 3 to the right may be directly output by the first data selector 748.

On the other hand, the adder 751 inputs the complement of the value obtained by shifting the rotation input data Xin r and the rotation input data Xin r by 3 to the right and the constant 1, and the adder 752 receives the rotation input data Xin. r), a value obtained by shifting the rotation input data (Xin r) by 2 to the right and a value obtained by shifting the rotation input data (Xin r) by 3 to the right, as inputs, and the adder 753 is a rotation input data (Xin r). ), A value obtained by shifting the rotation input data (Xin r) by 1 to the right, and a value obtained by shifting the rotation input data (Xin r) by 3 to the right, and the adder 754 is a rotation input data (Xin r). Is a complement of a value shifted by 3 to the right and a constant 1, and the adder 755 shifts the complement of the rotation input data Xin r and a value and a constant that shifts the rotation input data Xin r to the right by 3. Mouth 1 The adder 756 shifts the rotation input data Xin r's complement, the value of the shifted input data Xin r to the right by 2, and the rotation input data Xin r to the right by 3 The input of the complement and the constant 3, the adder 757, the complement of the rotation input data (Xin r), the complement of the value shifted the rotation input data (Xin r) by 1 to the right, the rotation input data (Xin Enter the complement of the value shifted r) by 3 to the right.

In addition, a value obtained by shifting the rotation input data Xin r by 3 to the right may be directly output by the second data selector 758.

8 is a view showing a cordic device according to another embodiment of the present invention.

As in the embodiment of FIG. 5, the codec device 800 inputs n processing units 810, 820, 830, and 840 to perform respective iterations on the input data X0 and Y0, where n is a natural number. And an additional processing unit 870 that performs shift processing and maintenance processing on the data.

However, unlike the embodiment of FIG. 5, each processing unit operates as a vectoring processing unit that performs a vectoring process or a vectoring operation. The apparatus further includes a declination calculator 880 that outputs declinations of the input data X0 and Y0 according to data output from the first to n-th processing units.

Each component is the same as the component of FIG. 5, and thus a detailed description thereof will be omitted.

Unlike the embodiment of FIG. 5, the n-th processing unit 840 operates according to a vectoring mode and performs a vectoring operation according to data output from the first to n-th processing units. When the data output from the n th processor 840 is multiplied by a preset factor, the sizes of the input data X0 and Y0 may be calculated.

The declination calculator 880 outputs a declination corresponding to the sign value of the input data Y0 and the sign value of the output data of the first through n-th processing units. For example, declination data in the form of a lookup table is stored, and declination data corresponding to data output from each processing unit is read out and output.

For example, when the sign value of the input data Y0 and the sign value of the output data of the first through n-th processing units, that is, the sine bit are (1, 1, 1, 1), are shown in FIG. Based on what is said, -175.5 ° is read from the lookup table and output. If the sign bit is (1, 1, 1, 0), -147.5 ° is read out from the lookup table and output.

10 is a flowchart illustrating a codic operation processing method performed in a codic device according to an embodiment of the present invention.

First, coordinates that are subject to calculation are input to the Codic device (S910). Typically, two-dimensional coordinates (X, Y) in the form of a vector are input, and a sine and cosine of the vector are finally output.

Next, the input code value of the Y coordinate of the input coordinates is transmitted to the processing unit (510, 520, 530, 540) of each step (S920). If the Y coordinate has a positive value, the input code value MSB0 becomes 0 and the sine bit σ1 is set to '-1'. On the other hand, if the Y coordinate has a negative value, the input code value MSB0 becomes 1 and the sine bit σ 1 is set to '1'.

Next, a complement and shift operation on the input coordinates is performed (S930).

As described in detail with reference to FIGS. 7A and 7B, the operation of shifting the X coordinate to the right by 1 and the operation of shifting the Y coordinate to the right by 1 are performed. In addition, the operation of generating the complement of the X coordinate, the complement of the Y coordinate, and the complement of the shifted value is performed. In addition, an operation of shifting the rotation input coordinates by 1, 2, or 3 to the right is performed. In addition, the operation of generating the complement of the rotation input coordinates and the complement of the shifted value is performed.

Next, in each processing unit, a vectoring process or a rotation process is performed in parallel (S940).

In the present invention, in order to shorten the operation time to the shortest time, the processor performing each iteration is configured to perform the operation in parallel.

The calculation target data is input data or output data of the additional processor 570, and performs an addition operation according to a configuration of an adder implemented in advance.

Next, when the code value is output from each processor, the code value is transmitted to the data selector of the next step processor (S950).

At this time, the addition operation of the previous step processing unit is completed before the addition operation is completed in each processing unit, so that the data selection unit can perform data selection without delay time. For example, before the i-th (i is a natural number) processor completes the addition operation, all of the first to i-th processors complete data output, and the i-th of all the code values of the output data are completed. Transfer the data to the data selection section of the processing section.

Next, the final processing unit outputs a processing result based on the rotation processing (S960).

For example, when the i th (i is a natural number) processor is a final processor, all of the code values of data output from the first to i-1 th processors are transmitted to the data selector of the i th processor. The final processing unit outputs the sine and cosine of the input coordinates based on the sign value of the data output from the processing unit of the previous step.

FIG. 11 illustrates experimental data comparing operation time of a cordial apparatus and another conventional cordic apparatus according to an embodiment of the present invention.

As shown, it can be seen that the codec device of the present invention has a minimum computation time compared to the basic codec device and the compact codec device. In particular, it can be seen that the increase rate of operation time is minimal despite the increase in the bit width, and when the bit width is 24 bits, the performance improvement of 28.1% can be achieved compared to the compact cordic structure.

For reference, the components illustrated in FIGS. 5 to 8 according to an embodiment of the present invention mean software or hardware components such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), and have a predetermined role. Perform them.

However, 'components' are not meant to be limited to software or hardware, and each component may be configured to be in an addressable storage medium or may be configured to reproduce one or more processors.

Thus, as an example, a component may include components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, procedures, and subs. Routines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

Components and the functionality provided within those components may be combined into a smaller number of components or further separated into additional components.

One embodiment of the present invention may also be embodied in the form of a recording medium including instructions executable by a computer, such as program modules, being executed by a computer. Computer readable media can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. In addition, computer readable media may include both computer storage media and communication media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Communication media typically includes computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave, or other transmission mechanism, and includes any information delivery media.

While the methods and systems of the present invention have been described in connection with specific embodiments, some or all of those elements or operations may be implemented using a computer system having a general purpose hardware architecture.

The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

500: cordic device
510, 520, 530, 540: processing unit
522, 532, 542, 546: adding part
524, 534, 544, 548: data selector
570: additional processing unit

Claims (19)

A processor for performing codic processing,
N vectoring (N is a natural number) for performing vectoring processing on one or more of input data, a complement of the input data, a shift value of the input data, and a complement of the shift value of the input data, respectively. Processing unit and
And a rotation processing unit configured to output a triangular function output value for the input data by performing rotation processing on the rotation input data, the compensation for the rotation input data, the shift value of the rotation input data, and the compensation for the shift input data. But
The vectoring processing unit and the rotation processing unit are connected in parallel to perform each vectoring process or rotation process,
And the rotation processor selects and outputs the trigonometric output value among the output values of the rotation process based on code values of the input data and code values of output data of the N vectoring units.
The method of claim 1,
Performing a complement operation on the input data and the rotation input data, a shift operation on the input data and the rotation input data, and a complement operation on the shift value calculated through the shift operation, respectively, and calculating a result value of each operation. And a further processing unit transferring the vectoring processing unit or the rotation processing unit.
The method of claim 1,
The N vectoring processing unit,
A first vectoring processor configured to perform a first vectoring process on the input data and output first output data;
A second vectoring processor configured to perform a second vectoring process on the input data and the complement of the input data, and output second output data;
Wherein the second vectoring processor selects one of the results of the second vectoring process and outputs the second output data based on a sign value of the Y coordinate of the input data and a sign value of the first output data. Incodic processor.
The method of claim 3, wherein
Performing a third vectoring process on the input data, the complement of the input data, the value of shifting the input data to the right by one, and the reward of the shifted value by one, and outputting third output data; 3 includes a vectoring processor,
The third vectoring processor selects any one of the results of the third vectoring process based on a sign value of the Y coordinate of the input data, a sign value of the first output data, and a sign value of the second output data. And output as the third output data.
The method of claim 4, wherein
The rotation processing unit
Rotation processing is performed on the rotation input data, the compensation for the rotation input data, the value for shifting the rotation input data by 1 to 3 to the right, and the compensation for the value for shifting the rotation input data by 1 to 3 to the right. To output the X coordinate data and Y coordinate output data,
A codec for selecting and outputting the X coordinate output data and the Y coordinate output data, respectively, from the results of the rotation process based on the code value of the Y coordinate of the input data and the code values of the first to third output data. Processor.
The method of claim 3, wherein
The first vectoring processor
An inverter for inverting a sign value of the Y coordinate of the input data, at least one XOR gate having the output of the inverter and the X coordinate of the input data as an input, and adding the output of the inverter and the output of the XOR gate to add the first value; A cordic processor comprising an adder for outputting output data.
The method of claim 3, wherein
The second vectoring processor
Four adders each performing a second vectoring process on at least one of said input data and said complement of said input data,
And a data selector configured to select one of output values of the four adders based on a sign value of the Y coordinate of the input data and a sign value of the first output data to output the second output data.
The method of claim 4, wherein
The third vectoring processing unit
Eight adders each performing a third vectoring process on at least one of the input data, the complement for the input data, the value shifted to the right by one, and the reward for the shifted by one; and,
A code selector including a data selector configured to select one of output values of the eight adders based on a sign value of a Y coordinate of the input data and a sign value of the first and second output data to output the third output data; Processor.
The method of claim 5, wherein
The rotation processing unit
For one or more of the rotation input data, the reward for the rotation input data, the value for shifting the rotation input data by 1 to 3 to the right, and the reward for the value for shifting the rotation input data by 1 to 3 to the right. Includes 16 adders each performing a rotation process,
Data selection for selecting and outputting the X coordinate output data and the Y coordinate output data, respectively, from among the output values of the 16 adders based on the code value of the Y coordinate of the input data and the code values of the first to third output data. Codic processor containing a wealth.
The method of claim 1,
And the trigonometric output value is multiplied by a preset factor and converted into a sine or cosine value for the input data.
The method according to any one of claims 7 to 9,
3. The codec processor of claim 1, wherein the adder having three or more pieces of data inputted therein is a carry save adder or a compressor adder.
A processor for performing codic processing,
A first vectoring processor to Nth for performing vectoring processing on at least one of input data, a complement of the input data, a shift value of the input data, and a complement of the shift value of the input data, respectively; Is a natural number)
A declination calculator configured to read and output declination data corresponding to data output from the first vectoring processor to the N-th vectoring processor among the vectoring processor,
Each vectoring processing unit is connected in parallel to perform each vectoring process,
And the N-th vectoring processor selects and outputs one of an output value of the vectoring process based on a code value of the input data and a code value of output data of the first to N-th vectoring processors.
The method of claim 12,
An additional processing unit which performs a complement operation on the input data, a shift operation on the input data, and a complement operation on the shift value calculated through the shift operation, and transfers the result value of each operation to the vectoring processor. Includes a Codic Processor.
The method of claim 12,
And a value output from the N-th vectoring processor is multiplied by a preset factor and converted into magnitude data of the input data.
In the Codic processing method using a Codic processor including a rotation processor and a plurality of vectoring processor connected in parallel,
Transmitting the input data to the first vectoring processor and simultaneously transmitting the sign value of the Y coordinate among the input data to the remaining vectoring processor and the rotation processor;
Performing a complement operation on the input data and the rotation input data, a shift operation on the input data and the rotation input data, and a complement operation on the shift value calculated through the shift operation, and calculating a result value of each operation. Transferring to the remaining vectoring processor or the rotation processor; and
Simultaneously performing a vectoring process on the basis of the input data by the first vectoring processor, and performing a vectoring process on the remaining vectoring processor based on at least one of the result values of the transferred operation;
Performing a vectoring process on the basis of the input data by the first vectoring processor and performing a rotation process on the rotation processing unit based on at least one of the result values of the transferred operation,
The performing of the rotation process may include selecting and outputting a trigonometric function output value from among output values of a plurality of rotation processes based on code values of the input data and code values of output data of the plurality of vectoring processors.
The method of claim 15,
The vectoring process may be performed by the remaining vectoring processor.
Performing a second vectoring process on the input data and the complement of the input data; and
Selecting one of the results of the second vectoring process and outputting the second output data based on a sign value of the Y coordinate of the input data and a sign value of the first output data which is an output result of the first vectoring processor. step
Cordic processing method comprising a.
17. The method of claim 16,
The vectoring process may be performed by the remaining vectoring processor.
Performing a third vectoring process on the input data, the complement for the input data, the value shifted to the right by one and the complement to the shifted value by one; and
Based on the sign value of the Y coordinate of the input data, the sign value of the first output data, and the sign value of the second output data, one of the results of the third vectoring process is selected to output the third output data. Steps to
Cordic processing method comprising a.
The method of claim 17,
The performing of the rotation process in the rotation processing unit
Rotation processing is performed on the rotation input data, the compensation for the rotation input data, the value for shifting the rotation input data by 1 to 3 to the right, and the compensation for the value for shifting the rotation input data by 1 to 3 to the right. Steps to perform and
Selecting and outputting the X coordinate output data and the Y coordinate output data, respectively, from the results of the rotation process based on the code value of the Y coordinate of the input data and the code values of the first to third output data. Cordic processing method comprising.
The method of claim 15,
And calculating a sine or cosine of the input data by multiplying a trigonometric output value output in the rotation processing unit by a preset factor.

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