KR20120056210A - Driving method of stereoscopic image display device - Google Patents

Abstract

PURPOSE: A driving method of a three-dimensional image display apparatus is provided to improve image quality by suppressing degradation of the image quality. CONSTITUTION: A first frame period is comprised of a right-eye image display period(310) and a left-eye image display period(320). The right-eye image display period is comprised of sub frame periods(SF1R-SF4R). The right-eye image display period comprises a first color display period(311), a second color display period(312), a third color display period(313), and a black display period(314). The left-eye image display period is comprised of sub frame periods(SF1L-SF4L). The left-eye image display period comprises a first color display period(321), a second color display period(322), a third color display period(323), and a black display period(324). A first color signal is recorded in a pixel during the first color display period. Red color is displayed during the first color display period. Green color is displayed during the second color display period. Blue color is displayed during the third color display period.

Description

DRIVING METHOD OF STEREOSCOPIC IMAGE DISPLAY DEVICE}

One embodiment of the present invention relates to a display device and a driving method of the display device.

In addition, in this specification, the semiconductor device refers to the general apparatus which can function by utilizing semiconductor characteristics, and a semiconductor circuit, a memory device, an imaging device, a display device, an electro-optical device, an electronic device, etc. are all semiconductor devices.

In recent years, the development of the display apparatus which can visually recognize a stereoscopic image (three-dimensional image) using a liquid crystal display device, an electroluminescent display device (also called an EL display device), etc. It's going on.

As the liquid crystal display device capable of visually visualizing a three-dimensional image, for example, a display device that perceives a two-dimensional image in three dimensions by using parallax in both eyes of a person. Can be mentioned. In the example of the display device, the left eye image and the right eye image are alternately displayed by the pixel portion, and the viewer visually recognizes the image through glasses having shutters corresponding to both eyes. At this time, when the display image is an image for the left eye, the shutter corresponding to the right eye of the glasses is closed to block light incident on the right eye of the viewer, and when the display image is an image for the right eye, The shutter is closed to block light incident on the viewer's left eye. As a result, the two-dimensional image is pseudoly viewed as a three-dimensional image.

Further, when displaying the left eye image and the right eye image, the light unit which divides a unit frame period for displaying each image into a plurality of subframe periods and irradiates a pixel circuit (also referred to as a display circuit) for each subframe period. By converting the color of the light (including the backlight) into a different color, a method (field sequential method) for displaying a full color image every unit frame period is known (for example, refer to Patent Document 1). ). By using the field sequential method, since the color filter does not need to be formed in a liquid crystal display device, light transmittance can be raised, for example.

In addition, a method of continuously displaying each of the left eye image and the right eye image in a plurality of frame periods is known (see Patent Document 2, for example). By using the above method, the interval for switching the shutters corresponding to both eyes in the glasses with the shutter can be increased, so that cross talk can be suppressed even when the frame frequency is increased.

JP 2003-259395 A Japanese Patent Application Laid-Open No. 2009-31523

The liquid crystal display device which displays by the field sequential method needs to improve the input frequency of the image signal with respect to each pixel. For example, a liquid crystal display device which performs display by a field sequential method using three colors of R (red), G (green), and B (blue) as a light source (back light) may convert white light into a light source (back light). Compared with the liquid crystal display device which displays by one color filter system, it is necessary to make the input frequency of the image signal with respect to each pixel at least 3 times. Specifically, in the case where the frame frequency is 60 Hz, in the liquid crystal display device which displays by the color filter method, it is necessary to input the image signal for each pixel 60 times per second, whereas R (red), In a liquid crystal display device which displays by the field sequential method using three colors of G (green) and B (blue) as a light source (backlight), it is necessary to perform image signal input to each pixel 180 times per second. .

In addition, when performing 3D image display by the field sequential method, it is necessary to have a period for displaying black (K) in addition to the above three colors in order to switch between the left eye image and the right eye image. Therefore, when three-dimensional image display is performed by the field sequential method, it is necessary to input the image signal for each pixel 480 times in one second.

As described above, color information is time-divided in a liquid crystal display device which displays in a field sequential manner. Therefore, specific display information is dropped due to the display being blocked for a short time such as blinking of the user, so that the display visually recognized by the user is changed from the display based on the original display information (also called color break or color breakage). The image quality of the display image is deteriorated.

An object of one embodiment of the present invention is to provide a display device with a good display quality while suppressing a decrease in image quality.

One object of one embodiment of the present invention is to provide a display device with low power consumption.

One object of this invention is to provide the display apparatus which can perform favorable three-dimensional display, without reducing a resolution.

By using a backlight having a plurality of backlight units capable of supplying light of different colors, the pixel portion is written for each specific area or for each backlight unit, and image signals are written and the backlight is turned on. Therefore, the backlight unlit period can be shorter than the method of turning on the backlight after recording the pixel signal in the entire pixel portion in the related art, and a display device with bright and good display quality can be realized.

In one embodiment of the present invention, a pixel portion having a plurality of pixels arranged in a matrix form is divided into a plurality of regions, and the lighting of the backlight unit emitting light of different colors is controlled for each region, It is a driving method of the display device which turns off the backlight unit of the area | region simultaneously and makes black display.

Also, the right eye image and the left eye image are switched and displayed for each black display, and the light incident on the right eye of the viewer is blocked when the display image is the left eye image, and when the display image is the right eye image, the left side of the viewer Blocks light entering the eye. In addition, display quality can be improved by writing an image signal to a pixel at the time of black display turning off the backlight unit.

One embodiment of the present invention has a pixel portion having a first region, a second region adjacent to the first region, and a third region adjacent to the second region, wherein the first to third regions are arranged in a matrix. A plurality of pixels, a plurality of backlight units arranged to overlap the plurality of pixels, the first sub frame period, the second sub frame period, the third sub frame period, the fourth sub frame period, A method of driving a liquid crystal display device having a first color display period, a second color display period, a third color display period, and a black display period, wherein the first region is the first color display period in the first sub frame period. The second area is the third color display period, the third area is the second color display period, the first area is the second color display period, and the second area is the first area in the second sub frame period. As the color display period, The third area is the third color display period, the first area is the third color display period, the second area is the second color display period, and the third area is the first color display period, in the third sub frame period. The driving method of the liquid crystal display device in which the first to third areas are subjected to the black display period in the fourth sub frame period.

One embodiment of the present invention has a pixel portion having a first region, a second region adjacent to the first region, and a third region adjacent to the second region, wherein the first to third regions are arranged in a matrix. A plurality of pixels having a plurality of pixels, and having a plurality of backlight units for supplying light of a first color, light of a second color, and light of a third color, overlapping the plurality of pixels, and performing a right eye image display A driving method of a liquid crystal display device having an eye image display period and a left eye image display period for performing a left eye image display, wherein the right eye image display period and the left eye image display period are a first sub frame period and a second sub frame. Period, a third sub frame period, and a fourth sub frame period, and after supplying a first color signal to a pixel of the first region in the first sub frame period, After supplying light of the first color, supplying the third color signal to the pixels of the second region, and then supplying the light of the third color from the backlight unit, supplying the second color signal to the pixels of the third region After that, the light of the second color is supplied from the backlight unit, the second color signal is supplied to the pixels of the first region in the second sub frame period, and then the light of the second color is supplied from the backlight unit. After supplying the first color signal to the pixels of the second region, supplying the light of the first color from the backlight unit, and supplying the third color signal to the pixels of the third region, and then from the backlight unit. After supplying the light of the third color, supplying the third color signal to the pixel of the first region in the third sub-frame period, supplying the light of the third color from the backlight unit, the pixel of the second region In the second color After supplying the arc, the second color light is supplied from the backlight unit, and the first color signal is supplied to the pixel of the third region, and then the light of the first color is supplied from the backlight unit, and the fourth The display device driving method is to turn off the backlight units in the first to third regions in the sub frame period.

Further, in the first sub frame period, the pixel adjacent to the second area of the first area is kept in the same color signal as the color signal held in the pixel in the fourth sub frame period.

Further, in the first sub frame period, the pixel adjacent to the third area of the second area is kept in the same color signal as the color signal held in the pixel in the fourth sub frame period.

Further, in the fourth sub frame period, the pixel adjacent to the first area of the second area is kept the same color signal as the color signal held in the pixel in the first sub frame period.

Further, in the fourth sub frame period, the pixel adjacent to the second area of the third area is kept in the same color signal as the color signal held in the pixel in the first sub frame period.

In addition, the viewer can visually recognize the three-dimensional image by alternately displaying the right eye image and the left eye image.

A display device having a good display quality can be provided.

A display device with low power consumption can be provided.

A display device capable of performing good stereoscopic display can be provided without degrading the resolution.

1 (A) and 1 (B) are diagrams showing a configuration example of a liquid crystal display device.
2A to 2C are diagrams showing a configuration example and an operation example of a scan line driver circuit.
3A to 3D are diagrams showing a configuration example and an operation example of a pulse output circuit.
4 is a diagram showing an example of operation of a scan line driver circuit;
5 (A) and 5 (B) are diagrams for explaining an example of the configuration of a signal line driver circuit and an example of timing for supplying an image signal.
6 (A) and 6 (B) show examples of the configuration of the backlight.
7 is a view for explaining an operation example of a liquid crystal display device.
8 is a view for explaining an operation example of a liquid crystal display device.
9 is a view for explaining an operation example of a liquid crystal display device.
10 (A) and 10 (B) are diagrams for explaining an operation example of the liquid crystal display device.
11A to 11G are views for explaining an operation example of the liquid crystal display device.
12A to 12D are cross-sectional views illustrating examples of the transistors.
13 (A) and 13 (B) are diagrams for explaining an example of the panel of the liquid crystal display device.
14 is a diagram illustrating a configuration example of a liquid crystal display device.
15A to 15D are diagrams for explaining a configuration example of an electronic device.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described, referring drawings. However, the present invention can be embodied in many different forms, and it can be easily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, it is not interpreted only to the description content of this embodiment. In addition, in the structure of this invention demonstrated below, the code | symbol which shows the same thing is common between different figures.

In addition, the magnitude | size of each structure, the thickness of a layer, a signal waveform, or an area shown by the figure of each embodiment etc. may be exaggeratedly expressed for clarity. Therefore, it is not necessarily limited to the scale.

In addition, the terms 1, 2, 3rd to Nth (N is a natural number), etc. used in the present specification are added to avoid confusion of components, and are not limited in number. In addition, natural numbers are demonstrated as one or more unless there is particular notice.

The transistor is one type of semiconductor element and can realize a switching operation for controlling amplification of current or voltage, conduction or non-conduction. Transistors presented herein include an IGFET (Insulated Gate Field Effect Transistor) or a thin film transistor (TFT).

Note that the functions of the "source" and "drain" of the transistor may be replaced when a transistor having a different polarity is employed or when the direction of the current changes in the circuit operation. Therefore, the terms "source" and "drain" may be used interchangeably herein.

(Embodiment 1)

In this embodiment, a liquid crystal display device of one embodiment of the present invention will be described with reference to FIGS. 1A to 11G.

<Configuration example of the liquid crystal display device>

FIG. 1A is a diagram illustrating a configuration example of the liquid crystal display device 100. In the liquid crystal display device 100 shown in FIG. 1A, the pixel portion 10, the scan line driver circuit 11, and the signal line driver circuit 12 are each arranged in parallel or substantially parallel to each other, and the scan line drive is performed. M scanning lines 13 whose potentials are controlled by the circuit 11, and n signal lines 14 each arranged in parallel or substantially parallel, and whose potentials are controlled by the signal line driver circuit 12. . In addition, the pixel portion 10 is divided into three regions (regions 101 to 103), and has a plurality of pixels 15 arranged in matrix form for each region.

Further, each scan line 13 is electrically connected to n pixels arranged in any one row among a plurality of pixels arranged in m rows n columns (m is a natural number of 12 or more, n is a natural number) in the pixel portion 10. Connected. In addition, each signal line 14 is electrically connected to m pixels arranged in any column among a plurality of pixels arranged in m rows n columns.

The m scanning lines 13 are divided into a plurality of groups according to the number of regions of the pixel portion 10. For example, in FIG. 1A, since the pixel portion 10 is divided into three regions, the m scan lines 13 are also divided into three groups. And the scanning line 13 which belongs to each group is electrically connected to the some pixel 15 which the area | region corresponding to the said group has. Specifically, each scan line 13 is electrically connected to n pixels 15 arranged in any row among the plurality of pixels 15 arranged in a matrix in each area.

The n signal lines 14 are electrically connected to the m pixels 15 arranged in any column among the plurality of pixels 15 arranged in the m rows and n columns in the pixel portion 10 regardless of the region. Connected.

FIG. 1B is a diagram showing an example of a circuit configuration of the pixel 15 included in the pixel portion 10 shown in FIG. 1A. The pixel 15 shown in FIG. 1B has a transistor 16, a capacitor 17, and a liquid crystal element 18.

The gate of the transistor 16 is electrically connected to the scan line 13, and one of the source and the drain is electrically connected to the signal line 14. In addition, one electrode of the capacitor 17 is electrically connected to the other of the source and the drain of the transistor 16, and the other electrode of the capacitor 17 is a wiring (also called a capacitor wiring) for supplying a capacitor potential. Is electrically connected to. One electrode (also referred to as a pixel electrode) of the liquid crystal element 18 is electrically connected to the other of the source and the drain of the transistor 16 and one electrode of the capacitor 17, and the liquid crystal element 18. The other electrode (also called a counter electrode) of () is electrically connected to a wiring for supplying a counter potential.

In the present embodiment, the transistor 16 is an n-channel transistor, but a p-channel transistor may be used. In addition, the capacitance potential and the opposite potential can be the same potential.

<Configuration example of scan line driver circuit>

FIG. 2A is a diagram showing an example of the configuration of the scan line driver circuit 11 included in the liquid crystal display device 100 shown in FIG. The scanning line driver circuit 11 shown in Fig. 2A includes wirings for supplying the clock signal GCK1 for the first scan line driver circuit to wirings for the clock signal GCK4 for the fourth scan line driver circuit, and first. The first pulse output circuit 20_1 electrically connected to the wiring for supplying the pulse width control signal PWM1 to the wiring for supplying the sixth pulse width control signal PWM6 and the scan line 13 arranged in the first row. And an mth pulse output circuit 20_m electrically connected to the scan line 13 arranged in the mth to mth rows.

In the present embodiment, the scan lines 13_1 to 13_k in which the first pulse output circuits 20_1 to k th pulse output circuits 20_k (k is a natural number of m / 3 or less) are arranged in the area 101. ) Shall be electrically connected. In the present embodiment, k is preferably a multiple of the number of clock signals GCK1 to GCK4 supplied to the scan line driver circuit 11, that is, a multiple of four.

In addition, it is assumed that the k + 1th pulse output circuits 20_k + 1 to 2k pulse output circuits 20_2k are electrically connected to the scan lines 13_k + 1 to 13_2k arranged in the region 102. It is also assumed that the second k + 1 pulse output circuits 20_2k + 1 to the m th pulse output circuits 20_m are electrically connected to the scan lines 13_2k + 1 to 13_m arranged in the region 103.

The first pulse output circuit 20_1 to the m th pulse output circuit 20_m sequentially shift shift pulses for each shift period, starting with the start pulse GSP for the scan line driver circuit input to the first pulse output circuit 20_1. It has a function of shifting. Further, the plurality of shift pulses can be shifted in parallel in the first pulse output circuit 20_1 to the m th pulse output circuit 20_m. That is, the start pulse GSP for the scan line driver circuit is input to the first pulse output circuit 20_1 even within the period in which the shift pulse is shifted in the first pulse output circuit 20_1 to the m th pulse output circuit 20_m. can do.

2B is a diagram showing an example of a specific operation of the signal. The clock signal GCK1 for the first scan line driver circuit shown in FIG. 2B periodically has a high level potential (high power supply potential V _dd ) and a low level potential (low power supply potential V _ss ). This signal is repeated and the duty ratio is 1/4. The clock signal GCK2 for the second scan line driver circuit is a signal shifted by a quarter period from the clock signal GCK1 for the first scan line driver circuit. The clock signal GCK3 for the third scan line driver circuit is a signal shifted by a half cycle from the clock signal GCK1 for the first scan line driver circuit. The clock signal GCK4 for the fourth scan line driver circuit is a signal shifted out of phase for three quarters from the clock signal GCK1 for the first scan line driver circuit.

The first pulse width control signal PWM1 shown in FIG. 2B periodically repeats a high level potential (high power supply potential V _dd ) and a low level potential (low power supply potential V _ss ). This is a signal with a duty ratio of 1/3. In addition, the second pulse width control signal PWM2 is a signal in which phases for 1 / 6th cycle are shifted from the first pulse width control signal PWM1. The third pulse width control signal PWC3 is a signal whose phase is shifted one third of the period from the first pulse width control signal PWC1. The fourth pulse width control signal PWC4 is a signal whose phase is shifted by 1/2 of the period from the first pulse width control signal PWM1. The fifth pulse width control signal PWC5 is a signal shifted out of phase by 2/3 periods from the first pulse width control signal PWM1. The sixth pulse width control signal PWM6 is a signal shifted out of phase for 5/6 periods from the first pulse width control signal PWM1.

Here, the pulse widths of the first scan line driver circuit clock signals GCK1 to the fourth scan line driver circuit clock signals GCK4 and the first pulse width control signals PWC1 to the sixth pulse width control signals PWC6. The ratio of pulse widths is set to 3: 2.

In the above-described liquid crystal display device 100, a circuit having the same configuration as the first pulse output circuit 20_1 to the m th pulse output circuit 20_m may be used. However, the electrical connection relationship of the several terminal which a pulse output circuit has differs for every pulse output circuit. A detailed connection relationship will be described with reference to FIGS. 2A and 2C.

Each of the first pulse output circuit 20_1 to the m th pulse output circuit 20_m has a terminal 21 to a terminal 27. The terminals 21 to 24 and the terminal 26 are input terminals, and the terminal 25 and the terminal 27 are output terminals.

First, the terminal 21 is described. The terminal 21 of the first pulse output circuit 20_1 is electrically connected to the wiring for supplying the start pulse GSP for the scan line driver circuit, and the second pulse output circuit 20_2 to the m th pulse output circuit 20_m The terminal 21 of is electrically connected to the terminal 27 of the pulse output circuit of a preceding stage.

Next, the terminal 22 is described. The terminal 22 of the (4a_3) th pulse output circuit (a is a natural number of m / 4 or less) is electrically connected to a wiring for supplying the clock signal GCK1 for the first scanning line driver circuit. The terminal 22 of the (4a_2) th pulse output circuit is electrically connected to a wiring for supplying the clock signal GCK2 for the second scan line driver circuit. The terminal 22 of the (4a_1) th pulse output circuit is electrically connected to a wiring for supplying the clock signal GCK3 for the third scan line driver circuit. The terminal 22 of the fourth pulse output circuit is electrically connected to a wiring for supplying the clock signal GCK4 for the fourth scanning line driver circuit.

Next, the terminal 23 is described. The terminal 23 of the (4a_3) th pulse output circuit is electrically connected to a wiring for supplying the clock signal GCK2 for the second scanning line driver circuit. The terminal 23 of the (4a_2) th pulse output circuit is electrically connected to a wiring for supplying the clock signal GCK3 for the third scanning line driver circuit. The terminal 23 of the (4a_1) th pulse output circuit is electrically connected to a wiring for supplying the clock signal GCK4 for the fourth scanning line driver circuit. The terminal 23 of the fourth pulse output circuit is electrically connected to a wiring for supplying the clock signal GCK1 for the first scanning line driver circuit.

Next, the terminal 24 is described. The terminal 24 of the (2b-1) th pulse output circuit (b is a k / 2 or less natural number) is electrically connected to a wiring for supplying the first pulse width control signal PWM1. The terminal 24 of the 2nd pulse output circuit is electrically connected to the wiring which supplies the 4th pulse width control signal PWM4. The terminal 24 of the (2c-1) pulse output circuit c is a natural number equal to or greater than (k / 2 + 1) k is electrically connected to the wiring for supplying the second pulse width control signal PWM2. . The terminal 24 of the second c pulse output circuit is electrically connected to the wiring for supplying the fifth pulse width control signal PWM5. The terminal 24 of the (2d-1) th pulse output circuit d is a natural number equal to or greater than (k + 1) m / 2 or less is electrically connected to a wiring for supplying the third pulse width control signal PWM3. . The terminal 24 of the 2d pulse output circuit is electrically connected to the wiring for supplying the sixth pulse width control signal PWM6.

Next, the terminal 25 is described. The terminal 25 of the x th pulse output circuit (x is a natural number of m or less) is electrically connected to the scan line 13_x arranged in the x th row.

Next, the terminal 26 will be described. The terminal 26 of the y th pulse output circuit (y is a natural number equal to or less than m −1) is electrically connected to the terminal 27 of the (y + 1) th pulse output circuit. The terminal 26 of the mth pulse output circuit is electrically connected to the wiring for supplying the stop signal STP for the mth pulse output circuit.

The stop signal STP for the mth pulse output circuit corresponds to the signal output from the terminal 27 of the (m + 1) th pulse output circuit, assuming that the (m + 1) th pulse output circuit is disposed. Is a signal. Specifically, these signals can be supplied to the mth pulse output circuit by actually disposing the (m + 1) th pulse output circuit as a dummy circuit or directly inputting the signal from the outside.

The connection relationship between the terminals 27 of the respective pulse output circuits has already been described. Therefore, the above description is used herein.

<Configuration example of pulse output circuit>

Fig. 3A is a diagram showing an example of the configuration of the pulse output circuit shown in Figs. 2A and 2C. The pulse output circuit shown in FIG. 3A has transistors 31 to 39.

The transistor 31 is electrically connected to a wiring (hereinafter also referred to as a high power supply potential line) for supplying a high power supply potential V _dd , and one of the source and drain is electrically connected to the terminal 21.

The transistor 32 is electrically connected to a wiring (hereinafter also referred to as a low power supply potential line) to which one of a source and a drain supplies a low power supply potential V _ss , and the other of the source and drain is connected to the transistor 31. Is electrically connected to the other of the source and the drain.

The transistor 33 has one of a source and a drain electrically connected to the terminal 22, the other of the source and a drain electrically connected to the terminal 27, and a gate of the transistor 33 being the other of the source and the drain of the transistor 31. One is electrically connected to the other of the source and the drain of the transistor 32.

Transistor 34 has one of a source and a drain electrically connected to a low power supply potential line, the other of the source and a drain electrically connected to terminal 27, and a gate is electrically connected to a gate of transistor 32. do.

Transistor 35 has one of a source and a drain electrically connected to a low power supply potential line, the other of the source and a drain is electrically connected to a gate of transistor 32 and a gate of transistor 34, with the gate being a terminal. It is electrically connected to (21).

Transistor 36 has one of a source and a drain electrically connected to a high power potential line, and the other of the source and the drain is a gate of transistor 32, a gate of transistor 34, and a source of transistor 35 and It is electrically connected to the other of the drains, and the gate is electrically connected to the terminal 26.

Transistor 37 has one of a source and a drain electrically connected to a high power potential line, and the other of the source and the drain is a gate of transistor 32, a gate of transistor 34, a source and a drain of transistor 35. Is electrically connected to the other, and to the other of the source and the drain of the transistor 36, and a gate is electrically connected to the terminal 23.

The transistor 38 has one of a source and a drain electrically connected to the terminal 24, the other of the source and the drain electrically connected to the terminal 25, and a gate of the source and the drain of the transistor 31. The other is electrically connected to the other of the source and the drain of the transistor 32 and the gate of the transistor 33.

In the transistor 39, one of a source and a drain is electrically connected to a low power supply potential line, the other of the source and a drain is electrically connected to a terminal 25, and the gate is a gate of the transistor 32, a transistor 34. ), The other of the source and the drain of the transistor 35, the other of the source and the drain of the transistor 36 and the other of the source and the drain of the transistor 37.

In addition, below, the node which the other of the source and the drain of the transistor 31, the other of the source and the drain of the transistor 32, the gate of the transistor 33, and the gate of the transistor 38 is electrically connected The node A will be described. In addition, the gate of the transistor 32, the gate of the transistor 34, the other of the source and drain of the transistor 35, the other of the source and drain of the transistor 36, the other of the source and drain of the transistor 37 One node and the node to which the gate of the transistor 39 is electrically connected will be described.

<Example of operation of pulse output circuit>

An operation example of the above-described pulse output circuit will be described with reference to FIGS. 3B to 3D. Here, the first pulse output circuit 20_1 and the (k + 1) are controlled by controlling the input timing of the start pulse GSP for the scan line driver circuit input to the terminal 21 of the first pulse output circuit 20_1. An operation example in the case of outputting a shift pulse at the same timing from the terminal 27 of the pulse output circuit 20_k + 1 and the (2k + 1) th pulse output circuit 20_2k + 1 will be described.

As a specific example, Fig. 3B shows the potential of the signal input to each terminal of the first pulse output circuit 20_1 when the start pulse GSP for the scan line driving circuit is input, and the potential of the nodes A and B. Shows. Fig. 3C shows the potential of the signal input to each terminal of the (k + 1) th pulse output circuit 20_k + 1 when a high level potential is input from the kth pulse output circuit 20_k, and the node. The potentials of A and Node B are shown. Fig. 3D shows the potential of the signal input to each terminal of the (2k + 1) th pulse output circuit 20_2k + 1 when the potential of the high level is input from the 2k pulse output circuit 20_2k, and the node. The potentials of A and Node B are shown.

In addition, in FIG.3 (B)-FIG.3 (D), the signal input to each terminal is added in the parentheses. In addition, pulse output circuits (second pulse output circuit 20_2, (k + 2) th pulse output circuit 20_k + 2), and (2k + 2) th pulse output circuit 20_2k + 2 disposed at the rear ends of the respective stages. Signals Gout2, Goutk + 2, and Gout2k + 2 output from the terminal 25 and signals output from the terminal 27 (SRout2 = input signal of the terminal 26 of the first pulse output circuit 20_1, SRoutk) +2 = input signal of the terminal 26 of the (k + 1) th pulse output circuit 20_k + 1, SRout2k + 2 = of the terminal 26 of the (2k + 1) th pulse output circuit 20_2k + 1 In addition, in the figure, Gout represents the signal which a pulse output circuit outputs to a scanning line, and SRout represents the signal which the said pulse output circuit outputs to a pulse output circuit of a later stage.

First, a case where a high level potential is input to the first pulse output circuit 20_1 as the start pulse for the scan line driving circuit GSP will be described with reference to FIG. 3B.

In the period t1, a high level potential (high power supply potential V _dd ) is input to the terminal 21. As a result, the transistors 31 and 35 are turned on. Therefore, the potential of the node A rises to a high level potential (a potential lowered from the high power supply potential V _{dd by} the threshold voltage of the transistor 31), and the potential of the node B rises to the low power supply potential V _ss . Descend to. Accompanying this, the transistor 33 and the transistor 38 are turned on, and the transistor 32, the transistor 34, and the transistor 39 are turned off.

As described above, the signal output from the terminal 27 in the period t1 becomes the signal input to the terminal 22, and the signal output from the terminal 25 becomes the signal input to the terminal 24. Here, the signals input to the terminal 22 and the terminal 24 in the period t1 are both low-level potentials (low power supply potential V _ss ). Therefore, in the period t1, the first pulse output circuit 20_1 has a low level potential (low power supply potential V _{ss) at} the scan line of the first row arranged in the terminal 21 and the pixel portion of the second pulse output circuit 20_2. Output)).

The signal input to each terminal in the period t2 does not change from the period t1. Therefore, the signals output from the terminal 25 and the terminal 27 also do not change, and both output a low level potential (low power supply potential V _ss ).

In the period t3, a high level potential (high power supply potential V _dd ) is input to the terminal 24. Further, the potential of the node A (source potential of the transistor 31) rises to a high level potential (a potential lowered by the threshold voltage of the transistor 31 from the high power supply potential V _dd ) in the period t1. Thus, the transistor 31 is turned off. At this time, a high-level potential (high power supply potential V _dd ) is input to the terminal 24 so that the potential of the node A (gate potential of the transistor 38) is formed by capacitive coupling of the source and gate of the transistor 38. Rises further (bootstrap operation). In addition, since the potential of the node A is raised by performing the bootstrap operation, the signal output from the terminal 25 does not fall from the high level potential (high power supply potential V _dd ) input to the terminal 24. . Therefore, in the period t3, the first pulse output circuit 20_1 outputs a high level potential (high power supply potential V _dd = selection signal) to the scanning lines arranged in the first row in the pixel portion.

In the period t4, a high level potential (high power supply potential V _dd ) is input to the terminal 22. Here, since the potential of the node A rises by the bootstrap operation, the signal output from the terminal 27 does not fall from the high level potential (high power supply potential V _dd ) input to the terminal 22. Therefore, in the period t4, the high level potential (high power supply potential V _dd ) input to the terminal 22 is output from the terminal 27. That is, the first pulse output circuit 20_1 outputs a high level potential (high power supply potential V _dd = shift pulse) to the terminal 21 of the second pulse output circuit 20_2. In the period t4, since the signal input to the terminal 24 maintains the high level potential (high power supply potential Vdd), the first row disposed in the pixel portion from the first pulse output circuit 20_1. The signal output to the scanning line of is a high level potential (high power supply potential Vdd = selection signal). In addition, in the period t4, the transistor 35 is turned off because a low level potential (low power supply potential V _ss ) is input to the terminal 21, although it is not directly involved in the output signal of the pulse output circuit.

In the period t5, a low level potential (low power supply potential V _ss ) is input to the terminal 24. Here, the transistor 38 remains on. Therefore, in the period t5, the signal output from the first pulse output circuit 20_1 to the scanning line of the first row arranged in the pixel portion becomes a low level potential (low power supply potential Vss).

The signal input to each terminal in the period t6 does not change from the period t5. Therefore, the signals output from the terminal 25 and the terminal 27 do not change, and a low level potential (low power supply potential V _ss ) is output from the terminal 25, and a high level is output from the terminal 27. The potential (high power supply potential (V _dd ) = shift pulse) is output.

In the period t7, a high level potential (high power supply potential V _dd ) is input to the terminal 23. As a result, the transistor 37 is turned on. Therefore, the potential of the node B rises from the high level potential (high power supply potential V _dd ) to the potential lowered by the threshold voltage of the transistor 37. In other words, the transistor 32, the transistor 34, and the transistor 39 are turned on. In addition to this, the potential of the node A falls to a low level potential (low power supply potential V _ss ). In other words, the transistors 33 and 38 are turned off. As described above, the signals output from the terminal 25 and the terminal 27 in the period t7 both become the low power supply potential V _ss . That is, in the period t7, the first pulse output circuit 20_1 outputs the low power supply potential V _ss to the terminal 21 of the second pulse output circuit 20_2 and the scanning line of the first row arranged in the pixel portion. .

Subsequently, when a high level potential is input as a shift pulse from the kth pulse output circuit 20_k to the terminal 21 of the (k + 1) th pulse output circuit 20_k + 1 with reference to FIG. 3C. This will be described.

The operation of the (k + 1) th pulse output circuit 20_k + 1 in the period t1 and the period t2 is the same as that of the first pulse output circuit 20_1 described above. Therefore, the above description is used herein.

The signal input to each terminal in the period t3 does not change from the period t2. Therefore, the signals output from the terminal 25 and the terminal 27 also do not change, and both output a low level potential (low power supply potential V _ss ).

In the period t4, a high level potential (high power supply potential V _dd ) is input to the terminal 22 and the terminal 24. Further, the potential of the node A (source potential of the transistor 31) rises to a high level potential (a potential lowered by the threshold voltage of the transistor 31 from the high power supply potential V _dd ) in the period t1. Thus, the transistor 31 is turned off in the period t1. Here, a high-level potential (high power supply potential V _dd ) is input to the terminals 22 and 24, thereby capacitive coupling of the source and gate of the transistor 33 and the source and gate of the transistor 38. The potential of the node A (gate potentials of the transistor 33 and the transistor 38) further rises (bootstrap operation). Further, by performing the bootstrap operation, a signal output from the terminal 25 and the terminal 27 falls from the high level potential (high power supply potential V _dd ) input to the terminal 22 and the terminal 24. I never do that. Therefore, in the period t4, the (k + 1) th pulse output circuit 20_k + 1 is connected to the scan line and the (k + 2) th pulse output circuit 20_k + 2 of the (k + 1) th row arranged in the pixel portion. A high level potential (high power supply potential V _dd = selection signal, shift pulse) is output to the terminal 21.

The signal input to each terminal in the period t5 does not change from the period t4. Therefore, the signals output from the terminals 25 and 27 also do not change, and output a high level potential (high power supply potential V _dd = selection signal, shift pulse).

In the period t6, a low level potential (low power supply potential V _ss ) is input to the terminal 24. Here, the transistor 38 remains on. Therefore, in the period t6, the signal output from the (k + 1) th pulse output circuit 20_k + 1 to the scan line of the (k + 1) th row arranged in the pixel portion has a low level potential (low power supply potential V). _ss )).

In the period t7, a high level potential (high power supply potential V _dd ) is input to the terminal 23. As a result, the transistor 37 is turned on. Therefore, the potential of the node B rises from the high level potential (high power supply potential V _dd ) to the potential lowered by the threshold voltage of the transistor 37. In other words, the transistor 32, the transistor 34, and the transistor 39 are turned on. In addition to this, the potential of the node A falls to a low level potential (low power supply potential V _ss ). In other words, the transistors 33 and 38 are turned off. As described above, the signals output from the terminal 25 and the terminal 27 in the period t7 are all at the low power supply potential V _ss . That is, in the period t7, the (k + 1) th pulse output circuit 20_k + 1 is disposed at the terminal 21 of the (k + 2) th pulse output circuit 20_k + 2 and the (k + 1) arranged in the pixel portion. The low power supply potential V _ss is output to the scanning line of the 1st row.

Subsequently, when a high level potential is input as a shift pulse from the second k pulse output circuit 20_2k to the terminal 21 of the (2k + 1) th pulse output circuit 20_2k + 1 with reference to FIG. 3D. This will be described.

In the period t1 to the period t3, the operation of the (2k + 1) th pulse output circuit 20_2k + 1 is the same as that of the (k + 1) th pulse output circuit 20_k + 1 described above. Therefore, the above description is used herein.

In the period t4, a high level potential (high power supply potential V _dd ) is input to the terminal 22. Further, the potential of the node A (source potential of the transistor 31) rises to a high level potential (a potential lowered by the threshold voltage of the transistor 31 from the high power supply potential V _dd ) in the period t1. Therefore, the transistor 31 is turned off in the period t1. Here, a high level potential (high power supply potential V _dd ) is input to the terminal 22, whereby the potential of the node A (gate potential of the transistor 33) is reduced by capacitive coupling of the source and the gate of the transistor 33. Further raise (bootstrap operation). In addition, the signal output from the terminal 27 does not fall from the high level potential (high power supply potential V _dd ) input to the terminal 22 by performing the bootstrap operation. Therefore, in the period t4, the (2k + 1) th pulse output circuit 20_k + 1 outputs a high level potential (high power supply potential Vdd = shift pulse) to the terminal 21 of the (2k + 2) th pulse output circuit 20_2k + 2. do. In the period t4, the transistor 35 is turned off because the output signal of the pulse output circuit is not directly involved, but the low level potential (low power supply potential V _ss ) is input to the terminal 21.

In the period t5, a high level potential (high power supply potential V _dd ) is input to the terminal 24. Here, since the potential of the node A rises by the bootstrap operation, the signal output from the terminal 25 does not fall from the high level potential (high power supply potential V _dd ) input to the terminal 24. Therefore, in the period t5, the high level potential (high power supply potential V _dd ) input to the terminal 22 is output from the terminal 25. That is, the (2k + 1) th pulse output circuit 20_k + 1 outputs a high level potential (high power supply potential V _dd = selection signal) to the scanning line of the (2k + 1) th row arranged in the pixel portion. do. In addition, since the signal input to the terminal 22 in the period t5 maintains the high level potential (high power supply potential V _dd ), the (2k + 1) th to (2k +) pulses from the (2k + 1) th pulse output circuit 20_2k + 1. 2) The signal output to the terminal 21 of the pulse output circuit 20_2k + 2 is a high level potential (high power supply potential V _dd = shift pulse).

The signal input to each terminal in the period t6 does not change from the period t5. Therefore, the signals output from the terminals 25 and 27 also do not change, and both output high potentials (high power supply potential V _dd = selection signal, shift pulse).

In the period t7, a high level potential (high power supply potential V _dd ) is input to the terminal 23. As a result, the transistor 37 is turned on. Therefore, the potential of the node B rises from the high level potential (high power supply potential V _dd ) to the potential lowered by the threshold voltage of the transistor 37. In other words, the transistor 32, the transistor 34, and the transistor 39 are turned on. In addition to this, the potential of the node A falls to a low level potential (low power supply potential V _ss ). In other words, the transistors 33 and 38 are turned off. As described above, the signals output from the terminal 25 and the terminal 27 in the period t7 are all at the low power supply potential V _ss . That is, in the period t7, the (k + 1) th pulse output circuit 20_k + 1 is disposed at the terminal 21 of the (k + 2) th pulse output circuit 20_k + 2 and the (k + 1) arranged in the pixel portion. The low power supply potential V _ss is output to the scanning line of the 1st row.

As shown in Figs. 3B to 3D, the first pulse output circuit 20_1 to the m th pulse output circuit 20_m controls the input timing of the start pulse GSP for the scan line driver circuit. A plurality of shift pulses can be shifted at the same time. Specifically, after inputting the start pulse GSP for the scan line driver circuit, the start pulse for the scan line driver circuit is again at the same timing as the shift pulse is output from the terminal 27 of the k-th pulse output circuit 20_k. By inputting GSP, the shift pulse can be output from the first pulse output circuit 20_1 and the (k + 1) th pulse output circuit 20_k + 1 at the same timing. Similarly, the first pulse output circuit 20_1, the (k + 1) th pulse output circuit 20_k + 1, and the (2k + 1) th pulse output circuit ( The shift pulse can be output at the same timing from 20_2k + 1).

The first pulse output circuit 20_1, the (k + 1) th pulse output circuit 20_k + 1, and the (2k + 1) th pulse output circuit 20_2k + 1 are different timings in parallel with the above operation. Can supply a selection signal for the scan line. That is, the above-described scan line driver circuit shifts a shift pulse having a unique shift period a plurality of times, and at the same timing as the operation, the plurality of pulse output circuits to which the shift pulse is input are selected signals for the scan line at different timings, respectively. Can be supplied.

<Example of operation of scan line driver circuit>

Next, the operation of the scan line driver circuit will be described.

4 shows an example of a timing chart for explaining the operation of the scan line driver circuit 11. In FIG. 4, the subframe period SF1, the subframe period SF2, and the subframe period SF3 are illustrated in one frame period. A timing chart of the sub frame period SF1 is shown as a representative example of one sub frame period.

In FIG. 4, the scan lines 13_1 to 13_k are electrically connected to the pixels in the region 101, and the scan lines 13_k + 1 to 13_2k are electrically connected to the pixels in the region 102. The scan lines 13_2k + 1 to 13_m exemplify timing charts in the case where they are electrically connected to the pixels in the region 103.

Each sub frame period SF starts with the drop in the potential of the pulse of the start pulse signal GSP for the scan line driver circuit. The pulse width of the start pulse signal GSP for the scan line driver circuit is about the same as the clock signal GCK1 for the first scan line driver circuit and the clock signal GCK4 for the fourth scan line driver circuit. Then, the drop of the potential of the pulse of the start pulse signal GSP for the scan line driver circuit and the rise of the potential of the pulse of the clock signal GCK1 for the first scan line driver circuit are synchronized. In addition, the drop of the potential of the pulse of the start pulse signal GSP for the scan line driver circuit is 1 of the first pulse width control signal PWM1 from the rise of the potential of the pulse of the first pulse width control signal PWM1. It appears at a timing delayed by / 6 cycles.

In response to the signal, the pulse output circuit shown in Fig. 3A operates in accordance with the timing chart shown in Fig. 3B. Therefore, as shown in FIG. 4, the selection signal obtained by sequentially shifting the pulses is applied to the scanning lines 13_1 to 13_k corresponding to the region 101. In addition, the pulses of the selection signal applied to the scanning lines 13_1 to 13_k are shifted so that their phases are delayed by a period corresponding to three-thirds of the pulse width. The pulse widths of the selection signals applied to the scan lines 13_1 to 13_k are about the same as the pulse widths of the first pulse width control signal PWM1 to the sixth pulse width control signal PWM6.

In addition, similarly to the case of the region 101, the selection signal obtained by sequentially shifting the pulses is provided to the scanning lines 13_k + 1 to 13_2k corresponding to the region 102. In addition, the pulses of the selection signal applied to the scanning lines 13_k + 1 to 13_2k are shifted so that their phases are delayed by a period corresponding to three-thirds of the pulse width. In addition, the pulse width of the selection signal applied to the scanning lines 13_k + 1 to 13_2k is about the same as the pulse width of the first pulse width control signal PWM1 to the sixth pulse width control signal PWM6.

In addition, similarly to the case of the region 101, the selection signals obtained by sequentially shifting pulses are provided to the scanning lines 13_2k + 1 to 13_m corresponding to the region 103. In addition, the pulses of the selection signal applied to the scanning lines 13_2k + 1 to 13_m are shifted so that the phase is delayed by a period corresponding to three-thirds of the pulse width. In addition, the pulse width of the selection signal applied to the scanning lines 13_2k + 1 to 13_m is about the same as the pulse width of the first pulse width control signal PWM1 to the sixth pulse width control signal PWM6.

The pulses of the selection signals supplied to the scan line 13_1, the scan line 13_k + 1, and the scan line 13_2k + 1 are sequentially shifted so that the phases are delayed by a period corresponding to one half of the pulse width.

<Configuration example of signal line driver circuit>

FIG. 5A is a diagram showing a configuration example of the signal line driver circuit 12 included in the liquid crystal display device 100 shown in FIG. 1A. The signal line driver circuit 12 shown in Fig. 5A has a shift register 120 having first to nth output terminals, a wiring for supplying an image signal DATA, and one of a source and a drain. Is electrically connected to the wiring for supplying the image signal DATA, the other of the source and the drain is electrically connected to the signal line 14_1 of the first column arranged in the pixel portion, and the gate is the first of the shift register 120. One of the transistors 121_1 to one of the source and the drain electrically connected to the output terminal is electrically connected to the wiring for supplying the image signal DATA, and the signal line of the nth column in which the other of the source and the drain is disposed in the pixel portion ( 14_n) and a transistor 121_n electrically connected to the nth output terminal of the shift register 120.

Further, the shift register 120 has a function of sequentially outputting a high level potential from the first to nth output terminals in sequence for each shift period by the start pulse SSP for the signal line driver circuit. That is, the transistors 121_1 to 121_n are sequentially turned on every shift period.

FIG. 5B is a diagram showing an example of timing at which the wiring for supplying the image signal DATA supplies the image signal. As shown in Fig. 5B, the wiring for supplying the image signal DATA supplies the image signal data 1 for pixels arranged in the first row in the period t4, and (k + 1) in the period t5. The pixel image signal data k + 1 arranged in the first row is supplied, and the pixel image signal data 2k + 1 arranged in the (2k + 1) th row is supplied in the period t6, and 2 in the period t7. The pixel image signal data 2 arranged in the first row is supplied. Similarly, the wiring for supplying the image signal DATA sequentially supplies the image signal for pixels arranged for each specific row. When generalized, an image signal for a pixel placed in the sth row (s is a natural number less than k), an image signal for a pixel placed next to the k + 1th row, and a pixel disposed in the 2k + sth row next The image signals may be supplied in order of the image signals for the image signal and then for the pixels arranged in the s + 1th row.

The above-described operation of the scan line driver circuit and the signal line driver circuit enables input of an image signal to three rows of pixels arranged in the pixel portion at each shift period in the pulse output circuit included in the scan line driver circuit.

<Configuration example of the back light>

FIG. 4 is a diagram illustrating a configuration example of a backlight formed behind the pixel portion 10 of the liquid crystal display device 100 illustrated in FIG. 1A. 6 (A) and 6 (B) show the light emission in the red wavelength band (also referred to as "R"), the light emission in the green wavelength band (also referred to as "G"), and the blue wavelength. There are a plurality of backlight units 40 provided with a light source that shows three colors of light emission by the band (also referred to as "B"). As the backlight unit 40, for example, a light emitting diode (LED) can be used. By using a red light emitting diode, a green light emitting diode, and a blue light emitting diode, the backlight unit 40 provided with the light source which shows three colors can be comprised.

In addition, the plurality of backlight units 40 are arranged in a matrix and can control lighting for each specific region. Here, as a backlight for the plurality of pixels 15 arranged in m rows and n columns, the backlight unit 40 is disposed at least every scan line t rows (t is a natural number satisfying k / N (N is a natural number)). do. N corresponds to the number of rows of the backlight unit 40 in each area. In addition, lighting of the backlight unit 40 shall be controlled independently.

In addition, it is assumed that the backlight unit 40 can also independently control the lighting of each of the light sources representing three colors of red (R), green (G), and blue (B). That is, the backlight unit 40 turns on one of the red (R), green (G), and blue (B) light sources to turn on the red (R), green (G), And light which represents any color of blue (B) can be irradiated.

As an example, in this embodiment, N is 4, the backlight units 40 are arranged in each area four rows, and the one backlight unit 40 functions as a light source of the pixels 15 for t rows. Shall be.

In addition, in this embodiment, although the pixel part 10 is divided | segmented into three area | regions, when m is not a multiple of 3, the number of rows of the backlight unit 40 may not become the same for each area | region. Since the number of rows of the backlight unit 40 in each area is not necessarily the same, the number of rows of the backlight unit 40 in each area may be appropriately set according to the number of rows of the pixels 15.

The light emission intensity (luminance) of the backlight unit 40 observed through the pixel 15 is determined by the light emission intensity of the backlight unit 40 disposed directly below the pixel 15. However, in practice, the light diffused from the adjacent backlight unit 40 is also taken into consideration.

Therefore, as shown in Fig. 6A, when the region of the pixel portion 10 and the region where the backlight unit 40 is arranged are the same, all the backlight units 40 are made to emit light with the same brightness, and all the pixels ( Even when the same pixel signal is supplied to 15, the luminance observed through the pixel 15 disposed along the outer periphery of the pixel portion 10 is weaker than the luminance observed through the pixel 15 disposed inside. Is observed.

FIG. 6B shows an example in which the backlight unit 40 is disposed larger than the pixel portion 10 beyond the end portion of the pixel portion 10. By arranging the backlight unit 40 outside the pixel portion 10, the luminance observed in the pixel 15 disposed along the outer periphery of the pixel portion 10 can be observed in the pixel 15 disposed therein. The same can be achieved with luminance.

<Example of operation of the liquid crystal display device>

Next, an example of an operation for displaying the three-dimensional image on the liquid crystal display device 100 will be described with reference to FIGS. 7 to 11G. 7 is a diagram schematically showing a three-dimensional display (stereoscopic display) operation. As shown in FIG. 7, in the display device of one embodiment of the present invention, one frame period includes a right eye image display period 310 and a left eye image display period 320.

The right eye image display period 310 is composed of sub frame period SF1R to sub frame period SF4R. The right eye image display period 310 has four periods of a first color display period 311, a second color display period 312, a third color display period 313, and a black display period 314. .

The left eye image display period 320 is composed of sub frame period SF1L to sub frame period SF4L. In addition, the left eye image display period 320 has four periods: a first color display period 321, a second color display period 322, a third color display period 323, and a black display period 324. .

In the first color display period 311 and the first color display period 321, a first color signal is recorded in the pixel 15, and then light of the first color is supplied from the backlight unit 40. In addition, in the second color display period 312 and the second color display period 322, the second color signal is recorded in the pixel 15, and then light of the second color is supplied from the backlight unit 40. do. In addition, in the third color display period 313 and the third color display period 323, a third color signal is recorded in the pixel 15, and then light of the third color is supplied from the backlight unit 40. do. In the black display period 314 and the black display period 324, the supply of light from the backlight unit 40 is stopped (lighted off).

In the first color display period 311 to the third color display period 313 and the first color display period 321 to the third color display period 323, image signals (color signals) corresponding to respective colors are converted into pixels. It sequentially writes to the sections, and the color of the light supplied to the pixel section by the backlight unit 40 is switched. Then, one image is formed by recording image signals corresponding to all colors within one frame period. Thus, the number of times the image signal is written to the pixel portion in one frame period is plural times, and the number is determined by the number of colors of light supplied from the backlight.

In this embodiment, a 1st color is made red, a 2nd color is made green, and a 3rd color is made blue. That is, red color is displayed in the first color display period 311 and the first color display period 321, and green color is displayed in the second color display period 312 and the second color display period 322. It is assumed that blue color is displayed in the third color display period 313 and the third color display period 323.

As shown in Fig. 8, the three-dimensional image can be observed by observing the image displayed on the pixel portion 10 using the glasses 702 having the left eye shutter 703A and the right eye shutter 703B. have.

During the right eye image display period 310, the right eye shutter 703B corresponding to the right eye 724 of the glasses is opened (the right eye shutter opening period 318) and the left eye 723 of the glasses is opened. The left eye shutter 703A is closed (left eye shutter closing period 319) to block light from entering the viewer's left eye 723. During the left eye image display period 320, the left eye shutter 703A corresponding to the left eye 723 of the glasses is opened (the shutter opening period 329 for the left eye), and the right eye 724 of the glasses is opened. The right eye shutter 703B is closed (right eye shutter closing period 328) to block light from entering the viewer's right eye 724. In this manner, by visually recognizing different images for the right eye 724 and the left eye 723 of the viewer, the two-dimensional image displayed on the pixel portion 10 can be visually recognized as a three-dimensional image.

In addition, the opening and closing of the left eye shutter 703A and the right eye shutter 703B are performed at the time ta and the time tg shown in FIG. At the time ta and the time tg, since the whole pixel part 10 becomes black display, when the shutter opens and closes, the image for a right eye and an image for a left eye are not visually recognized incorrectly, and 3D image with a favorable display quality can be observed. .

Subsequently, an image signal is recorded in the areas 101 to 103 that constitute the pixel portion 10 using Figs. 9 and 11A to 11G, and from the backlight unit 40 The right eye image display period 310 will be described as an example for the operation of supplying red (R) light, blue (B) light, and green (G) light.

FIG. 9 is a diagram illustrating in detail the operations of the areas 101 to 103 in the right eye image display period 310 of FIG. 7, and recording the image signals in the sub frame periods SF1R to SF4R. The relationship between the period 331 and the backlight lighting period 332 is shown.

FIG. 10A is an enlarged view of the boundary between the region 101 and the region 102 in FIG. 9. FIG. 10B is an enlarged view of the boundary between the region 102 and the region 103 in FIG. 9.

11A to 11G, image signals are recorded in the areas 101 to 103 that constitute the pixel portion 10, and the red (R) light is emitted from the backlight unit 40, The state in which the light of blue (B) and the light of green (G) is supplied is shown.

11A to 11G show display states of the regions 101 to 103 at the time ta and the time tg shown in FIGS. 7 and 9, respectively. At time ta, the backlight units 40 of the areas 101 to 103 are turned off so that the entire pixel portion 10 is displayed in black (K) (see Fig. 11A).

After the time ta, in the region 101, the scan lines 13_1 to 13_k are sequentially selected, and the R image signal is recorded in the pixel 15 electrically connected to the selected scan line 13. The image signal recorded in the pixel 15 is held until the pixel 15 is selected again. At this time, when recording of t rows is completed, light of R is supplied from the backlight unit 40 corresponding to the recorded t rows.

Further, in the region 102, up to the scan lines 13_k + 1 to 13_2k are sequentially selected, and the image signal of B is recorded in the pixel 15 electrically connected to the selected scan line 13. The image signal recorded in the pixel 15 is held until the pixel 15 is selected again. At this time, when recording of t rows is completed, light of B is supplied from the backlight unit 40 corresponding to the recorded t rows.

Further, in the region 103, the scan lines 13_2k + 1 to 13_m are sequentially selected, and a G image signal is recorded in the pixel 15 electrically connected to the selected scan line 13. The image signal recorded in the pixel 15 is held until the pixel 15 is selected again. At this time, when the recording of the t rows is finished, the G light is supplied from the backlight unit 40 corresponding to the recorded t rows.

In addition, unless otherwise stated, "recording an image signal to a pixel" or "rewriting an image signal of a pixel" in this specification means that an image signal is newly supplied to a pixel, and then the image signal is supplied again. Indicates that the image signal supplied to the pixel is maintained until

FIG. 11B shows the display situation of the regions 101 to 103 at the time tb. At the time tb, the pixels 15 included in the regions 101 to 103 are rewritten to the middle of the regions, respectively.

FIG. 11C shows a display situation of the regions 101 to 103 at the time tc. FIG. At time tc, an image signal of R is recorded in all the pixels 15 included in the area 101, and light of R is supplied from the backlight unit 40. In addition, an image signal of B is recorded in all the pixels 15 included in the region 102, and light of B is supplied from the backlight unit 40. In addition, G image signals are recorded in all the pixels 15 included in the region 103, and the G light is supplied from the backlight unit 40.

After the time tc, the backlight unit 40 corresponding to the scanning lines of the scanning lines 13_1 to 13_t is turned off in the area 101, and then the scanning lines 13_1 to the scanning lines 13_t are sequentially turned on. A G image signal is recorded in the pixel which is selected and electrically connected to the selected scanning line 13. When the recording of the scan line 13_t is completed, the G light is supplied from the backlight unit 40 corresponding to the scan line 13_t in the scan line 13_1.

Further, in the region 102, the backlight unit 40 corresponding to the scanning line of the scanning lines 13_k + 1 to 13_k + 1 + t is turned off, and then the scanning lines 13_k in the scanning line 13_k + 1. Up to + 1 + t) are sequentially selected, and an image signal of R is recorded in a pixel electrically connected to the selected scanning line 13. When the recording of the scan line 13_k + 1 + t ends, the light of R is supplied from the backlight unit 40 corresponding to the scan line 13_k + 1 + t in the scan line 13_k + 1.

In the region 103, the backlight corresponding to the scanning lines of the scanning lines 13_2k + 1 to 13_2k + 1 + t is turned off, and then the scanning lines 13_2k + 1 + t in the scanning lines 13_2k + 1. ) Is sequentially selected, and the image signal of B is recorded in the pixel electrically connected to the selected scanning line 13. When the recording of the scan line 13_2k + 1 + t ends, light of B is supplied from the backlight corresponding to the scan line 13_2k + 1 + t in the scan line 13_2k + 1.

11D shows the display situation of the regions 101 to 103 at the time td. At time td, the pixel 15 included in the regions 101 to 103 is rewritten to the middle of each region.

FIG. 11E shows the display situation of the regions 101 to 103 at the time te. At time te, the image signal of B is recorded in all the pixels 15 included in the area 101, and the light of B is supplied from the backlight unit 40. In addition, G image signals are recorded in all the pixels 15 included in the region 102, and the G light is supplied from the backlight unit 40. In addition, an image signal of R is recorded in all the pixels 15 included in the region 103, and light of R is supplied from the backlight unit 40.

After the time te, the backlight unit 40 corresponding to the scanning lines of the scanning lines 13_1 to 13_t is turned off in the area 101, and then the scanning lines 13_1 to the scanning lines 13_t are sequentially turned on. An image signal of K is written to the pixel which is selected and electrically connected to the selected scanning line 13.

Further, in the region 102, the backlight unit 40 corresponding to the scan lines 13_k + 1 to 13_k + 1 + t is turned off, and then the scan lines 13_k + 1 in the scan lines 13_k + 1. up to + t) are sequentially selected, and an image signal of K is recorded in a pixel electrically connected to the selected scanning line 13.

In the region 103, the backlights corresponding to the scan lines 13_2k + 1 to 13_2k + 1 + t are turned off, and thereafter, from the scan lines 13_2k + 1 to the scan lines 13_2k + 1 + t. Are sequentially selected, and the K image signal is recorded in the pixel electrically connected to the selected scanning line 13.

Fig. 11F shows the display situation of the regions 101 to 103 at the time tf. At the time tf, the state in which the pixels 15 included in the regions 101 to 103 are rewritten to the middle of each region is shown.

11G shows the display situation of the regions 101 to 103 at the time tg. At time tg, all the backlight units 40 in the areas 101 to 103 are turned off, and the entire pixel portion 10 is marked with K.

In this manner, the display device shown in the present embodiment can divide the pixel portion 10 into a plurality of regions and display an image for each backlight unit 40. In the conventional field sequential method, the backlight needs to be turned on after the image signal is recorded in the entire pixel portion 10. However, the display device shown in this embodiment has an image signal for each region or for each backlight unit 40. FIG. Since the recording and the backlight can be turned on, the backlight off period can be shortened. Therefore, a display device that is bright and has good display quality can be realized. In addition, the deterioration of the image quality of the display image due to the color break can be reduced. In addition, a display device with low power consumption can be realized.

In addition, as described in the configuration example of the backlight, the luminance observed in the pixel 15 is equal to the light of the backlight unit 40 disposed immediately below the pixel 15 and the adjacent backlight unit 40. Is determined by the sum of diffused light. Therefore, the luminance of the pixels 15 adjacent to the row in which the black display is turned off and the backlight unit 40 is turned off is observed as the luminance decreases so that the diffused light of the adjacent backlight unit 40 disappears.

Thus, in the sub frame period SF1R, the pixels 15 electrically connected to the scan lines 13_3t + 1 to 13_k of the area 101 become black display, and the scan lines 13_3t + 1 to 13_k are black. When the backlight unit 40 corresponding to) is turned off, the luminance of the pixel 15 electrically connected to the scan line 13_k + 1 of the region 102 is lowered.

In the sub-frame period SF4R, the pixels 15 electrically connected to the scan lines 13_k + 1 to 13_k + 1 + t of the region 102 become black display, and the scan lines of the region 102 are black. When the backlight unit 40 corresponding to (13_k + 1) to the scan line 13_k + 1 + t is turned off, the luminance of the pixel 15 electrically connected to the scan line 13_k of the region 101 is lowered. do.

In the sub frame period SF1R, the pixels 15 electrically connected to the scanning lines 13_k + 1 + 3t + 1 to the scanning lines 13_2k in the region 102 become black display, and the scanning lines 13_k + 1 + When the backlight unit 40 corresponding to 3t + 1 to the scanning line 13_2k is turned off, the luminance of the pixel 15 electrically connected to the scanning line 13_2k + 1 of the region 103 is lowered.

Further, in the sub frame period SF4R, the pixels 15 electrically connected to the scan lines 13_2k + 1 to 13_2k + 1 + t in the region 103 become black display, and the scan lines in the region 103 are black. When the backlight unit 40 corresponding to (13_2k + 1) to scan line 13_2k + 1 + t is turned off, the luminance of the pixel 15 electrically connected to the scan line 13_2k in the region 102 is lowered. do.

That is, in the boundary between the region 101 and the region 102 and the boundary between the region 102 and the region 103, luminance deterioration of any of R, G, and B occurs, so that accurate color reproduction cannot be performed. The display quality deteriorates.

Therefore, in the sub frame period SF1R, when the pixel 15 electrically connected to the scan lines 13_3t + 1 to 13_k of the area 101 is displayed in black, in the immediately preceding sub frame period SF4L, After the backlight unit 40 corresponding to the scan lines 13_3t + 1 to 13_k in the area 101 is turned off, the subframe period SF4R is connected to the pixel 15 electrically connected to the scan line 13_k. An image signal 341 for performing blue display is recorded on the pixel 15 electrically connected to the scanning line 13_k (see Fig. 10A).

Thus, the image information of the sub frame period SF4R for displaying the blue color in the pixel 15 electrically connected to the scan line 13_k in the black display period of the sub frame period SF1R is maintained. Then, the diffused light of the backlight unit 40 on the adjacent region 102 side is observed through the pixel 15 electrically connected to the scan line 13_k during the black display period.

The viewer is electrically connected to the increase in luminance of the pixel 15 electrically connected to the scan line 13_k in the black display period (sub frame period SF1R) and the scan line 13_k in the blue display period (sub frame period SF4R). The decrease in luminance of the pixels 15 connected to each other is observed substantially simultaneously. At this time, since the image information recorded in the pixel 15 electrically connected to the scanning line 13_k is the same image information in the sub frame period SF1R and the sub frame period SF4R, the above-mentioned brightness rise and brightness fall cancel each other and correct Color reproduction can be performed.

In addition, in this embodiment, although the fall of the brightness | luminance in a boundary part arises only with respect to one scanning line 13, it was demonstrated that depending on the structure, arrangement | positioning method, and luminescence intensity of the backlight unit 40, brightness fall-in several plural scanning lines. There is a possibility to occur over (13). Therefore, the image information for displaying the color may be retained in the pixel 15 electrically connected to the plurality of scan lines 13 in the black display calculation.

For example, the scan lines 13_3t + 1 to 13_k in the sub-frame period SF4R are connected to the pixels 15 electrically connected to the scan lines 13_3t + 1 to the scan line 13_k which become black in the sub-frame period SF1R. An image signal for displaying a blue color may be held in the pixel 15 electrically connected to the pixel 15. In addition, an image signal for writing to the pixel 15 electrically connected to the scanning lines 13_3t + 1 to the scanning line 13_k in the black display period is recorded with an image signal for displaying blue color in the sub frame period SF4R. The pixel 15 is written in the same pixel.

Further, in the sub frame period SF4R, when the pixel 15 electrically connected to the scan lines 13_k + 1 to 13_k + 1 + t of the region 102 is displayed in black, the scan lines 13_k + 1 ), An image signal 342 for performing blue display is recorded on the pixel 15 electrically connected to the scanning line 13_k + 1 in the subframe period SF1R (Fig. 10). (A)).

Further, in the sub frame period SF1R, when the pixel 15 electrically connected to the scanning lines 13_k + 1 + 3t + 1 to the scanning lines 13_2k in the region 102 is displayed in black, the immediately preceding sub frame period In SF4L, after turning off the backlight unit 40 corresponding to the scan lines 13_k + 1 + 3t + 1 to the scan line 13_2k, the subframe is connected to the pixel 15 electrically connected to the scan line 13_2k. In the period SF4R, an image signal 343 for displaying green color is recorded in the pixel 15 electrically connected to the scan line 13_2k. Thus, the image information of the sub frame period SF4R for displaying the green color in the pixel 15 electrically connected to the scan line 13_2k during the black display period of the sub frame period SF1R is retained (see Fig. 10B). ).

In the sub-frame period SF4R, when the pixels 15 electrically connected to the scanning lines 13_2k + 1 to 13_2k + 1 + t of the region 103 are displayed in black, the scanning lines 13_2k + 1 are displayed. An image signal 344 for green display is recorded in the pixel 15 electrically connected to the pixel 15 electrically connected to the scan line 13_2k + 1 in the subframe period SF1R (Fig. 10 (B). ) Reference).

In this way, by recording the image information in the pixel 15 during the black display period, a display device having good color reproducibility and good display quality can be realized.

Moreover, since the liquid crystal display device 100 shown in this embodiment does not use a color filter, it can perform favorable three-dimensional display, without reducing a resolution. In addition, since no color filter is used, absorption of backlight light by the color filter does not occur. Therefore, a liquid crystal display device with bright display quality can be realized. In addition, a liquid crystal display device with low power consumption can be realized.

In the present embodiment, red is displayed in the first color display period 311, green is displayed in the second color display period 312, and blue is displayed in the third color display period 313. It is not limited. The first color display period 311 to the third color display period 313 may use any color. For example, blue may be displayed in the first color display period 311, red may be displayed in the second color display period 312, and green may be displayed in the third color display period 313.

In addition, the color used in the first color display period 311 to the third color display period 313 is not a combination of red, green, and blue, but cyan, magenta, and yellow (yellow). ) May be used. Further, the color display period may be extended, and the colors of red, green, blue, cyan, magenta, and yellow may be appropriately combined. In addition, the same color may be applied to the first color display period 311 to the third color display period 313 to achieve monochromatic display. The same applies to the first color display period 321 to the third color display period 323 of the left eye image display period 320.

The color displayed in the first color display period 311 to the third color display period 313 and the first color display period 321 to the third color display period 323 is the right eye image display period ( Switching may be performed for each of 310 and the left eye image display period 320, or may be switched for each frame. For example, red may be displayed in the first color display period 311 of the right eye image display period 310 and green may be displayed in the first color display period 321 of the left eye image display period 320. good. By displaying in this way, it is possible to further reduce the deterioration of the image quality of the display image due to the color break, thereby realizing a display device having good display quality.

In addition, the liquid crystal display device 100 shown in this embodiment can also perform two-dimensional display. In the case of performing two-dimensional display, since the right eye image display period 310 and the left eye image display period 320 do not need to be viewed separately, the image can be observed without using the glasses 702.

In addition, since there is no need to divide the image display period 310 for the right eye and the image display period 320 for the left eye, it is possible to halve the frame period compared to the three-dimensional display, and to provide a bright and low power consumption display device. It can be realized. In addition, since the entire surface of the pixel portion 10 is displayed in black every one frame (black insertion), afterimages during video display can be reduced.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 2)

In this embodiment, an example of a transistor applicable to the liquid crystal display device disclosed in this specification is shown. The structure of the transistor that can be applied to the liquid crystal display device disclosed in the present specification is not particularly limited, and for example, a top gate structure in which the gate electrode is disposed above the semiconductor layer via the gate insulating layer, or the gate electrode is A staggered type, a planar type, or the like of a bottom gate structure disposed below the semiconductor layer via the gate insulating layer can be used. The transistor may be a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. Alternatively, a dual gate type may be provided having two gate electrode layers arranged above and below the channel region with the gate insulating layer interposed therebetween. In addition, an example of the cross-sectional structure of a transistor is shown below using FIGS. 12 (A)-12 (D).

The transistor 410 shown in Fig. 12A is one of the transistors having a bottom gate structure, and is also called an inverted staggered transistor.

The transistor 410 includes a gate electrode 401, a gate insulating layer 402, a semiconductor layer 403, a source electrode 405a, and a drain electrode 405b over a substrate 400 having an insulating surface. An insulating layer 407 is formed to cover the transistor 410 and be stacked on the semiconductor layer 403. A protective insulating layer 409 is further formed on the insulating layer 407.

The transistor 420 shown in Fig. 12B is one of a bottom gate structure called a channel protection type (also called a channel stop type), and is also called an inverted staggered transistor.

The transistor 420 functions as a channel protection layer that covers the channel formation regions of the gate electrode 401, the gate insulating layer 402, the semiconductor layer 403, and the semiconductor layer 403 on the substrate 400 having an insulating surface. An insulating layer 427, a source electrode 405a, and a drain electrode 405b. In addition, the protective insulating layer 409 is formed to cover the transistor 420.

The transistor 430 shown in FIG. 12C is a bottom gate type transistor, and the gate electrode 401, the gate insulating layer 402, the source electrode 405a, and the drain are disposed on a substrate 400 having an insulating surface. An electrode 405b and a semiconductor layer 403 are included. In addition, an insulating layer 407 is formed to cover the transistor 430 and to contact the semiconductor layer 403. A protective insulating layer 409 is further formed on the insulating layer 407.

In the transistor 430, the gate insulating layer 402 is formed in contact with the substrate 400 and the gate electrode 401, and the source electrode 405a and the drain electrode 405b are formed in contact with the gate insulating layer 402. . The semiconductor layer 403 is formed on the gate insulating layer 402, the source electrode 405a, and the drain electrode 405b.

The transistor 440 shown in Fig. 12D is one of the transistors having a top gate structure. The transistor 440 is disposed on the substrate 400 having an insulating surface, and includes an insulating layer 437, a semiconductor layer 403, a source electrode 405a, a drain electrode 405b, a gate insulating layer 402, and a gate electrode ( The wiring layer 436a and the wiring layer 436b are formed in contact with the source electrode 405a and the drain electrode 405b, respectively, and are electrically connected.

The semiconductor material used for the semiconductor layer 403 is not limited to non-single-crystal semiconductors such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, and the like, but is a single crystal semiconductor, a compound semiconductor such as GaAs or CdTe, or an oxide such as ZnO or InGaZnO. Known semiconductor materials such as semiconductors and organic semiconductors can be used.

Although there is no big restriction | limiting in the board | substrate which can be used for the board | substrate 400 which has an insulating surface, Glass substrates, such as barium borosilicate glass and alumino borosilicate glass, are used.

In the bottom gate structure transistors 410, 420, and 430, an insulating layer serving as an underlayer may be formed between the substrate and the gate electrode. The base layer has a function of preventing the diffusion of impurity elements into the substrate 400 and includes one or a plurality of insulating layers selected from a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, or a silicon oxynitride layer. It can form by a laminated structure.

In addition, by including a halogen element such as chlorine or fluorine in the insulating layer serving as the underlayer, the function of preventing the diffusion of the impurity element from the substrate 400 can be further improved. The concentration of the halogen element contained in the insulating layer serving as the base layer is 1 × 10 ¹⁵ / cm ³ or more and 1 × 10 ²⁰ / cm ³ or less in the concentration peak obtained by analysis using SIMS (secondary ion mass spectrometer). It is good to do.

In addition, you may use gallium oxide as an insulating layer used as a base layer. The insulating layer serving as the base layer may be a laminated structure of gallium oxide and the insulating layer. Since gallium oxide is a material which is hard to charge, the fluctuation of the threshold voltage according to the charge up of an insulating layer can be suppressed.

The material of the gate electrode 401 is aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), scandium Metal materials such as (Sc) or alloy materials containing these elements as a main component, or metal nitrides (titanium nitride, molybdenum nitride, tungsten nitride, etc.) containing these elements as a component, are formed in a single layer or laminated. can do.

Since the conductive layer is also formed as a wiring, it is preferable to use Al or Cu which is a low resistance material. By using Al or Cu, signal delay can be reduced and high image quality can be realized. In addition, Al has low heat resistance, and defects due to hillock, whiskers, or migration are likely to occur. In order to prevent the migration of Al, it is preferable to laminate a metal material having a higher melting point than Al, such as Mo, Ti, and W, on Al.

In addition, when using Cu for a conductive layer, in order to prevent the defect by migration and the diffusion of a Cu element, it is preferable to laminate metal materials with a higher melting point than Cu, such as Mo, Ti, and W.

The gate insulating layer 402 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, or an oxynitride by using a plasma CVD method or a sputtering method. An aluminum layer or a hafnium oxide layer can be formed in a single layer or in a stack. For example, a silicon nitride layer (SiN _y (y> 0)) having a thickness of 50 nm or more and 200 nm or less is formed as a first gate insulating layer by a plasma CVD method, and a film is formed as a second gate insulating layer on the first gate insulating layer. A silicon oxide layer (SiO _x (x> 0)) having a thickness of 5 nm or more and 300 nm or less is laminated to obtain a gate insulating layer having a total film thickness of 200 nm.

The conductive layer used for the source electrode 405a and the drain electrode 405b can be formed with the same material and method as the gate electrode 401. The same material as that of the source electrode 405a and the drain electrode 405b can be used for the conductive layers such as the wiring layer 436a and the wiring layer 436b connected to the source electrode 405a and the drain electrode 405b.

The conductive layer serving as the source electrode 405a and the drain electrode 405b (including a wiring layer formed of such a layer) may be formed of a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide alloy (abbreviated as In ₂ O ₃ -SnO ₂ , ITO), and indium zinc oxide Alloys (In ₂ O ₃ -ZnO) or those containing silicon oxide in the metal oxide material can be used. Moreover, you may use the material which consists of 1-10 sheets of graphene sheets (for 1 layer of graphite).

The insulating layer 407, the insulating layer 427, and the insulating layer 437 formed below the semiconductor layer 403 are typically silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, or the like. Inorganic insulators may be used.

As the protective insulating layer 409 formed on the semiconductor layer 403, an inorganic insulating film such as silicon nitride, aluminum nitride, silicon nitride oxide, aluminum nitride oxide, or the like can be used.

In addition, a planarization insulating layer may be formed on the protective insulating layer 409 in order to reduce surface irregularities caused by the transistor. As the planarization insulating layer, organic materials such as polyimide, acrylic resin, benzocyclobutene resin and epoxy resin can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus glass) and the like can be used. In addition, a planarization insulating layer may be formed by laminating a plurality of insulating layers formed of these materials.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 3)

In this embodiment, an example of the panel of the liquid crystal display device of one embodiment of the present invention will be described with reference to FIGS. 13A and 13B. Moreover, the structural example of the liquid crystal display device of one embodiment of this invention is demonstrated using FIG.

FIG. 13A is a top view of a panel in which a substrate 4001 and an opposing substrate 4006 are bonded together by a sealant 4005, and FIG. 13B is a broken line Z-Z 'in FIG. 13A. Corresponds to the cross-sectional view in.

The seal member 4005 is formed so as to surround the pixel portion 4002 formed on the substrate 4001 and the scanning line driver circuit 4004. An opposing substrate 4006 is formed over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the liquid crystal 4007 by the substrate 4001, the seal member 4005, and the opposing substrate 4006.

The substrate 4021 on which the signal line driver circuit 4003 is formed is mounted in a region different from the region surrounded by the seal member 4005 on the substrate 4001. 13A and 13B illustrate a transistor 4009 included in the signal line driver circuit 4003.

The pixel portion 4002 and the scan line driver circuit 4004 formed on the substrate 4001 include a plurality of transistors on the base layer 4008. In FIG. 13B, the transistor 4022 and the capacitor 4020 included in the pixel portion 4002 are illustrated. The shielding layer 4040 formed on the opposing substrate 4006 overlaps the transistor 4023 of the scanning line driver circuit 4004. By shielding the transistor 4023, it is possible to prevent degradation of the semiconductor layer 403 due to light, and to prevent degradation of characteristics such as shifting of the threshold voltage of the transistor 4023. As the transistors 4022 and 4023, the transistors described in Embodiment 2 can be used.

The back gate electrode 4032 is formed over the transistor 4023 with the planarization insulating layer 4012 interposed therebetween. In addition, the back gate electrode is disposed to sandwich the channel formation region of the semiconductor layer 403 between the gate electrode and the back gate electrode. The back gate electrode is formed of a conductive layer and can function similarly to the gate electrode. In addition, the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode. The back gate electrodes 4032 shown in FIGS. 13A and 13B are formed of the same conductive layer as the pixel electrode 4030.

The pixel electrode 4030 of the liquid crystal element 4011 is formed of a light-transmitting conductive material and electrically connected to the transistor 4022 and the capacitor 4020. Examples of the light-transmitting conductive material include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide alloy (abbreviated as In ₂ O ₃ -SnO ₂ , ITO), and indium oxide Zinc oxide alloys (In ₂ O ₃ -ZnO), or those containing silicon oxide in the metal oxide material can be used. Moreover, you may use the material which consists of 1-10 sheets of graphene sheets (for 1 layer of graphite).

The counter electrode 4031 of the liquid crystal element 4011 is formed on the counter substrate 4006. The portion where the pixel electrode 4030, the counter electrode 4031, and the liquid crystal 4007 overlap each other corresponds to the liquid crystal element 4011. The pixel electrode 4030 overlaps the liquid crystal 4007 with the alignment layer 4034 interposed therebetween, and the counter electrode 4031 overlaps the liquid crystal 4007 with the alignment layer 4035 interposed therebetween.

Examples of the liquid crystal material used for the liquid crystal 4007 include nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular liquid crystal, polymer dispersed liquid crystal (PDLC), and ferroelectric Liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain type polymer liquid crystal, banana type liquid crystal, etc. are mentioned.

Moreover, you may use the liquid crystal which shows the blue phase which does not use an orientation layer. The blue phase is one of the liquid crystal phases, and when the cholesteric liquid crystal is continuously heated, the blue phase is a phase which is expressed immediately before transition from the cholesteric phase to the isotropic phase. Since the blue phase is expressed only in a narrow temperature range, the chiral agent or ultraviolet curing resin is added to improve the temperature range. Since the liquid crystal composition containing the liquid crystal showing a blue phase and a chiral agent is optically isotropic, since an orientation process is unnecessary and a viewing angle dependency is small, it is preferable. Moreover, the liquid crystal which shows a blue phase has a response speed of 10 microseconds. More than 100μsec. Short as Therefore, it is preferable to use a liquid crystal exhibiting a blue phase in a field sequential method requiring high speed operation.

In addition, as a driving method of the liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, VA (Vertical Alignment) mode, MVA (Multi-domain Vertical Alignment) mode, IPS (In-Plane Switching) mode, OCB ( Optically Compensated Birefringence (ECB) Mode, Electrically Controlled Birefringence (ECB) Mode, Ferroelectric Liquid Crystal (FLC) Mode, AntiFerroelectric Liquid Crystal (AFLC) Mode, Polymer Dispersed Liquid Crystal (PDLC) Mode, Polymer Network Liquid Crystal (PNLC) Mode, Guest Host It is possible to apply modes and the like.

The spacer 4036 is a columnar spacer formed of an insulating layer on the counter substrate 4006 and is formed to control the distance (cell gap) between the pixel electrode 4030 and the counter electrode 4031. In addition, although FIG. 13B illustrates the case where the spacer 4036 is formed by patterning the insulating film, a spherical spacer may be used.

In addition, various signals and potentials applied to the signal line driver circuit 4003, the scan line driver circuit 4004, and the pixel portion 4002 are supplied from the connection terminal 4016 through the wiring 4015. The connection terminal 4016 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019.

In addition, glass, ceramics, and plastic can be used for the substrate 4001, the counter substrate 4006, and the substrate 4021. Plastics include fiberglass-reinforced plastics (FRP) plates, polyvinyl fluoride (PVF) films, polyester films, or acrylic resin films.

14 is a perspective view illustrating a configuration example of a liquid crystal display device of one embodiment of the present invention. The liquid crystal display shown in FIG. 14 includes a panel 1601 having a pixel portion, a first diffuser plate 1602, a prism sheet 1603, a second diffuser plate 1604, a light guide plate 1605, and a backlight panel 1607. And a substrate 1611 on which a circuit board 1608 and a signal line driver circuit are formed.

The panel 1601, the first diffusion plate 1602, the prism sheet 1603, the second diffusion plate 1604, the light guide plate 1605, and the backlight panel 1607 are sequentially stacked. The backlight panel 1607 has a backlight 1612 in which a plurality of backlight units 40 are arranged in a matrix. Light from the backlight 1612 diffused into the light guide plate 1605 is irradiated to the panel 1601 by the first diffusion plate 1602, the prism sheet 1603, and the second diffusion plate 1604.

In addition, in this embodiment, although the 1st diffuser plate 1602 and the 2nd diffuser plate 1604 are used, the number of diffuser plates is not limited to this and may be single or 3 or more. Further, the diffusion plate may be formed between the light guide plate 1605 and the panel 1601. Therefore, the diffusion plate may be formed only on the side closer to the panel 1601 than the prism sheet 1603, and the diffusion plate may be formed only on the side closer to the light guide plate 1605 than the prism sheet 1603.

The prism sheet 1603 is not limited to the sawtooth-shaped cross section shown in FIG. 14, and may have a shape capable of condensing light from the light guide plate 1605 toward the panel 1601 side.

In the circuit board 1608, a circuit for generating various signals input to the panel 1601, a circuit for processing these signals, and the like are formed. In this embodiment, the circuit board 1608 and the panel 1601 are electrically connected through the COF tape 1609. The substrate 1611 on which the signal line driver circuit is formed is electrically connected to the COF tape 1609 by using a chip on film (COF) method.

In the present embodiment, an example in which a circuit of a control system for controlling the driving of the backlight 1612 is formed on the circuit board 1608, and the circuit of the control system and the backlight panel 1607 are electrically connected through the FPC 1610. Shows. However, the circuit of the control system may be formed in the panel 1601. In this case, the panel 1601 and the backlight panel 1607 are connected by FPC or the like.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Fourth Embodiment)

In this embodiment, an example of the configuration of an electronic apparatus provided with the display device in the above embodiment is described as one embodiment of the semiconductor device.

The structural example of the electronic device of this embodiment is demonstrated using FIG. 15 (A)-FIG. 15 (D). 15A to 15D are schematic views for explaining a configuration example of an electronic device.

The electronic device shown in Fig. 15A is an example of a portable information communication terminal. The information terminal shown in FIG. 15A includes a case 1001a and a display portion 1002a formed in the case 1001a. Since the liquid crystal display device disclosed in the above-described embodiment does not use a color filter, the light of the backlight can be efficiently transmitted to the viewer. Therefore, by using the liquid crystal display device disclosed in the above-described embodiment for the display portion 1002a, a portable information terminal with low power consumption can be realized.

In addition, one or a plurality of connection terminals for connecting the external device to the side surface 1003a of the case 1001a and buttons for operating the portable information terminal shown in Fig. 15A may be formed.

The portable information terminal shown in Fig. 15A includes a CPU and a main memory in the case 1001a, an interface for transmitting and receiving signals between the external device and the CPU and the main memory, and an antenna for transmitting and receiving signals to and from the external device. do. In addition, one or more integrated circuits having a specific function may be formed in the case 1001a.

As shown in Fig. 15A, by visually recognizing the image of the display portion 1002a using the shutter glasses 1011a, the three-dimensional image can be visually recognized. The eyeglasses 1011a include a left eye shutter 1012a and a right eye shutter 1013a that are configured using liquid crystals. For example, when the image of the display portion 1002a is an image for the left eye, when light is incident on the right eye of the viewer by the right eye shutter 1013a, and when the image of the display portion 1002a is an image for the right eye By blocking light from being incident on the viewer's left eye by the left eye shutter 1012a, the viewer can pseudoly recognize a three-dimensional image. Further, by forming an antenna on the glasses 1011a and receiving a carrier wave containing a control signal by wireless communication, the transmission or blocking of light by the left eye shutter 1012a and the right eye shutter 1013a is controlled. You may also do it.

The portable information terminal shown in Fig. 15A has a function as one or a plurality of telephones, electronic books, personal computers and game machines, for example.

The electronic device shown in Fig. 15B is an example of a clamshell type portable information terminal. The portable information terminal shown in Fig. 15B has a display portion 1002b formed on the case 1001b and the case 1001b, a case 1004, a display portion 1005 formed on the case 1004, and a case 1001b. ) And a shaft portion 1006 connecting the case 1004.

In the portable information terminal illustrated in FIG. 15B, the case 1001b can be superimposed on the case 1004 by moving the case 1001b or the case 1004 by the shaft portion 1006.

In addition, one of a terminal for connecting an external device to the side surface 1003b of the case 1001b or the side surface 1007 of the case 1004 and a button for operating the portable information terminal shown in Fig. 15B. Alternatively, a plurality may be formed.

In addition, the display unit 1002b and the display unit 1005 may display different images or successive images. Note that the display portion 1005 does not necessarily need to be formed, and a keyboard, which is an input device, may be provided instead of the display portion 1005.

In addition, the portable information terminal shown in Fig. 15B includes a CPU and a main memory, and an interface for transmitting and receiving signals between an external device, a CPU, and a main memory in the case 1001b or the case 1004. One or more integrated circuits having a specific function may be formed in the case 1001b or the case 1004. In addition, the portable information terminal shown in Fig. 15B may be provided with an antenna for transmitting and receiving signals with the outside.

As shown in Fig. 15B, by using the shutter glasses 1011b to visually recognize the image of the display portion 1002b or the display portion 1005, three-dimensional images can be visually recognized. The spectacles 1011b include a left eye shutter 1012b and a right eye shutter 1013b that are configured using liquid crystal. For example, when the image of the display portion 1002b or the display portion 1005 is an image for the left eye, light is prevented from entering the viewer's right eye by the right eye shutter 1013b, and the display portion 1002b or the display portion ( When the image of 1005 is a right eye image, the viewer can recognize a three-dimensional image by blocking light from being incident on the left eye of the viewer by the left eye shutter 1012b. In addition, by transmitting an antenna to the glasses 1011b and receiving a carrier wave including a control signal by wireless communication, the transmission or blocking of light by the left eye shutter 1012b and the right eye shutter 1013b may be controlled. .

The portable information terminal shown in Fig. 15B has a function as one or more of a telephone, an electronic book, a personal computer and a game machine.

The electronic device shown in FIG. 15C is an example of an installed type information terminal. The installation type information terminal shown in FIG. 15C includes a case 1001c and a display portion 1002c formed in the case 1001c.

In addition, the display portion 1002c may be formed in the deck portion 1008 of the case 1001c.

The installed type information terminal shown in FIG. 15C includes a CPU and a main memory in the case 1001c, and an interface for transmitting and receiving signals between an external device, the CPU, and the main memory. In addition, one or more integrated circuits having a specific function may be formed in the case 1001c. In addition, the installation type information terminal shown in FIG. 15C may be provided with an antenna for transmitting and receiving signals to and from the outside.

In addition, one or more of a ticket output part, a coin input part, and a banknote insertion part which output a ticket etc. to the side surface 1003c of the case 1001c in the mounting type information terminal shown to FIG. 15C. May be formed.

As shown in Fig. 15C, by visually recognizing the image of the display portion 1002c using the shutter glasses 1011c, the three-dimensional image can be visually recognized. The spectacles 1011c include a left eye shutter 1012c and a right eye shutter 1013c that are configured using liquid crystal. For example, when the image of the display portion 1002c is an image for the left eye, the light is blocked from entering the right eye of the viewer by the right eye shutter 1013c, and when the image of the display portion 1002c is the image for the right eye By blocking light from being incident on the viewer's left eye by the left eye shutter 1012c, the viewer can pseudoly recognize a three-dimensional image. In addition, by transmitting an antenna to the glasses 1011c and receiving a carrier wave including a control signal by wireless communication, the transmission or blocking of light by the left eye shutter 1012c and the right eye shutter 1013c may be controlled. .

The installed information terminal shown in Fig. 15C has a function as, for example, an information communication terminal (also called a multi media station) or a game machine for obtaining an ATM, a ticket, or the like.

The electronic device shown in FIG. 15D is an example of an installed type information terminal. The mounting type information terminal shown in FIG. 15D includes a case 1001d and a display portion 1002d formed in the case 1001d. Moreover, you may provide the support stand which supports the case 1001d.

In addition, one or a plurality of connection terminals for connecting the external device to the side surface 1003d of the case 1001d and buttons for operating the mounting type information terminal shown in Fig. 15D may be formed.

In addition, the installed type information terminal shown in FIG. 15D may be provided with a CPU and a main memory, and an interface for transmitting and receiving signals to and from an external device, the CPU, and the main memory in the case 1001d. In addition, one or more integrated circuits having a specific function may be formed in the case 1001d. In addition, an antenna for transmitting and receiving signals to and from the outside of the installed information terminal shown in Fig. 15D may be provided.

As shown in Fig. 15D, by visually recognizing the image of the display portion 1002d using the shutter glasses 1011d, it is possible to visually visualize the three-dimensional image. The glasses 1011d include a left eye shutter 1012d and a right eye shutter 1013d that are configured using liquid crystals. For example, when the image of the display portion 1002d is an image for the left eye, when the image of the display portion 1002d is an image for the right eye, the light is prevented from entering the right eye of the viewer by the right eye shutter 1013d. By blocking light from being incident on the viewer's left eye by the left eye shutter 1012d, the viewer can pseudoly display a three-dimensional image. In addition, by transmitting an antenna to the glasses 1011d and receiving a carrier wave including a control signal by wireless communication, the transmission or blocking of light by the left eye shutter 1012d and the right eye shutter 1013d may be controlled. .

In addition, the installation type information terminal shown in FIG. 15D has a function as a digital photo frame, an input / output monitor, or a television apparatus, for example.

The liquid crystal display device of the above-mentioned embodiment is used as a display part of an electronic device, for example, and is used as the display part 1002a-display part 1002d shown to FIG. 15A-FIG. 15D, for example. In addition, you may use the liquid crystal display device of embodiment mentioned above as the display part 1005 shown to FIG. 15 (B).

As demonstrated using FIG.15 (A)-FIG.15D, an example of the electronic device of this embodiment is a structure provided with the display part where the liquid crystal display device in the said embodiment was used. By setting it as the said structure, the image of a display part can be visually recognized as a three-dimensional image.

In addition, as an example of the electronic apparatus of this embodiment, you may form in the case any one or multiple of the photoelectric conversion part which produces | generates a power supply voltage, and the operation part which operates a liquid crystal display device according to the illumination intensity which injects. For example, by forming a photoelectric conversion unit, the electronic device can be used for a long time even in a place without an external power source.

101: area
102: area
103: area
310: Image display period for the right eye
311: Color Display Period
312: Color Display Period
313: color display period
314: black display period
318: shutter opening period for the right eye
319: left eye shutter closure period
320: Image display period for the left eye
321: color display period
322: color display period
323: Color Display Period
324: black display period
328: shutter closing period for right eye
329: Left eye shutter opening period

Claims (16)

As a display device,
A pixel portion having a first region and a second region;
A first pixel of the first region;
A second pixel of the second region;
A first backlight unit superimposed on the first pixel;
A second backlight unit superimposed on the second pixel,
As a driving method of the display device,
Supplying a first color signal to the first pixel in a first sub frame period;
Supplying light of a first color to the first pixel by the first backlight unit according to the first color signal;
Supplying a second color signal to the second pixel in the first sub frame period;
Supplying light of a second color to the second pixel by the second backlight unit according to the second color signal;
And turning off the first backlight unit and the second backlight unit in a second sub frame period.
The method of claim 1,
And the first color and the second color are different from each other.
As a display device,
A pixel portion having a first region and a second region;
A first pixel of the first region;
A second pixel of the second region;
A first backlight unit superimposed on the first pixel;
A second backlight unit superimposed on the second pixel,
Each of the right eye image display period and the left eye image display period each include a first sub frame period and a second sub frame period,
As a driving method of the display device,
Supplying a first color signal to the first pixel in the first sub frame period;
Supplying light of a first color to the first pixel by the first backlight unit according to the first color signal;
Supplying a second color signal to the second pixel in the first sub frame period;
Supplying light of a second color to the second pixel by the second backlight unit according to the second color signal;
Turning off the first backlight unit and the second backlight unit in the second sub frame period;
And the right eye image display period and the left eye image display period are alternately provided.
The method of claim 3, wherein
And the first color and the second color are different from each other.
As a display device,
A pixel portion having a first region, a second region adjacent to the first region, and a third region adjacent to the second region;
A first pixel of the first region;
A second pixel of the second region;
A third pixel of the third region;
A first backlight unit superimposed on the first pixel;
A second backlight unit superimposed on the second pixel;
A third backlight unit superimposed on the third pixel,
As a driving method of the display device,
Supplying a first color signal to the first pixel in a first sub frame period;
Supplying light of a first color to the first pixel by the first backlight unit in accordance with the first color signal in the first sub frame period;
Supplying a third color signal to the second pixel in the first sub frame period;
Supplying light of a third color to the second pixel by the second backlight unit in accordance with the third color signal in the first sub frame period;
Supplying a second color signal to the third pixel in the first sub frame period;
Supplying light of a second color to the third pixel by the third backlight unit in accordance with the second color signal in the first sub frame period;
Supplying the second color signal to the first pixel in a second sub frame period;
Supplying light of the second color to the first pixel by the first backlight unit in accordance with the second color signal in the second sub frame period;
Supplying the first color signal to the second pixel in the second sub frame period;
Supplying light of the first color to the second pixel by the second backlight unit in accordance with the first color signal in the second sub frame period;
Supplying the third color signal to the third pixel in the second sub frame period;
Supplying light of the third color to the third pixel by the third backlight unit in accordance with the third color signal in the second sub frame period;
Supplying the third color signal to the first pixel in a third sub frame period;
Supplying light of the third color to the first pixel by the first backlight unit in accordance with the third color signal in the third sub frame period;
Supplying the second color signal to the second pixel in the third sub frame period;
Supplying light of the second color to the second pixel by the second backlight unit in accordance with the second color signal in the third sub frame period;
Supplying the first color signal to the third pixel in the third sub frame period;
Supplying light of the first color to the third pixel by the third backlight unit in accordance with the first color signal in the third sub frame period;
And turning off the first backlight unit, the second backlight unit, and the third backlight unit in a fourth sub frame period.
The method of claim 5, wherein
A color signal contained in the first area in the first sub frame period and held in the pixel adjacent to the second area is the same signal as the color signal held in the pixel in the fourth sub frame period Method of driving the device.
The method of claim 5, wherein
A color signal contained in the second region in the first sub frame period and held in the pixel adjacent to the third region is the same signal as the color signal held in the pixel in the fourth sub frame period Method of driving the device.
The method of claim 5, wherein
A color signal contained in the second region in the fourth sub frame period and held in the pixel adjacent to the first region is the same signal as the color signal held in the pixel in the first sub frame period Method of driving the device.
The method of claim 5, wherein
A color signal contained in the third region in the fourth sub frame period and held in the pixel adjacent to the second region is the same signal as the color signal held in the pixel in the first sub frame period Method of driving the device.
The method of claim 5, wherein
The first color, the second color, and the third color are different from each other.
As a display device,
A pixel portion having a first region, a second region adjacent to the first region, and a third region adjacent to the second region;
A first pixel of the first region;
A second pixel of the second region;
A third pixel of the third region;
A first backlight unit superimposed on the first pixel;
A second backlight unit superimposed on the second pixel;
A third backlight unit superimposed on the third pixel,
Each of the right eye image display period and the left eye image display period each include a first sub frame period, a second sub frame period, a third sub frame period, and a fourth sub frame period,
As a driving method of the display device,
Supplying a first color signal to the first pixel in the first sub frame period;
Supplying light of a first color to the first pixel by the first backlight unit in accordance with the first color signal in the first sub frame period;
Supplying a third color signal to the second pixel in the first sub frame period;
Supplying light of a third color to the second pixel by the second backlight unit in accordance with the third color signal in the first sub frame period;
Supplying a second color signal to the third pixel in the first sub frame period;
Supplying light of a second color to the third pixel by the third backlight unit in accordance with the second color signal in the first sub frame period;
Supplying the second color signal to the first pixel in the second sub frame period;
Supplying light of the second color to the first pixel by the first backlight unit in accordance with the second color signal in the second sub frame period;
Supplying the first color signal to the second pixel in the second sub frame period;
Supplying light of the first color to the second pixel by the second backlight unit in accordance with the first color signal in the second sub frame period;
Supplying the third color signal to the third pixel in the second sub frame period;
Supplying light of the third color to the third pixel by the third backlight unit in accordance with the third color signal in the second sub frame period;
Supplying the third color signal to the first pixel in the third sub frame period;
Supplying light of the third color to the first pixel by the first backlight unit in accordance with the third color signal in the third sub frame period;
Supplying the second color signal to the second pixel in the third sub frame period;
Supplying light of the second color to the second pixel by the second backlight unit in accordance with the second color signal in the third sub frame period;
Supplying the first color signal to the third pixel in the third sub frame period;
Supplying light of the first color to the third pixel by the third backlight unit in accordance with the first color signal in the third sub frame period;
Turning off the first backlight unit, the second backlight unit, and the third backlight unit in a fourth sub frame period at all times;
And the right eye image display period and the left eye image display period are alternately provided.
The method of claim 11,
A color signal contained in the first area in the first sub frame period and held in the pixel adjacent to the second area is the same signal as the color signal held in the pixel in the fourth sub frame period Method of driving the device.
The method of claim 11,
A display device wherein the color signal held in the pixel adjacent to the third region in the first sub frame period is the same as the color signal held in the pixel in the fourth sub frame period Method of driving.
The method of claim 11,
A display device in which the color signal is retained in the pixel adjacent to the first area in the fourth sub frame period and is the same as the color signal retained in the pixel in the first sub frame period. Method of driving.
The method of claim 11,
And a color signal held in the pixel adjacent to the second region in the fourth sub frame period is the same as the color signal held in the pixel in the first sub frame period. Method of driving.
The method of claim 11,
The first color, the second color, and the third color are different from each other.

Images