KR20120055218A - Apparatus for fault analysis for a security processor - Google Patents

Abstract

PURPOSE: An erroneous input sub channel analysis test device of a security processor is provided to supply a power and clock module, thereby easily testing erroneous input of the security processor. CONSTITUTION: A control unit(210) receives an erroneous input test setting value from an analysis system(110). The control unit generates a power control signal and a clock control signal. The control unit inputs an error about a security processor(240). A power control module(220) supplies normal power or erroneously input power to the security processor. A clock control module(230) supplies a normal clock and an erroneously input clock to the security processor.

Description

Error injection side channel analysis test device of security processor {APPARATUS FOR FAULT ANALYSIS FOR A SECURITY PROCESSOR}

The present invention relates to an error injection test apparatus, and more particularly, to an error injection subchannel analysis test apparatus of a security processor that can be universally applied to various security processors and can easily implement and test an error injection function.

With the advent of the information society, the protection of information using cryptographic algorithms and cryptographic protocols is increasing in importance. Side Channel Attack is one of the powerful attack techniques for cryptographic algorithms. Because of this, side-channel analytics is becoming a huge threat to security products.

The subchannel analysis technique measures physical characteristics such as communication execution time, power consumption, and electromagnetic radiation, and obtains information related to the internal encryption key from the subchannel. In other words, one of the sub-channel analysis techniques uses power or electromagnetic signals generated during the operation of a secure processor, and gradually injects an error into the processor to cause a malfunction, and analyzes the sub-channel using additional information and results generated at this time. Techniques for doing this are being developed.

However, error injection that causes a malfunction within the range in which the secure processor operates is very difficult, and in particular, there is a difficulty in implementing a universally usable device.

In order to solve the above problems, an object of the present invention is not only to easily implement the error injection function through the power control and clock control, but also the error injection subchannel analysis test of the security processor capable of performing subchannel analysis according to the error injection. To provide a device.

The object of the present invention is not limited to the above-mentioned object, and other objects which are not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, an error injection subchannel analysis test apparatus of a security processor according to an embodiment of the present invention is an error injection subchannel analysis test apparatus of a security processor including a security processor that performs a cryptographic operation. The control unit inputs an error injection test set value consisting of a power and a clock from a system to generate a power control signal and a clock control signal, and inputs an error to the security processor, and a normal power or error injection according to the power control signal. A power control module for supplying power to the security processor, and a clock control module for providing a normal clock or an error-injected clock to the security processor in accordance with the cool-lock control signal, wherein the control unit comprises: the clock control module and the power supply; The security according to the clock and power provided from the control module When the processor performs a cryptographic operation, an error is input to the security processor, and the cryptographic operation result of the security processor when the security processor operates according to the input of the error is provided to the analysis system.

In the error injection subchannel analysis test apparatus of the security processor according to an embodiment of the present invention, the power control module may include a variable resistor unit whose resistance is changed based on the power control signal, and a power source variable according to the change of the resistance. It characterized in that it comprises a power supply regulator for supplying.

In the error injection subchannel analysis test apparatus of the security processor according to an embodiment of the present invention, the power control module is connected to the variable resistor unit to generate an impulse voltage according to the power control signal to provide a power boost to the power regulator It characterized in that it comprises a conversion unit.

In the error injection subchannel analysis test apparatus of the security processor according to an embodiment of the present invention, the clock control module includes an oscillator for generating the normal clock, a variable oscillator for generating a variable clock that is the error injection clock, and the clock signal. And a switch for outputting the normal clock or the variable clock by switching according to a signal.

In the error injection subchannel analysis test apparatus of the security processor according to an embodiment of the present invention, the clock control module may include a variable resistor unit whose resistance is changed according to the clock control signal, and an impulse according to the variable resistor of the variable resistor unit. And a diode for generating a power boost converter and adding an impulse of the power boost converter to a clock generated by the clock control module.

The present invention provides a power supply and a clock module to easily perform an error injection test of the security processor, and can provide an error injection test procedure using the same, as well as implementing both an error injection test apparatus and a power measurement module. This allows for more complex and sophisticated subchannel analysis tests.

1 is a block diagram illustrating an error injection subchannel analysis test apparatus and its peripheral configuration of a security processor according to an embodiment of the present invention;
2 is a block diagram illustrating a detailed configuration of a power control module of an error injection subchannel analysis test apparatus of a security processor according to an embodiment of the present invention;
3 is a block diagram illustrating a configuration for controlling an impulse output from a power supply control module according to an embodiment of the present disclosure;
4 is a block diagram showing a detailed configuration of a clock control module according to an embodiment of the present invention;
5 is a flowchart illustrating a process of analyzing a subchannel using an error injection subchannel analysis test apparatus of a security processor according to an exemplary embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions in the embodiments of the present invention, which may vary depending on the intention of the user, the intention or the custom of the operator. Therefore, the definition should be based on the contents throughout this specification.

Each block of the accompanying block diagrams and combinations of steps of the flowchart may be performed by computer program instructions. These computer program instructions may be mounted on a processor of a general purpose computer, special purpose computer, or other programmable data processing equipment such that instructions executed through the processor of the computer or other programmable data processing equipment may not be included in each block or flowchart of the block diagram. It will create means for performing the functions described in each step. These computer program instructions may be stored in a computer usable or computer readable memory that can be directed to a computer or other programmable data processing equipment to implement functionality in a particular manner, and thus the computer usable or computer readable memory. It is also possible for the instructions stored in to produce an article of manufacture containing instruction means for performing the functions described in each block or flowchart of each step of the block diagram. Computer program instructions may also be mounted on a computer or other programmable data processing equipment, such that a series of operating steps may be performed on the computer or other programmable data processing equipment to create a computer-implemented process to create a computer or other programmable data. Instructions that perform processing equipment may also provide steps for performing the functions described in each block of the block diagram and in each step of the flowchart.

In addition, each block or step may represent a portion of a module, segment or code that includes one or more executable instructions for executing a specified logical function (s). It should also be noted that in some alternative embodiments, the functions mentioned in the blocks or steps may occur out of order. For example, the two blocks or steps shown in succession may in fact be executed substantially concurrently or the blocks or steps may sometimes be performed in the reverse order, depending on the functionality involved.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram illustrating an error injection subchannel analysis test apparatus and a peripheral configuration of a security processor according to an exemplary embodiment of the present invention. The analysis system 100, the error injection test apparatus 200, and a waveform measurement system ( 300) and the like.

The analysis system 100 may provide the error injection test set value, the cryptographic operation control, and the data to the error injection test apparatus 200, and receive the waveform measurement data from the waveform measurement system 300 to perform a rain injection analysis. . Here, the error injection test set value can be largely divided into a power supply and a clock. The power supply is used to set functions such as an impulse, a variable within a VDD, a cutoff, an operation start point and an operation interval of each function, and a clock. May be used to set a function such as a variable high frequency and a high impulse within a frequency, an operation start time and an operation period of each function.

The analysis system 100 adjusts the power and the clock in the error injection test set value and provides the error injection test apparatus 200 to the error injection test apparatus 200 and outputs the cryptographic calculation result data and the waveform measurement system 300. The error injection analysis for the subchannels can be performed based on the power waveform measurement data provided from

The error injection test apparatus 200 performs an encryption operation by controlling a power and a clock according to the error injection test setting value, and inputs an error according to the error injection test setting value when the encryption operation is performed, and then the password according to the error input. The calculation result data is provided to the analysis system 100, and for this purpose, the controller 210, the power control module 220, the clock control module 230, the security processor 240, and the power measurement module 250 are configured. Can be.

The controller 210 performs communication such as data and control necessary for cryptographic operation between the security processor 240 to be tested and the analysis system 100, and controls the power control module 220 and the clock according to the error injection test setting value. Module 230 can be controlled.

The power control module 220 is for supplying error-injected power such as normal power, impulse, variable voltage, and blocking to the security processor 240. As shown in FIG. 2, the digital variable resistor unit 222 made of a variable resistor. ), A power regulator 224 for providing a normal power supply (VDD), a power boost converter 226 for supplying an impulse power, and the like.

The power control module 220 adjusts the variable resistance of the digital variable resistor unit 222 to provide a normal power source (VDD) to the security processor 240 or to provide a variable or blocked power source (VDD) to the security processor 240. Can provide. Here, the variable resistance of the digital variable resistor unit 222 may be controlled by the controller 210, that is, the variable resistor value may be changed according to the error injection test set value.

On the other hand, the power control module 220 outputs a high impulse power by using the power boost converter 226, by outputting the output impulse to the normal power supply (VDD) through the diode (D), impulse injection error The supplied power to the security processor 240.

The clock control module 230 may generate a clock to which a variable clock or an impulse is added and provide the clock to the security processor 240. As shown in FIG. 3, the clock control module 230 is switched according to the control of the oscillator 232 for generating a normal clock, the variable oscillator 234 for generating a variable clock, and the controller 210. The switch 236 may include a digital variable resistor 237, a power boost converter 238, and the like to provide an impulse clock.

The clock control module 230 may select and output any one of the outputs of the oscillator 232 and the variable oscillator 234 according to the operation of the switch 236. The variable oscillator 234 for generating a variable clock may be implemented by installing a plurality of oscillators and switching them or switching the oscillators in a socket manner.

Meanwhile, the digital variable resistor 237 and the power boost converter 238 of the clock control module 230 may be controlled to generate an impulse having a high impulse power supply. In addition, it may be provided to the security processor 240.

The security processor 240 performs an encryption operation according to the power and the clock output from the power control module 220 and the clock control module 230, and may provide the encryption operation result data to the controller 210.

The power measurement module 250 may measure the power when the security processor 240 performs the cryptographic operation and the power according to the error injection during the cryptographic operation to provide the waveform analysis system 100.

The waveform analysis system 100 may generate the power waveform data by analyzing the power measured by the power measurement module 250 and provide the generated power waveform data to the analysis system 100.

The operation of the error injection test apparatus having the above configuration will be described with reference to FIG. 4.

4 is a flowchart illustrating an operation of an error injection subchannel analysis system according to an exemplary embodiment of the present invention.

As shown in FIG. 4, first, the controller 210 of the error injection test apparatus 200 is provided with an error injection test set value generated by the analysis system 100 (S400).

Thereafter, the controller 210 generates a normal power and a normal clock through the control of the power control module 220 and the clock control module 230 to operate the security processor 240, and the security processor 240 operates. After performing the cryptographic operation, the power control module 220 and the clock control module 230 are controlled based on the error injection test set value to provide the security processor 240 with the error injected power and clock ( S402). Here, the security processor 240 may provide a predetermined trigger signal to the controller 210 when the cryptographic operation is started after the operation is performed, and the controller 210 may supply an error-injected power and clock based on the trigger signal. The power control module 220 and the clock control module 230 may be controlled to be provided to the security processor 240.

In an exemplary embodiment of the present invention, the error injection test set value is provided before the operation of the security processor 240. However, after the security processor 240 is operated according to a normal power source and a clock, a trigger signal from the security processor 240 is generated. When received, the request may be provided to the analysis system 100.

Thereafter, the controller 210 determines whether the security processor 240 performs a cryptographic operation after error injection (S404).

As a result of the determination in S404, when the security processor 240 performs the cryptographic operation, the controller 210 receives the cryptographic operation result data according to the cryptographic operation from the security processor 240, and provides the data to the analysis system 100. The measurement module 250 measures power during operation of the security processor 240 according to the error injection, and provides the measured power to the waveform analysis system 100 in operation S406. The waveform analysis system 100 analyzes the waveform of the measured power and provides it to the analysis system 100. The analysis system 100 analyzes the subchannels according to the error injection based on the encryption operation result data and the waveform of the power ( S408).

Meanwhile, as a result of the determination of S404, when the security processor 240 does not perform the cryptographic operation, the controller 210 changes the error injection test setting value (S410) and provides the security processor 240, that is, the changed error injection. After controlling the power control module 220 and the clock control module 230 according to the test setting value, the changed error injection power and the clock are provided to the security processor 240, and then the process proceeds to S404 to perform a subsequent step.

According to an embodiment of the present invention, the error injection test of the security processor can be easily performed by using the power supply and the clock control module to perform a more complicated and sophisticated subchannel analysis test.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. For example, those skilled in the art can change each component according to the field of application, or combine or substitute the disclosed embodiments in a form that is not clearly disclosed in the embodiments of the present invention, but this is also within the scope of the present invention. It is not. Therefore, the above-described embodiments are to be considered in all respects as illustrative and not restrictive, and such modified embodiments should be included in the technical spirit described in the claims of the present invention.

100: Analysis System
200: error injection test device
210: control unit
220: power control module
230: clock control module
240: security processor
250: power measurement module
300: waveform measurement system

Claims (1)

An error injection subchannel analysis test apparatus having a security processor that performs a cryptographic operation,
A control unit which receives an error injection test set value including power and clock from an analysis system, generates a power control signal and a clock control signal, and inputs an error for the security processor;
A power control module configured to provide normal power or error-injected power to the security processor according to the power control signal;
A clock control module configured to provide a normal clock or an error-injected clock to the security processor according to the cool clock control signal,
The controller inputs an error to the security processor when the security processor performs an encryption operation according to the clock and power provided from the clock control module and the power control module, and the security processor operates according to the input of the error. Characterized in that it provides the result of the cryptographic operation of the security processor to the analysis system.
Error injection side channel analysis test device of the security processor.

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