KR20120054757A - Semiconductor package - Google Patents

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KR20120054757A
KR20120054757A KR1020100116030A KR20100116030A KR20120054757A KR 20120054757 A KR20120054757 A KR 20120054757A KR 1020100116030 A KR1020100116030 A KR 1020100116030A KR 20100116030 A KR20100116030 A KR 20100116030A KR 20120054757 A KR20120054757 A KR 20120054757A
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semiconductor chip
solder ball
bump
semiconductor device
attached
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KR1020100116030A
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Korean (ko)
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KR101185455B1 (en
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이정석
김인태
김윤주
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020100116030A priority Critical patent/KR101185455B1/en
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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A semiconductor device is provided to buffer stress according to a warpage phenomenon by supporting an input/output terminal such as a solder ball or a bump attached on the outer side of a semiconductor chip using a support member. CONSTITUTION: A semiconductor chip(10) comprises an electrode pad(14). The electrode pad is arranged on the whole area of the semiconductor chip with an equal distance from each other. A bump or a solder ball(40) is attached on the electrode pad. A support member(60) arranges a passivation material(62) for reducing stress on an uppermost second passivation film(20). The support member supports the bump or the solder ball on the surface of the semiconductor chip.

Description

반도체 장치{Semiconductor package}Semiconductor device {Semiconductor package}

본 발명은 반도체 장치에 관한 것으로서, 더욱 상세하게는 반도체 칩의 솔더 또는 구리필러가 범핑된 위치에서 그 주변에 스트레스 완화용 패시베이션을 형성시킨 새로운 구조의 반도체 장치에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a novel structure in which stress relaxation passivation is formed around a solder or copper filler bump of a semiconductor chip.

통상적으로, 반도체 패키지는 기판에 반도체 칩을 부착하고, 반도체 칩과 기판간을 도전성 와이어로 연결한 후, 반도체 칩과 와이어 등을 몰딩 컴파운드 수지로 봉지시킨 구조로 제조되고 있다.In general, a semiconductor package is manufactured by attaching a semiconductor chip to a substrate, connecting the semiconductor chip and the substrate with a conductive wire, and then sealing the semiconductor chip and the wire with a molding compound resin.

이러한 반도체 패키지의 구성중, 기판과 반도체 칩을 전기적 신호 교환 가능하게 연결하는 도전성 와이어는 소정의 길이를 갖기 때문에 실질적으로 반도체 패키지의 좌우 및 상하방향 크기를 증가시키는 원인이 되고 있고, 특히 칩 적층시 도전성 와이어는 오히려 간섭 요인으로 작용함에 따라, 반도체 패키지를 소형화시키기 위한 노력에 역행하는 요인이 되고 있다.In the configuration of such a semiconductor package, since the conductive wire connecting the substrate and the semiconductor chip so as to be capable of electrical signal exchange has a predetermined length, it is a cause of substantially increasing the size of the semiconductor package in the left and right directions, and particularly in the case of chip stacking. As the conductive wire acts as an interference factor, it has become a factor against the efforts to miniaturize the semiconductor package.

따라서, 반도체 칩의 전극패드(=본딩패드)에 솔더 또는 금속 재질의 범프를 직접 형성하고, 이 범프를 매개로 반도체 칩들을 상호 적층하거나, 반도체 칩과 기판을 전기적으로 연결시키는 반도체 패키지가 제안되고 있다.Accordingly, a semiconductor package is proposed in which bumps made of solder or metal are directly formed on electrode pads (= bonding pads) of a semiconductor chip, and semiconductor chips are laminated to each other or electrically connected between the semiconductor chip and a substrate through the bumps. have.

여기서, 종래의 범프 구조를 첨부한 도 6을 참조로 설명하면 다음과 같다.Here, with reference to Figure 6 attached to the conventional bump structure as follows.

먼저, 반도체 칩(10, 실리콘 기판)위에 제1패시베이션 막(18)이 형성된다.First, the first passivation film 18 is formed on the semiconductor chip 10 (silicon substrate).

이때, 반도체 칩(10)상에 소정의 배열을 이루는 다수의 전극패드 즉, 본딩패드(12)상에는 제1패시베이션 막(18)이 도포되지 않는데, 그 이유는 본딩패드(12)상에 반도체 소자를 작동시키는 전압 등을 인가받기 위한 일종의 전극단자인 언더 범프 메탈(14,Under Bump Matal, 이하 전극패드로 칭함)이 형성되기 때문이다.In this case, the first passivation film 18 is not coated on the plurality of electrode pads, that is, the bonding pads 12, which are arranged on the semiconductor chip 10, for the reason that the semiconductor device is formed on the bonding pads 12. This is because an under bump metal 14 (hereinafter, referred to as an electrode pad) is formed, which is a kind of electrode terminal for receiving a voltage for operating the device.

위와 같이, 상기 본딩패드(12) 위에 전극단자인 전극패드(14)가 형성된 후, 상기 제1패시베이션 막(18) 위에 다시 제2패시베이션 막(20)이 더 형성될 수 있으며, 이 제2패시베이션 막(20)은 외부로부터의 기계적 충격, 수분, 각종 이물질 등을 차단하는 기능 외에 반도체 칩(10)의 전체 표면을 평탄화시키면서 각 전극패드(14)간의 절연 기능을 수행하게 된다.As described above, after the electrode pad 14, which is an electrode terminal, is formed on the bonding pad 12, the second passivation film 20 may be further formed on the first passivation film 18, and the second passivation may be performed. The film 20 serves to insulate between the electrode pads 14 while planarizing the entire surface of the semiconductor chip 10 in addition to blocking mechanical shocks, moisture, and various foreign matters from the outside.

이러한 상태에서, 도 6의 (a)에서 보듯이 전극패드(14)에 전기적 입출력단자로서 범프(30)가 융착되거나, 또는 도 6의 (b)에서 보듯이 전극패드(14)에 전기적 입출력단자로서 솔더볼(40)이 융착되어진다.In this state, as shown in FIG. 6A, the bumps 30 are fused as the electric input / output terminals to the electrode pads 14, or as shown in FIG. 6B, the electric input / output terminals are connected to the electrode pads 14. As a result, the solder ball 40 is fused.

상기 범프(30)는 구리 도금 공정을 진행하여 전극패드(14)상에 소정의 높이로 형성되는 구리필러(32)와, 이 구리필러(30)의 상면에 일체로 형성되는 전도성 솔더(34)로 구성된다.The bump 30 may be formed of a copper filler 32 having a predetermined height on the electrode pad 14 by a copper plating process, and a conductive solder 34 integrally formed on an upper surface of the copper filler 30. It consists of.

즉, 상기 범프(30)를 형성하기 위하여, 전극패드(14)상에 구리필러(32)가 먼저 도금된 후, 그 위에 전도성 솔더(34)가 도금된다.That is, in order to form the bump 30, the copper filler 32 is first plated on the electrode pad 14, and then the conductive solder 34 is plated thereon.

이렇게 반도체 칩(10)의 본딩패드에 형성된 일종의 전극단자인 전극패드(14)에 입출력수단인 범프(30) 또는 솔더볼(40)이 일체로 범핑된 상태에서, 각 범프(30) 또는 솔더볼(40)이 적층 대상의 칩 또는 기판의 본딩영역 등에 본딩된다.As such, bumps 30 or solder balls 40 serving as input / output means are integrally bumped to the electrode pads 14, which are a kind of electrode terminals formed on the bonding pads of the semiconductor chip 10, and the bumps 30 or the solder balls 40 are formed. ) Is bonded to the bonding area of the chip or substrate to be stacked.

보다 상세하게는, 적층 대상의 칩 또는 기판과 같은 상대부품의 본딩영역에 반도체 칩의 범프(30) 또는 솔더볼(40)을 접착시키되, 리플로우 방법 또는 소정의 온도에서 가압하는 써멀 컴프레션 방법을 이용하여 범프(30) 또는 솔더볼(40)을 상대부품의 본딩영역에 접착시킴으로써, 반도체 칩간의 적층이 이루어지거나, 반도체 칩이 기판에 도전 가능하게 연결된다.More specifically, the bump 30 or the solder ball 40 of the semiconductor chip is bonded to a bonding area of a counterpart such as a chip or a substrate to be stacked, but a reflow method or a thermal compression method is applied at a predetermined temperature. By bonding the bumps 30 or the solder balls 40 to the bonding regions of the counterpart parts, the semiconductor chips are laminated or the semiconductor chips are electrically connected to the substrate.

그러나, 상기와 같이 범프 또는 솔더볼이 범핑된 반도체 칩을 적층 대상 칩 또는 기판 등에 실장하는 과정에서 다음과 같은 문제점이 있다.However, in the process of mounting a semiconductor chip bumped or solder ball bumped as described above, such as a stacking target chip or a substrate, there are the following problems.

반도체 칩의 전체 면적에 걸쳐 고르게 형성된 전극패드에 범프 또는 솔더볼이 부착된 상태에서, 이 범프 또는 솔더볼을 적층 대상 칩 또는 기판에 접착시키며 실장시키게 되는데, 이때 반도체 칩의 외곽 부분에 대한 스트레스가 더 많이 발생하여 외곽 부분에 있는 범프 또는 솔더볼 형상이 변형되는 등의 문제점이 있었다.With the bumps or solder balls attached to the electrode pads evenly formed over the entire area of the semiconductor chip, the bumps or solder balls are bonded to the stacking chip or the substrate and mounted thereon, with more stress on the outer portion of the semiconductor chip. There was a problem such that the bump or solder ball shape in the outer portion is deformed.

특히, 첨부한 도 7에서 보듯이 반도체 칩의 범프 또는 솔더볼을 기판의 본딩영역에 접착시키는 고온의 리플로우 공정중, 반도체 칩(10)과 기판(50) 간의 열팽창계수 차이로 인하여 워피지(휨: warpage) 현상이 발생됨에 따라, 반도체 칩의 외곽쪽으로 갈수록 점차 많은 스트레스를 받게 되고, 이 스트레스로 인하여 반도체 칩(10)의 외곽쪽 범프(30) 또는 솔더볼(40)에 더 많은 변형이 발생되는 문제점이 있었다.
In particular, during the high temperature reflow process in which bumps or solder balls of a semiconductor chip are bonded to a bonding region of a substrate, as shown in FIG. 7, warpage (warpage) may occur due to a difference in thermal expansion coefficient between the semiconductor chip 10 and the substrate 50. As the warpage phenomenon occurs, more and more stress is applied toward the outer side of the semiconductor chip, and the stress causes more deformation in the outer bump 30 or the solder ball 40 of the semiconductor chip 10. There was a problem.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 안출한 것으로서, 반도체 칩의 범프 또는 솔더볼 주변에 스트레스 완화용 패시베이션 또는 미러볼 등과 같은 별도의 지지수단을 더 형성해줌으로써, 반도체 칩의 범프 또는 솔더볼을 기판의 본딩영역에 접착시키는 공정 중, 반도체 칩의 외곽쪽에 부착된 범프 또는 솔더볼과 같은 입출력단자를 지지수단에서 받쳐줌에 따라 범프 또는 솔더볼 등의 변형을 용이하게 방지할 수 있도록 한 반도체 장치를 제공하는데 그 목적이 있다.
The present invention has been made to solve the above-mentioned conventional problems, and by forming a separate support means such as a passivation for reducing stress or a mirror ball around the bump or solder ball of the semiconductor chip, the bump or solder ball of the semiconductor chip substrate In the process of adhering to the bonding area of the semiconductor chip, the support means supports the input and output terminals such as bump or solder ball attached to the outer side of the semiconductor chip to provide a semiconductor device that can easily prevent deformation of bump or solder ball, etc. The purpose is.

상기한 목적을 달성하기 위한 본 발명은 전체 면적에 걸쳐 다수의 전극패드가 등간격을 이루며 형성된 반도체 칩과, 상기 전극패드에 부착되는 범프 또는 솔더볼을 포함하는 반도체 장치에 있어서, 상기 반도체 칩의 표면에서, 범프 또는 솔더볼의 외곽을 향하는 주변 위치에 범프 또는 솔더볼을 받쳐줄 수 있는 지지수단을 형성하여, 기판의 본딩영역에 범프 또는 솔더볼이 접착될 때의 스트레스를 지지수단에서 완충시킬 수 있도록 한 것을 특징으로 하는 반도체 장치를 제공한다.The present invention for achieving the above object is a semiconductor device comprising a semiconductor chip formed with a plurality of electrode pads at equal intervals over the entire area, and a bump or solder ball attached to the electrode pad, the surface of the semiconductor chip In, by forming a support means for supporting the bump or solder ball in the peripheral position toward the outside of the bump or solder ball, it is possible to buffer the stress when the bump or solder ball is bonded to the bonding area of the substrate in the support means A semiconductor device is provided.

본 발명의 바람직한 구현예로서, 상기 지지수단은 범프 또는 솔더볼의 하단 및 그 외곽방향 외경면을 받쳐줄 수 있는 스트레스 완화용 패시베이션을 반도체 칩의 최상층 제2패시베이션 막 위에 형성하여서 된 것임을 특징으로 한다.In a preferred embodiment of the present invention, the support means is characterized in that the stress relief passivation that can support the lower surface of the bump or solder ball and the outer surface of the outer surface on the second passivation film of the semiconductor chip.

더욱 바람직한 구현예로서, 상기 스트레스 완화용 패시베이션은 원주 형상으로 형성되되, 반도체 칩의 중심쪽에 위치한 범프 또는 솔더볼을 받쳐주는 스트레스 완화용 패시베이션의 원주길이는 작게 형성되고, 외곽쪽에 위치한 범프 또는 솔더볼을 받쳐주는 스트레스 완화용 패시베이션의 원주길이는 점차 크게 형성되는 것을 특징으로 한다.In a more preferred embodiment, the stress relief passivation is formed in a circumferential shape, the circumferential length of the stress relief passivation supporting the bump or solder ball located in the center of the semiconductor chip is formed small, and the bump or solder ball located in the outer side The circumferential length of the stress relaxation passivation is characterized in that gradually formed.

본 발명의 바람직한 다른 구현예로서, 상기 반도체 칩에 부착된 솔더볼중 가장 외곽에 위치한 솔더볼의 외곽쪽 외경면과 인접한 반도체 칩의 표면에 더미 기능의 미러 볼이 부착된 것을 특징으로 한다.In another preferred embodiment of the present invention, the mirror ball having a dummy function is attached to the surface of the semiconductor chip adjacent to the outer outer surface of the solder ball located at the outermost side of the solder ball attached to the semiconductor chip.

바람직하게는, 상기 미러볼은 솔더볼의 하단 및 그 외곽방향 외경면을 받쳐줄 수 있도록 솔더볼에 비하여 작은 직경으로 형성된 것을 특징으로 한다.Preferably, the mirror ball is characterized in that formed in a smaller diameter than the solder ball so as to support the outer surface of the solder ball and its outer diameter.

본 발명의 바람직한 또 다른 구현예로서, 상기 반도체 칩에 형성된 전극패드중 가장 외곽에 위치한 전극패드를 외곽방향으로 연장하여 크게 형성하고, 면적이 증대된 가장 외곽의 전극패드에 외경이 크고 높이가 낮은 대형 솔더볼이 부착된 것을 특징으로 한다.In another preferred embodiment of the present invention, the outermost electrode pads formed on the semiconductor chip are formed to extend in the outer direction and are formed to be large, and the outer diameter of the outermost electrode pad having an increased area has a large outer diameter and a low height. It is characterized in that the large solder ball is attached.

또한, 상기 반도체 칩에 부착된 범프중 가장 외곽에 위치한 범프의 외곽쪽 외경면에는 스트레스 완화용 연장단이 일체로 더 형성된 것을 특징으로 한다.
In addition, the outer peripheral surface of the bump located at the outermost of the bumps attached to the semiconductor chip is characterized in that the stress relief extension end is further formed integrally.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above problem solving means, the present invention provides the following effects.

본 발명에 따르면, 전체 면적에 걸쳐 범프 또는 솔더볼이 부착된 반도체 칩에 있어서, 각 범프 또는 솔더볼의 외곽쪽 외경면 주변에 스트레스 완화용 패시베이션 또는 미러볼 등과 같은 별도의 지지수단을 더 형성하여, 반도체 칩의 범프 또는 솔더볼을 기판의 본딩영역에 접착시키는 공정 중, 범프 또는 솔더볼과 같은 입출력단자를 지지수단에서 받쳐줌에 따라 범프 또는 솔더볼 등에 작용하는 스트레스를 완충시켜, 범프 또는 솔더볼 등의 변형을 용이하게 방지할 수 있다.According to the present invention, in a semiconductor chip having bumps or solder balls attached over its entire area, a separate support means such as a stress relaxation passivation or a mirror ball is further formed around the outer outer surface of each bump or solder ball, thereby providing a semiconductor chip. Of the bumps or solder balls to support the input and output terminals such as bumps or solder balls in the support means to buffer the stress applied to the bumps or solder balls, thereby easily deforming the bumps or solder balls, etc. It can prevent.

즉, 반도체 칩의 범프 또는 솔더볼을 기판의 본딩영역에 접착시키는 고온의 리플로우 공정 중, 반도체 칩과 기판간의 열팽창계수 차이로 인한 워피지가 발생하더라도 범프 또는 솔더볼과 같은 입출력단자(특히 외곽쪽에 배치된 입출력단자)를 지지수단에서 받쳐주며 워피지 현상에 따른 스트레스를 완충시켜 줌으로써, 범프 또는 솔더볼 등의 변형을 용이하게 방지할 수 있다.
That is, during the high temperature reflow process in which bumps or solder balls of a semiconductor chip are bonded to a bonding region of a substrate, even if warpage occurs due to a difference in thermal expansion coefficient between the semiconductor chip and the substrate, an input / output terminal such as bumps or solder balls (especially disposed outside) The input and output terminals) by the support means to buffer the stress caused by the warpage phenomenon, it is possible to easily prevent deformation of bumps or solder balls.

도 1은 본 발명의 제1실시예에 따른 반도체 장치를 나타내는 평면도 및 단면도,
도 2는 본 발명의 제2실시예에 따른 반도체 장치를 나타내는 평면도 및 단면도,
도 3은 본 발명의 제3실시예에 따른 반도체 장치를 나타내는 평면도 및 단면도,
도 4는 본 발명의 제4실시예에 따른 반도체 장치를 나타내는 평면도 및 단면도,
도 5는 본 발명의 제5실시예에 따른 반도체 장치를 나타내는 평면도 및 단면도,
도 6은 종래의 반도체 장치를 나타내는 단면도,
도 7은 종래의 반도체 장치에서 발생되는 문제점을 설명하는 개략도.1 is a plan view and a sectional view of a semiconductor device according to a first embodiment of the present invention;
2 is a plan view and a sectional view of a semiconductor device according to a second embodiment of the present invention;
3 is a plan view and a sectional view of a semiconductor device according to a third embodiment of the present invention;
4 is a plan view and a sectional view of a semiconductor device according to a fourth embodiment of the present invention;
5 is a plan view and a sectional view of a semiconductor device according to a fifth embodiment of the present invention;
6 is a cross-sectional view showing a conventional semiconductor device;
Fig. 7 is a schematic diagram illustrating a problem occurring in the conventional semiconductor device.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 범프 또는 솔더볼을 갖는 반도체 칩을 적층 대상 칩 또는 기판에 실장할 때, 스트레스로 인하여 범프 또는 솔더볼(특히, 최외곽쪽에 위치한 범프 또는 솔더볼)이 변형되는 것을 용이하게 방지할 수 있도록 한 점에 주안점이 있다.According to the present invention, when a semiconductor chip having bumps or solder balls is mounted on a stacking chip or a substrate, it is easy to prevent the bumps or solder balls (especially the outermost bump or solder balls) from being deformed due to stress. There is a focus on this.

이를 위해, 반도체 칩의 표면에 범프 또는 솔더볼을 받쳐줄 수 있는 별도의 지지수단을 일체로 형성하고, 반도체 칩이 기판에 실장될 때의 스트레스를 지지수단에서 완충시킬 수 있도록 한다.To this end, a separate supporting means for supporting bumps or solder balls is integrally formed on the surface of the semiconductor chip, and the stress when the semiconductor chip is mounted on the substrate can be buffered by the supporting means.

즉, 첨부한 도 1 내지 도 5에 도시된 본 발명의 각 실시예와 같이, 상기 반도체 칩(10)의 표면 영역중, 범프(30) 또는 솔더볼(40)의 외곽을 향하는 주변 위치에 범프(30) 또는 솔더볼(40)의 하단 및 외경면을 받쳐줄 수 있는 지지수단(60)을 형성하여, 기판의 본딩영역에 범프(30) 또는 솔더볼(40)이 접착될 때의 스트레스를 지지수단(60)에서 완충시킬 수 있도록 한다.That is, as in each of the embodiments of the present invention illustrated in FIGS. 1 to 5, bumps (bumps) may be disposed at peripheral portions of the surface area of the semiconductor chip 10 facing the outside of the bumps 30 or the solder balls 40. 30 or the support means 60 to support the lower and outer diameter surface of the solder ball 40, to support the stress when the bump 30 or the solder ball 40 is bonded to the bonding region of the substrate (60) ) Can be buffered.

여기서, 본 발명의 제1실시예에 따른 반도체 장치를 첨부한 도 1을 참조로 설명하면 다음과 같다.A semiconductor device according to a first embodiment of the present invention will now be described with reference to FIG. 1.

본 발명의 제1실시예에 따른 반도체 장치는 반도체 칩(10)의 전체 면적에 걸쳐 형성된 다수의 전극패드(14)에 솔더볼(40)이 부착된 구조로서, 각 솔더볼(40)의 외곽쪽을 향하는 그 하단부 및 외경면을 받쳐주는 지지수단(60)을 스트레스 완충용 패시베이션(62)으로 채택한 점에 특징이 있다.The semiconductor device according to the first embodiment of the present invention has a structure in which solder balls 40 are attached to a plurality of electrode pads 14 formed over the entire area of the semiconductor chip 10, and the outer side of each solder ball 40 is formed. It is characterized in that the support means 60 for supporting the lower end portion and the outer diameter surface facing toward the stress buffer passivation 62.

즉, 본 발명의 제1실시예에 따른 지지수단(60)은 솔더볼(40)의 하단 및 그 외곽방향 외경면을 받쳐줄 수 있는 스트레스 완화용 패시베이션(62)을 반도체 칩(10)의 최상층을 구성하고 있는 제2패시베이션 막(20) 위에 형성하여서 달성된다.That is, the support means 60 according to the first embodiment of the present invention constitutes the uppermost layer of the semiconductor chip 10 with a stress relief passivation 62 that can support the lower end of the solder ball 40 and its outer surface. It is achieved by forming on the second passivation film 20.

보다 상세하게는, 상기 스트레스 완화용 패시베이션(62)은 솔더볼(40)의 하단 및 그 외곽방향 외경면을 받쳐줄 수 있는 원주 형상으로 형성되는 바, 반도체 칩(10)의 중심쪽에 위치한 솔더볼(40)의 외곽방향쪽을 받쳐주는 스트레스 완화용 패시베이션(62)의 원주길이는 보다 작게 형성되고, 반도체 칩의 외곽쪽(테두리 및 모서리 쪽)에 위치한 솔더볼(40)의 외곽방향쪽을 받쳐주는 스트레스 완화용 패시베이션(62)의 원주길이는 점차 크게 형성된다.More specifically, the stress relief passivation 62 is formed in a circumferential shape that can support the lower end of the solder ball 40 and its outer circumferential surface, and the solder ball 40 located at the center of the semiconductor chip 10. The circumferential length of the stress relief passivation 62 supporting the outer side of the stress relief for supporting the outer side of the solder ball 40 located on the outer side (border and corner side) of the semiconductor chip is smaller. The circumferential length of the passivation 62 is gradually increased.

이때, 반도체 칩(10)의 외곽쪽에 부착된 솔더볼(40)을 받쳐주는 스트레스 완화용 패시베이션(62)의 원주길이를 보다 크게 형성한 이유는 반도체 칩(10)을 기판에 실장할 때의 스트레스가 반도체 칩(10)의 외곽쪽에 더 작용하므로 스트레스에 대한 완충력을 좀 더 크게 얻어내도록 한 점에 있다.At this time, the reason that the circumferential length of the stress relaxation passivation 62 supporting the solder ball 40 attached to the outer side of the semiconductor chip 10 is made larger is that stress when mounting the semiconductor chip 10 on a substrate is increased. Since it acts more on the outer side of the semiconductor chip 10 is to obtain a greater buffering capacity for stress.

따라서, 반도체 칩(10)의 솔더볼(40)을 기판의 본딩영역에 접착시키는 고온의 리플로우 공정 중, 반도체 칩과 기판간의 열팽창계수 차이로 인하여 워피지 현상이 발생하더라도, 즉 반도체 칩과 기판간의 워피지 정도(휨량)이 달라지더라도, 솔더볼(40)에 대한 지지수단인 스트레스 완화용 패시베이션(62)이 솔더볼(40)의 외곽쪽 외경면을 받쳐주면서 워피지 현상에 따른 스트레스를 완충시켜 줌으로써, 결국 솔더볼 등의 변형을 용이하게 방지할 수 있다.Therefore, even when warpage occurs due to a difference in thermal expansion coefficient between the semiconductor chip and the substrate during the high temperature reflow process in which the solder balls 40 of the semiconductor chip 10 are bonded to the bonding region of the substrate, that is, between the semiconductor chip and the substrate, Even if the warpage degree (warpage amount) varies, the stress relief passivation 62, which is a support means for the solder ball 40, supports the outer diameter surface of the solder ball 40 while buffering the stress due to the warpage phenomenon. As a result, deformation of solder balls and the like can be easily prevented.

본 발명의 제2실시예에 따른 반도체 장치는 첨부한 도 2에 도시된 바와 같이, 반도체 칩(10)의 전체 면적에 걸쳐 형성된 다수의 전극패드(14)에 범프(30)가 부착된 구조로서, 각 범프(30)의 외곽쪽을 향하는 그 하단부 및 외경면을 받쳐주는 지지수단(60)을 제1실시예와 같이 스트레스 완충용 패시베이션(62)으로 채택한 점에 특징이 있으며, 제2실시예는 솔더볼이 아닌 범프(30)가 반도체 칩(10)에 부착된 점에 차이가 있을 뿐, 지지수단(60)인 스트레스 완충용 패시베이션(62)이 범프(30)의 외곽쪽 하단 및 외경면을 받쳐줄 수 있는 구조로 형성된 점은 제1실시예와 동일하므로, 제2실시예의 지지수단에 대한 구체적인 구성 및 효과 설명은 생략하기로 한다.As shown in FIG. 2, the semiconductor device according to the second embodiment of the present invention has a structure in which bumps 30 are attached to a plurality of electrode pads 14 formed over the entire area of the semiconductor chip 10. It is characterized in that the support means 60 for supporting the lower end portion and the outer diameter face toward the outer side of each bump 30 as a stress buffer passivation 62 as in the first embodiment, the second embodiment There is a difference in that the bump 30, not the solder ball is attached to the semiconductor chip 10, the stress buffer passivation 62, the support means 60 is the outer bottom and outer diameter surface of the bump 30 Since the point formed in the supporting structure is the same as in the first embodiment, a detailed description of the configuration and effect of the supporting means of the second embodiment will be omitted.

여기서, 본 발명의 제3실시예에 따른 반도체 장치를 첨부한 도 3을 참조로 설명하면 다음과 같다.A semiconductor device according to a third embodiment of the present invention will now be described with reference to FIG. 3.

본 발명의 제3실시예는 반도체 칩(10)에 부착된 다수의 솔더볼(40)중 가장 외곽에 위치한 솔더볼(40)의 외곽쪽 외경면과 인접한 위치에 더미 기능의 미러 볼(64)이 부착된 점에 특징이 있다.According to the third embodiment of the present invention, the mirror ball 64 having a dummy function is attached to a position adjacent to the outer outer diameter surface of the solder ball 40 located at the outermost side of the plurality of solder balls 40 attached to the semiconductor chip 10. There is a characteristic to the point.

반도체 칩(10)의 솔더볼(40)을 기판의 본딩영역에 접착시키는 고온의 리플로우 공정 중, 반도체 칩과 기판간의 열팽창계수 차이로 인하여 워피지 현상이 발생될 때, 그 스트레스가 반도체 칩(10)의 외곽쪽에 집중됨에 따라, 본 발명의 제3실시예에서는 반도체 칩(10)의 외곽에 위치한 솔더볼(40)을 받쳐주며 지지할 수 있는 지지수단(60)으로서 미러 볼(64)이 채택된 것이다.During the high temperature reflow process of adhering the solder ball 40 of the semiconductor chip 10 to the bonding region of the substrate, when the warpage phenomenon occurs due to the difference in thermal expansion coefficient between the semiconductor chip and the substrate, the stress is caused to occur. In the third embodiment of the present invention, the mirror ball 64 is adopted as the support means 60 that can support and support the solder ball 40 located on the outside of the semiconductor chip 10. will be.

바람직하게는, 상기 반도체 칩(10)의 최외곽에 부착된 미러 볼(64)을 인접한 솔더볼(40)에 비하여 작은 직경으로 형성하여, 솔더볼(40)의 하단 및 그 외곽방향 외경면을 받쳐줄 수 있도록 한다.Preferably, the mirror ball 64 attached to the outermost part of the semiconductor chip 10 may be formed to have a smaller diameter than the adjacent solder ball 40 to support the lower end of the solder ball 40 and its outer surface. Make sure

따라서, 반도체 칩(10)의 솔더볼(40)을 기판의 본딩영역에 접착시키는 고온의 리플로우 공정 중, 반도체 칩과 기판간의 열팽창계수 차이로 인하여 워피지 현상이 발생하더라도, 즉 반도체 칩과 기판간의 워피지 정도(휨량)이 달라지더라도, 솔더볼(40)에 대한 지지수단인 더미 기능의 미러 볼(64)이 솔더볼(40)의 외곽쪽 하단 및 외경면을 받쳐주면서 워피지 현상에 따른 스트레스를 완충시켜 줌으로써, 결국 솔더볼 등의 변형을 용이하게 방지할 수 있다.Therefore, even when warpage occurs due to a difference in thermal expansion coefficient between the semiconductor chip and the substrate during the high temperature reflow process in which the solder balls 40 of the semiconductor chip 10 are bonded to the bonding region of the substrate, that is, between the semiconductor chip and the substrate, Even if the warpage degree (warpage amount) varies, the mirror ball 64 of the dummy function, which is a support means for the solder ball 40, supports the outer lower surface and the outer diameter surface of the solder ball 40, thereby reducing the stress caused by the warpage phenomenon. By buffering, deformation of a solder ball etc. can be easily prevented eventually.

여기서, 본 발명의 제4실시예에 따른 반도체 장치를 첨부한 도 4를 참조로 설명하면 다음과 같다.A semiconductor device according to a fourth embodiment of the present invention will now be described with reference to FIG. 4.

본 발명의 제4실시예는 반도체 칩(10)에 형성된 전극패드들중 가장 외곽에 위치한 전극패드(14)를 외곽방향으로 연장하여 솔더볼 또는 범프가 융착될 수 있는 면적을 더 크게 형성하고, 면적이 증대된 가장 외곽의 전극패드(14)에 외경이 크고 높이가 낮은 대형 솔더볼(66)을 부착하거나, 직경이 증대된 범프(30)가 형성되도록 한 점에 특징이 있다.The fourth embodiment of the present invention extends the outermost electrode pad 14 among the electrode pads formed in the semiconductor chip 10 in the outer direction to form a larger area in which solder balls or bumps can be fused, and the area thereof. A large solder ball 66 having a large outer diameter and a low height is attached to the increased outermost electrode pad 14, or a bump 30 having an increased diameter is formed.

따라서, 반도체 칩(10)의 솔더볼(40)을 기판의 본딩영역에 접착시키는 고온의 리플로우 공정 중, 반도체 칩과 기판간의 열팽창계수 차이로 인하여 워피지 현상이 발생하더라도, 다시 말해서 반도체 칩과 기판간의 열팽창계수 차이로 인하여 워피지 현상이 발생될 때의 스트레스가 반도체 칩(10)의 외곽쪽에 집중되더라도, 반도체 칩(10) 및 기판(50)을 연결하는 대형 솔더볼(40) 또는 범프(30)의 융착 면적이 증대된 상태이므로 대형 솔더볼(40) 또는 범프(30)에서 스트레스를 분산시키는 역할을 하게 되어, 결국 대형 솔더볼(40) 및 범프(30)의 형상이 변형없이 유지될 수 있다.Therefore, even when warpage occurs due to a difference in thermal expansion coefficient between the semiconductor chip and the substrate during the high temperature reflow process in which the solder ball 40 of the semiconductor chip 10 is bonded to the bonding region of the substrate, that is, the semiconductor chip and the substrate The large solder ball 40 or bump 30 connecting the semiconductor chip 10 and the substrate 50 may be concentrated even when the stress when warpage occurs due to a difference in thermal expansion coefficient between the semiconductor chips 10 and the semiconductor chip 10. Since the fusion area of the increased state to serve to distribute the stress in the large solder ball 40 or bump 30, the shape of the large solder ball 40 and bump 30 can be maintained without deformation.

여기서, 본 발명의 제5실시예에 따른 반도체 장치를 첨부한 도 5를 참조로 설명하면 다음과 같다.A semiconductor device according to a fifth embodiment of the present invention will now be described with reference to FIG. 5.

본 발명의 제5실시예는 상기 반도체 칩(10)의 각 전극패드(14)에 범프(30)가 부착된 경우, 각 범프들중 가장 외곽에 위치한 범프(30)의 단면적을 외곽쪽을 증대시킨 점에 특징이 있다.According to the fifth embodiment of the present invention, when the bumps 30 are attached to the electrode pads 14 of the semiconductor chip 10, the cross-sectional area of the bumps 30 located at the outermost of the bumps is increased to the outer side. It is characteristic in point.

즉, 반도체 칩(10)에 부착되는 범프들중 가장 외곽쪽에 부착된 범프(30)의 외곽쪽을 향하는 외경면에 범프(30)의 도금 공정시 스트레스 완화용 연장단(68)을 일체로 더 형성함으로써, 이 스트레스 완화용 연장단(68) 부분에서 스트레스를 완충시키는 역할을 하게 된다.That is, an extension end 68 for stress relaxation during the plating process of the bumps 30 is further integrally formed on the outer diameter surface of the bumps 30 attached to the outermost side of the bumps attached to the semiconductor chip 10. By forming, it serves to buffer the stress in the stress relief extension end 68 portion.

따라서, 반도체 칩(10)의 범프(30)을 기판의 본딩영역에 접착시키는 고온의 리플로우 공정 중, 반도체 칩과 기판간의 열팽창계수 차이로 인하여 워피지 현상이 발생될 때의 스트레스가 반도체 칩(10)의 외곽쪽에 집중되더라도, 반도체 칩(10) 및 기판(50)을 연결하는 범프(30)의 스트레스 완화용 연장단(68)에서 스트레스를 분산시키는 역할을 하게 되어, 결국 범프(30)의 형상이 변형없이 유지될 수 있다.Therefore, during the high temperature reflow process in which the bump 30 of the semiconductor chip 10 is bonded to the bonding region of the substrate, the stress when the warpage phenomenon occurs due to the difference in thermal expansion coefficient between the semiconductor chip and the substrate is caused to occur. Even if concentrated on the outer side of the 10, it serves to distribute the stress in the stress relief extension end 68 of the bump 30 that connects the semiconductor chip 10 and the substrate 50, the end of the bump 30 The shape can be maintained without deformation.

이상과 같이, 반도체 칩의 범프 또는 솔더볼을 기판의 본딩영역에 접착시키는 공정 중, 범프 또는 솔더볼과 같은 입출력단자가 받는 스트레스를 상기한 각 실시예의 지지수단에서 분산 또는 완충시켜줌에 따라, 반도체 칩에 부착된 각 범프 또는 솔더볼 등의 변형 현상을 용이하게 방지할 수 있다.
As described above, during the process of bonding the bump or the solder ball of the semiconductor chip to the bonding region of the substrate, the stress applied to the input / output terminals such as the bump or the solder ball is dispersed or buffered by the supporting means of each of the above-described embodiments. Deformation phenomenon of each bump or solder ball attached can be easily prevented.

10 : 반도체 칩 12 : 본딩패드
14 : 전극패드 18 : 제1패시베이션 막
20 : 제2패시베이션 막 30 : 범프
32 : 구리필러 34 : 전도성 솔더
40 : 솔더볼 50 : 기판
60 : 지지수단 62 : 스트레스 완화용 패시베이션
64 : 미러 볼 66 : 대형 솔더볼
68 : 스트레스 완화용 연장단10 semiconductor chip 12 bonding pad
14 electrode pad 18 first passivation film
20: second passivation film 30: bump
32: copper filler 34: conductive solder
40: solder ball 50: substrate
60: support means 62: passivation for stress relief
64: mirror ball 66: large solder ball
68: extension of stress relief

Claims (7)

전체 면적에 걸쳐 다수의 전극패드(14)가 등간격을 이루며 형성된 반도체 칩(10)과, 전극패드(14)에 부착되는 범프(30) 또는 솔더볼(40)을 포함하는 반도체 장치에 있어서,
상기 반도체 칩(10)의 표면에서, 범프(30) 또는 솔더볼(40)의 외곽을 향하는 주변 위치에 범프(30) 또는 솔더볼(40)을 받쳐줄 수 있는 지지수단(60)을 형성하여, 기판의 본딩영역에 범프(30) 또는 솔더볼(40)이 접착될 때의 스트레스를 지지수단(60)에서 완충시킬 수 있도록 한 것을 특징으로 하는 반도체 장치.
In the semiconductor device comprising a semiconductor chip 10 formed with a plurality of electrode pads 14 at equal intervals over the entire area, and the bump 30 or solder ball 40 attached to the electrode pad 14,
On the surface of the semiconductor chip 10, the support means 60 for supporting the bump 30 or the solder ball 40 in the peripheral position toward the outside of the bump 30 or the solder ball 40 is formed to form a substrate A semiconductor device characterized in that the support means (60) can buffer the stress when the bump (30) or the solder ball (40) is bonded to the bonding area.
청구항 1에 있어서,
상기 지지수단(60)은 범프(30) 또는 솔더볼(40)의 하단 및 그 외곽방향 외경면을 받쳐줄 수 있는 스트레스 완화용 패시베이션(62)을 반도체 칩(10)의 최상층 제2패시베이션 막(20) 위에 형성하여서 된 것임을 특징으로 하는 반도체 장치.
The method according to claim 1,
The support means 60 may include a stress relaxation passivation 62 that may support the lower end of the bump 30 or the solder ball 40 and its outer surface in the outer direction thereof, and the second passivation layer 20 of the uppermost layer of the semiconductor chip 10. The semiconductor device formed by forming on it.
청구항 1 또는 청구항 2에 있어서,
상기 스트레스 완화용 패시베이션(62)은 원주 형상으로 형성되되, 반도체 칩(10)의 중심쪽에 위치한 범프(30) 또는 솔더볼(40)을 받쳐주는 스트레스 완화용 패시베이션(62)의 원주길이는 작게 형성되고, 외곽쪽에 위치한 범프(30) 또는 솔더볼(40)을 받쳐주는 스트레스 완화용 패시베이션(62)의 원주길이는 점차 크게 형성되는 것을 특징으로 하는 반도체 장치.
The method according to claim 1 or 2,
The stress relief passivation 62 is formed in a circumferential shape, and the circumferential length of the stress relief passivation 62 supporting the bump 30 or the solder ball 40 positioned at the center of the semiconductor chip 10 is formed small. , The semiconductor device, characterized in that the circumferential length of the stress relief passivation 62 supporting the bump 30 or the solder ball 40 located on the outer side thereof is gradually formed.
청구항 1에 있어서,
상기 반도체 칩(10)에 부착된 솔더볼(40)중 가장 외곽에 위치한 솔더볼(40)의 외곽쪽 외경면과 인접한 반도체 칩(10)의 표면에 더미 기능의 미러 볼(64)이 부착된 것을 특징으로 하는 반도체 장치.
The method according to claim 1,
The dummy ball mirror ball 64 is attached to the surface of the semiconductor chip 10 adjacent to the outer outer surface of the solder ball 40 positioned at the outermost side of the solder ball 40 attached to the semiconductor chip 10. A semiconductor device.
청구항 4에 있어서,
상기 미러 볼(64)은 솔더볼(40)의 하단 및 그 외곽방향 외경면을 받쳐줄 수 있도록 솔더볼(40)에 비하여 작은 직경으로 형성된 것을 특징으로 하는 반도체 장치.
The method of claim 4,
The mirror ball 64 is a semiconductor device, characterized in that formed in a smaller diameter than the solder ball 40 so as to support the lower surface of the solder ball (40) and the outer surface of the outer direction.
청구항 1에 있어서,
상기 반도체 칩(10)에 형성된 전극패드중 가장 외곽에 위치한 전극패드(14)를 외곽방향으로 연장하여 더 크게 형성하고, 면적이 증대된 가장 외곽의 전극패드(14)에 외경이 크고 높이가 낮은 대형 솔더볼(66)이 부착되거나, 직경이 큰 범프(30)가 부착된 것을 특징으로 하는 반도체 장치.
The method according to claim 1,
Among the electrode pads formed on the semiconductor chip 10, the outermost electrode pads 14 are formed to extend in the outer direction and are formed larger, and the outer diameters of the outermost electrode pads 14 having an increased area have a larger outer diameter and a lower height. A large solder ball (66) is attached, or a semiconductor device characterized in that the large bump (30) is attached.
청구항 1에 있어서,
상기 반도체 칩(10)에 부착된 범프(30)중 가장 외곽에 위치한 범프(30)의 외곽쪽 외경면에는 스트레스 완화용 연장단(68)이 일체로 더 형성된 것을 특징으로 하는 반도체 장치.The method according to claim 1,
The semiconductor device, characterized in that the outer end surface of the bump (30) located on the outermost of the bumps (30) attached to the semiconductor chip (10) is further formed with an extension end (68) for stress relief.
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WO2014011612A3 (en) * 2012-07-09 2014-04-10 Qualcomm Incorporated Non-circular under bump metallization (ubm) structure, orientation of non-circular ubm structure and trace orientation to inhibit peeling and/or cracking

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KR102171197B1 (en) 2014-02-20 2020-10-28 삼성전자주식회사 Method of Fabricating Bump Pad Structures Having Buffer Patterns

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014011612A3 (en) * 2012-07-09 2014-04-10 Qualcomm Incorporated Non-circular under bump metallization (ubm) structure, orientation of non-circular ubm structure and trace orientation to inhibit peeling and/or cracking
US8847391B2 (en) 2012-07-09 2014-09-30 Qualcomm Incorporated Non-circular under bump metallization (UBM) structure, orientation of non-circular UBM structure and trace orientation to inhibit peeling and/or cracking

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