KR20120048840A - Semiconductor package - Google Patents

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KR20120048840A
KR20120048840A KR1020100110238A KR20100110238A KR20120048840A KR 20120048840 A KR20120048840 A KR 20120048840A KR 1020100110238 A KR1020100110238 A KR 1020100110238A KR 20100110238 A KR20100110238 A KR 20100110238A KR 20120048840 A KR20120048840 A KR 20120048840A
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South Korea
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substrate
semiconductor chip
magnet
adhesive
present
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KR1020100110238A
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Korean (ko)
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배진호
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에스케이하이닉스 주식회사
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Priority to KR1020100110238A priority Critical patent/KR20120048840A/en
Publication of KR20120048840A publication Critical patent/KR20120048840A/en

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Abstract

PURPOSE: A semiconductor package is provided to improve manufacturing yield since faults generated due to the bending of a semiconductor chip is controlled by preventing the semiconductor chip from being bent. CONSTITUTION: A substrate(200) has an upper side and a lower side facing the upper side. A magnet(203) is arranged on the upper side of the substrate. A semiconductor chip(208) has one side facing the upper side of the substrate and the other side facing the one side. An adhesive(206) is interposed between the upper side of the substrate and the one side of the semiconductor chip. The adhesive includes an adhesive material(204) and a ferromagnetic material(205). A connecting member(W) electrically connects the substrate and the semiconductor chip.

Description

반도체 패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게, 반도체 칩의 휨 현상을 방지하여 패키지의 특성 및 제조 수율을 향상시킬 수 있는 반도체 패키지에 관한 것이다, The present invention relates to a semiconductor package, and more particularly, to a semiconductor package that can prevent the warpage of the semiconductor chip to improve the characteristics and manufacturing yield of the package,

하나의 패키지의 밀도를 증가시키기 위해서는 반도체칩의 밀도를 증가시키거나 반도체칩의 갯수를 증가시키는 방법이 있는데, 상기 반도체칩의 밀도를 증가시키는 것은 기술적으로 어렵기 때문에, 상기 반도체칩의 갯수를 증가시키는 방법이 일반적으로 사용되고 있다. In order to increase the density of one package, there is a method of increasing the density of the semiconductor chip or increasing the number of semiconductor chips. Since it is technically difficult to increase the density of the semiconductor chip, the number of the semiconductor chips is increased. The method of making is generally used.

그러나, 상기 반도체칩의 갯수를 증가시키는 방법도 패키지의 크기가 정해져 있고 한도 없이 크기를 키우기에도 한계가 있다. However, the method of increasing the number of the semiconductor chips is also limited in size of the package is limited, without increasing the size.

이를 해결하기 위해서, 반도체칩의 두께를 얇게 하여 스택하고 있으나, 반도체칩의 두께가 얇아질수록 반도체칩의 활성층과 그 하단의 실리콘(Si)부 사이의 차이로 인하여 반도체칩이 휘어지거나 들뜨는 현상이 발생하여 후속 공정에서 불량을 야기시키는 문제점이 발생되고 있다. In order to solve this problem, the semiconductor chip is made thin and stacked. However, as the thickness of the semiconductor chip becomes thinner, the semiconductor chip is bent or lifted due to the difference between the active layer of the semiconductor chip and the silicon (Si) portion at the bottom thereof. There is a problem that occurs, causing a failure in the subsequent process.

도 1에서와 같이, 반도체칩(108)을 기판(100)에 부착한 후에도 상기 반도체칩(108)이 휘어지거나 들뜨는 '휨(Warpage) 또는 들뜸 현상'으로 인하여 후속 공정인 상기 기판과 상기 반도체칩을 전기적으로 연결시키는 전도성 와이어 공정에서 칩 바운싱(Bouncing)으로 인한 불량으로 인하여 상기 반도체칩과 기판 간의 접착력 약화로 신뢰성 불량이 발생될 수 있다. 또한, 상기 반도체칩에 크랙(Crack)이 발생 될 수도 있다.As shown in FIG. 1, even after the semiconductor chip 108 is attached to the substrate 100, the substrate and the semiconductor chip are a subsequent process due to the warpage or lifting phenomenon in which the semiconductor chip 108 is bent or lifted. In the conductive wire process for electrically connecting the wires, the reliability due to the weakening of the adhesive force between the semiconductor chip and the substrate may occur due to a defect due to chip bouncing. In addition, cracks may occur in the semiconductor chip.

본 발명은 반도체칩의 휨 현상을 방지할 수 있는 반도체 패키지를 제공한다. The present invention provides a semiconductor package capable of preventing warpage of the semiconductor chip.

또한, 본 발명은 반도체칩의 휨 현상을 방지함으로써, 상기 반도체칩의 휨 현상으로 인해 발생하는 불량을 억제할 수 있는 반도체 패키지를 제공한다.In addition, the present invention provides a semiconductor package that can suppress the defect caused by the warpage of the semiconductor chip by preventing the warpage of the semiconductor chip.

게다가, 본 발명은 패키지의 특성 및 제조 수율을 향상시킬 수 있는 반도체 패키지를 제공한다.In addition, the present invention provides a semiconductor package capable of improving the characteristics and manufacturing yield of the package.

본 발명의 실시예에 따른 반도체 패키지는, 상면 및 상기 상면에 대향하는 하면을 가지며 자석을 구비한 기판; 상기 기판의 상면 상에 배치되며, 상기 기판의 상면과 마주하는 일면 및 상기 일면에 대향하는 타면을 갖는 반도체칩; 및 상기 기판의 상면 및 상기 반도체칩의 일면 사이에 개재된 강자성체를 갖는 접착제;를 포함한다. A semiconductor package according to an embodiment of the present invention includes a substrate having a top surface and a bottom surface opposite to the top surface, the substrate including a magnet; A semiconductor chip disposed on an upper surface of the substrate and having one surface facing the upper surface of the substrate and the other surface opposite to the one surface; And an adhesive having a ferromagnetic body interposed between an upper surface of the substrate and one surface of the semiconductor chip.

상기 자석은 상기 기판의 상면에 배치된 것을 특징으로 한다. The magnet is characterized in that disposed on the upper surface of the substrate.

상기 자석은 상기 강자성체보다 큰 크기를 갖는 것을 특징으로 한다. The magnet is characterized in that it has a larger size than the ferromagnetic material.

상기 강자성체는 상기 자석과 대응하는 부분에 삽입된 것을 특징으로 한다. The ferromagnetic material is characterized in that inserted in the portion corresponding to the magnet.

상기 강자성체는 다수의 전도성 필러로 구성된 것을 특징으로 한다. The ferromagnetic material is characterized by consisting of a plurality of conductive fillers.

상기 자석 및 상기 강자성체는 각각 상기 반도체칩의 적어도 마주하는 양측 가장자리에 대응하는 부분들에 배치되는 것을 특징으로 한다. The magnet and the ferromagnetic body are each disposed at portions corresponding to at least opposite edges of the semiconductor chip.

상기 자석 및 상기 강자성체는 각각 상기 반도체칩의 각 모서리 부분에 대응하는 부분들에 배치되는 것을 특징으로 한다. The magnet and the ferromagnetic body are each disposed in portions corresponding to each corner portion of the semiconductor chip.

상기 기판과 상기 반도체칩들 간을 전기적으로 연결하는 연결부재를 더 포함한다. It further comprises a connection member for electrically connecting the substrate and the semiconductor chips.

본 발명은 기판 상에 반도체칩의 부착시 접착제를 이용하여 부착하는데, 이때, 상기 접착제 내에 상기 반도체칩의 가장자리 부분에 대응하는 위치에 강자성체를 형성한다. 그리고, 상기 기판 내에는 상기 강자성체와 대응하는 위치에 자석을 삽입한다. The present invention is attached to the substrate using an adhesive when attaching the semiconductor chip, wherein the ferromagnetic material is formed in a position corresponding to the edge portion of the semiconductor chip in the adhesive. A magnet is inserted into the substrate at a position corresponding to the ferromagnetic material.

이렇게 함으로써, 본 발명은 기판 상에 반도체칩의 부착시, 상기 자석과 강자성체를 통하여 상기 기판과 반도체칩들 사이의 접착력을 증가시킬 수 있다. By doing so, the present invention can increase the adhesive force between the substrate and the semiconductor chip through the magnet and the ferromagnetic material when the semiconductor chip is attached to the substrate.

또한, 본 발명은 상기 기판과의 접착력 약화로 상기 반도체칩이 휘어지는 휨 현상으로 인해 발생하는 불량을 억제할 수 있다. In addition, the present invention can suppress the defects caused by the bending phenomenon in which the semiconductor chip is bent by weakening the adhesion to the substrate.

따라서, 본 발명은 패키지 수율 및 작업성을 향상시킬 수 있다. Therefore, the present invention can improve package yield and workability.

도 1은 종래 기술의 문제점을 설명하기 위해 도시한 단면도이다.
도 2a는 본 발명의 실시예에 따른 접착제를 설명하기 위해 도시한 평면도이다.
도 2b는 본 발명의 실시예에 따른 접착제를 반도체칩에 부착한 단면도이다.
도 3a는 본 발명의 실시예에 따른 기판을 설명하기 위해 도시한 평면도이다.
도 3b는 본 발명의 실시예에 따른 기판을 설명하기 위해 도시한 단면도이다.
도 4a는 본 발명의 실시예에 따른 접착제를 이용하여 기판 상에 반도체칩을 부착하려는 도면이다.
도 4b는 본 발명의 실시예에 따른 접착제를 이용하여 기판 상에 반도체칩을 부착한 평면도이다.
도 5는 본 발명의 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도이다. 1 is a cross-sectional view illustrating a problem of the prior art.
2A is a plan view illustrating the adhesive agent according to the embodiment of the present invention.
2B is a cross-sectional view of attaching an adhesive to a semiconductor chip according to an embodiment of the present invention.
3A is a plan view illustrating a substrate according to an embodiment of the present invention.
3B is a cross-sectional view illustrating a substrate according to an embodiment of the present invention.
4A is a view for attaching a semiconductor chip on a substrate using an adhesive according to an embodiment of the present invention.
4B is a plan view of attaching a semiconductor chip on a substrate using an adhesive according to an embodiment of the present invention.
5 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a는 본 발명의 실시예에 따른 접착제를 설명하기 위해 도시한 평면도이고, 도 2b는 본 발명의 실시예에 따른 접착제를 반도체칩에 부착한 단면도이다. 2A is a plan view illustrating the adhesive agent according to the embodiment of the present invention, and FIG. 2B is a cross-sectional view of the adhesive agent attached to the semiconductor chip according to the embodiment of the present invention.

도 2a를 참조하면, 본 발명의 실시예에 따른 접착제(206)는 접착물질(204)을 포함하며, 상기 접착물질(204) 내에 강자성체(205)가 삽입된 것을 특징으로 한다. 2A, the adhesive 206 according to the embodiment of the present invention includes an adhesive material 204, and a ferromagnetic material 205 is inserted into the adhesive material 204.

이때, 상기 강자성체(205)는, 예를 들어, 상기 접착물질(204) 내부에 전체적으로 삽입될 수 있지만, 본 발명에서는, 상기 강자성체(205)가 상기 접착물질(204)의 각 모서리 부분에 대응하는 가장자리 부분들에 배치되는 것이 바람직하다. 여기서, 상기 강자성체(205)는 다수의 전도성 필러로 구성될 수도 있다. At this time, the ferromagnetic material 205, for example, may be inserted entirely inside the adhesive material 204, in the present invention, the ferromagnetic material 205 corresponding to each corner portion of the adhesive material 204 It is preferably arranged at the edge portions. Here, the ferromagnetic material 205 may be composed of a plurality of conductive fillers.

한편, 상기 강자성체(205)는 자석에 달라붙는 성질을 갖는 물질을 말하며, 예를 들어, 철, 코발트, 니켈 및 그들의 합금이 대표적으로 들 수 있다. 상기 강자성체(205)는 개개의 원자가 자석과 같은 역할을 하는데 이들 원자들은 외부의 자기장이 걸려 있지 않은 상황에서는 불규칙하게 정렬해 있기 때문에, 전체적으로 자석과 같은 효과는 없다. 그러나, 외부에서 자석을 갖다 대면, 그 원자들이 외부 자기장의 방향으로 배열하려 하기 때문에 자석에 달라붙게 되는 성질이 있다. 이렇게 외부 자기장의 영향으로 원자들이 일정한 방향으로 배열하는 것을 '자화'라고 하며, 자화된 물질은 그 자신이 자석처럼 다른 강자성체를 잡아당길 수 있다. On the other hand, the ferromagnetic material 205 refers to a material having a property of sticking to the magnet, for example, iron, cobalt, nickel and alloys thereof may be representative. The ferromagnetic material 205 acts like an individual valence magnet, and since these atoms are irregularly aligned in a situation where an external magnetic field is not applied, the ferromagnetic material 205 does not have a magnet-like effect as a whole. However, when the magnet is brought from the outside, the atoms tend to stick to the magnet because they try to align in the direction of the external magnetic field. The arrangement of atoms in a certain direction under the influence of an external magnetic field is called 'magnetization', and the magnetized material itself can pull other ferromagnetic bodies like magnets.

본 발명에서는 전술한 특성을 가지는 상기 접착제(206)를 도 2b에서와 같이, 반도체칩(208)에 부착한다. In the present invention, the adhesive 206 having the above-described characteristics is attached to the semiconductor chip 208 as shown in FIG. 2B.

도 3a는 본 발명의 실시예에 따른 기판을 설명하기 위해 도시한 평면도이고, 도 3b는 본 발명의 실시예에 따른 기판을 설명하기 위해 도시한 단면도이다.3A is a plan view illustrating a substrate according to an embodiment of the present invention, and FIG. 3B is a cross-sectional view illustrating the substrate according to an embodiment of the present invention.

도 3a 및 도 3b를 참조하면, 본 발명의 실시예에 따른 기판(200)은 상면 및 상기 상면에 대향하는 하면을 가지며, 상기 상면에는 본드핑거(202)가 배치되어 있다. 상기 상면에는 자석(203)이 형성되어 있으며, 이와 다르게, 상기 자석(203)은 상기 기판(200)의 내부에 형성될 수도 있다. 3A and 3B, the substrate 200 according to the embodiment of the present invention has a top surface and a bottom surface opposite to the top surface, and a bond finger 202 is disposed on the top surface. The magnet 203 is formed on the upper surface. Alternatively, the magnet 203 may be formed inside the substrate 200.

상기 자석(203)은, 평면 및 단면상으로 보았을 때, 예를 들어, 상기 본드핑거(202)보다 안쪽에 배치되도록 구현된다. 그리고, 상기 자석(203)은 상기 기판(200)의 각 모서리 부분에 대응하는 가장자리 부분들에 배치되는 것이 바람직하다. The magnet 203 is embodied to be disposed inward of the bond finger 202 when viewed in plan and cross-section, for example. In addition, the magnet 203 may be disposed at edge portions corresponding to each corner portion of the substrate 200.

도 4a 및 도 4b는 본 발명의 실시예에 따른 접착제를 이용하여 기판 상에 반도체칩을 부착하려는 도면이다. 4A and 4B are diagrams for attaching a semiconductor chip onto a substrate using an adhesive according to an embodiment of the present invention.

도 4a 및 도 4b를 참조하면, 도 2a, 도 2b, 도 3a 및 도 3b에서 전술한 바와 같이, 본 발명에 따른 접착제(206)를 이용하여 기판(200) 상에 반도체칩(208)을 부착한다. 즉, 상기 기판(200)의 자석(203)과 대응하는 부분에 상기 접착제(206)의 강자성체(205)가 부착되도록 상기 반도체칩(208)을 부착한다.4A and 4B, as described above with reference to FIGS. 2A, 2B, 3A, and 3B, the semiconductor chip 208 is attached onto the substrate 200 using the adhesive 206 according to the present invention. do. That is, the semiconductor chip 208 is attached to the ferromagnetic material 205 of the adhesive 206 to a portion corresponding to the magnet 203 of the substrate 200.

한편, 이하에서는, 전술한 본 발명에 따른 기판(200), 접착제(206) 및 반도체칩(208)을 포함하는 반도체 패키지에 대하여 설명하도록 한다. Meanwhile, hereinafter, a semiconductor package including the substrate 200, the adhesive 206, and the semiconductor chip 208 according to the present invention will be described.

도 5는 본 발명의 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도이다. 5 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

도시된 바와 같이, 본 발명의 일 실시예에 따른 반도체 패키지(210)는, 기판(200), 반도체칩(208), 접착제(206) 및 연결부재(W)를 포함한다. As shown, the semiconductor package 210 according to an embodiment of the present invention includes a substrate 200, a semiconductor chip 208, an adhesive 206 and a connection member (W).

구체적으로, 상기 기판(200)은 상면 및 상기 상면에 대향하는 하면을 가지며, 상기 상면 상에 본드핑거(202) 및 자석(203)을 구비한다. In detail, the substrate 200 has an upper surface and a lower surface facing the upper surface, and includes a bond finger 202 and a magnet 203 on the upper surface.

상기 본드핑거(202)는 상기 자석(203)보다 바깥쪽에, 예를 들어, 상기 기판(200) 상면의 가장자리(모서리) 부분에 대응하는 부분에 위치한다. The bond finger 202 is located outside the magnet 203, for example, at a portion corresponding to an edge (edge) of the upper surface of the substrate 200.

상기 자석(203)은 상기 접착제(206)의 상기 강자성체(205)보다 큰 크기를 가지며, 상기 자석(203)은 상기 기판(200)의 상면 또는 상기 기판(200)의 내부에 형성될 수도 있다. 본 발명의 실시예에서는, 상기 기판(200)의 상면에 상기 자석(203)을 배치하였다.The magnet 203 may have a larger size than the ferromagnetic material 205 of the adhesive 206, and the magnet 203 may be formed on an upper surface of the substrate 200 or inside the substrate 200. In the embodiment of the present invention, the magnet 203 is disposed on the upper surface of the substrate 200.

한편, 상기 자석(203)은 상기 반도체칩(208)의 적어도 마주하는 양측 가장자리에 대응하는 부분들에 배치되거나, 또는, 각각 상기 반도체칩(208)의 각 모서리 부분에 대응하는 부분들에 배치되는 것이 바람직하다. On the other hand, the magnet 203 is disposed in portions corresponding to at least opposite edges of the semiconductor chip 208, or are respectively disposed in portions corresponding to each corner portion of the semiconductor chip 208. It is preferable.

상기 반도체칩(208)은 기판(200)의 상면 상에 배치되며, 일면 및 상기 일면에 대향하는 타면을 갖는다. 상기 반도체칩(208)의 상기 일면은 상기 기판(200)의 상면과 서로 마주하며, 상기 반도체칩(208)의 상기 타면 상에는 본딩패드(209)가 형성되어 있다. The semiconductor chip 208 is disposed on an upper surface of the substrate 200 and has one surface and the other surface opposite to the one surface. One surface of the semiconductor chip 208 faces the top surface of the substrate 200, and a bonding pad 209 is formed on the other surface of the semiconductor chip 208.

상기 접착제(206)는 상기 기판(20)의 상면 및 상기 반도체칩(208)의 일면 사이에 개재된다. 이때, 상기 접착제(206)는 접착물질(204) 및 상기 접착물질(204) 내에 상기 기판(200)의 자석(203)과 대응하는 부분에 삽입된 강자성체(205)로 이루어진다. The adhesive 206 is interposed between an upper surface of the substrate 20 and one surface of the semiconductor chip 208. In this case, the adhesive 206 is formed of an adhesive material 204 and a ferromagnetic material 205 inserted into a portion of the adhesive material 204 corresponding to the magnet 203 of the substrate 200.

여기서, 상기 강자성체(205)는 상기 반도체칩(208)의 가장자리가 상기 기판(200)의 상면에 물리적으로 접착되도록 하는 역할을 하며, 예를 들어, 상기 강자성체(205)는 자석에 달라붙는 성질을 갖는 물질을 말하며, 철, 코발트, 니켈 및 그들의 합금이 대표적으로 들 수 있다. Here, the ferromagnetic material 205 serves to physically bond the edge of the semiconductor chip 208 to the upper surface of the substrate 200, for example, the ferromagnetic material 205 is attached to a magnet It refers to a material having, and iron, cobalt, nickel and alloys thereof are representative.

한편, 상기 강자성체(205)는, 예를 들어, 상기 접착물질(204) 내부에 전체적으로 삽입될 수 있지만, 본 발명에서는, 상기 강자성체(205)가 상기 접착물질(204)의 각 모서리 부분에 대응하는 가장자리 부분, 예를 들어, 상기 자석(203)과 대응하는 부분에 삽입되는 것이 바람직하다. 상기 강자성체(205)는 다수의 전도성 필러로 구성될 수도 있다. On the other hand, the ferromagnetic material 205, for example, may be inserted entirely inside the adhesive material 204, in the present invention, the ferromagnetic material 205 corresponding to each corner portion of the adhesive material 204 It is preferably inserted into an edge portion, for example a portion corresponding to the magnet 203. The ferromagnetic material 205 may be composed of a plurality of conductive fillers.

전술한 바와 같이, 이러한 강자성체의 특성을 이용하여 본 발명은, 상기 기판과 반도체칩을 물리적으로 접착시켜 상기 기판과 반도체칩 사이의 접착력을 증가시킬 수 있다. 또한, 본 발명은 상기 반도체칩과 기판과의 접착력 약화로 상기 반도체칩의 휨 현상으로 인해 발생하는 불량을 억제할 수 있다. As described above, the present invention by using the characteristics of the ferromagnetic material, by physically bonding the substrate and the semiconductor chip can increase the adhesion between the substrate and the semiconductor chip. In addition, the present invention can suppress the defect caused by the warpage phenomenon of the semiconductor chip by weakening the adhesion between the semiconductor chip and the substrate.

계속해서, 상기 연결부재(W)는 상기 기판(200)의 상기 본드핑거(202)와 상기 반도체칩(208)의 상기 본딩패드(209) 사이를 전기적으로 연결하며, 예를 들어, 금속 와이어일 수 있다. Subsequently, the connection member W electrically connects between the bond finger 202 of the substrate 200 and the bonding pad 209 of the semiconductor chip 208, for example, a metal wire. Can be.

전술한 바와 같이, 본 발명은 기판 상에 부착되는 반도체칩의 휨 또는 들뜸을 방지하기 위하여 상기 기판 상에 반도체칩을 부착시, 가장자리 부분(모서리 부분)에 자석을 구비한 기판과 상기 기판의 가장자리 부분에 대응하는 부분에 강자성체가 삽입된 접착제를 이용하여 상기 기판 상에 상기 반도체칩을 부착함으로써, 상기 기판과 상기 반도체칩 간을 물리적으로 고정시켜줄 수 있다. As described above, the present invention, when the semiconductor chip is attached to the substrate in order to prevent bending or lifting of the semiconductor chip attached to the substrate, the substrate having a magnet on the edge portion (edge portion) and the edge of the substrate By attaching the semiconductor chip on the substrate using an adhesive in which a ferromagnetic material is inserted into a portion corresponding to the portion, the substrate and the semiconductor chip may be physically fixed.

이렇게 함으로써, 본 발명은 상기 기판의 자석과 상기 접착제의 강자성체를 통하여 상기 기판과 반도체칩들 사이의 접착력을 종래 대비 효과적으로 증가시킬 수 있다. By doing so, the present invention can effectively increase the adhesive force between the substrate and the semiconductor chip through the ferromagnetic material of the magnet and the adhesive of the substrate compared with the conventional.

따라서, 본 발명은 상기 기판과의 접착력 약화로 반도체칩의 휨 현상으로 인해 발생하는 불량을 억제할 수 있으므로, 패키지 수율 및 작업성을 향상시킬 수 있다. Therefore, the present invention can suppress the defects caused by the warpage of the semiconductor chip due to the weakened adhesion to the substrate, it is possible to improve the package yield and workability.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

*도면의 주요 부분에 대한 부호의 설명*
200 : 기판 202 : 본딩패드
203 : 자석 204 : 접착물질
205 : 강자성체 206 : 접착제
208 : 반도체칩 209 : 본드핑거
W : 연결부재 210 : 반도체 패키지Description of the Related Art [0002]
200: substrate 202: bonding pad
203: magnet 204: adhesive material
205: ferromagnetic material 206: adhesive
208 semiconductor chip 209 bond finger
W: connecting member 210: semiconductor package

Claims (8)

상면 및 상기 상면에 대향하는 하면을 가지며 자석을 구비한 기판;
상기 기판의 상면 상에 배치되며, 상기 기판의 상면과 마주하는 일면 및 상기 일면에 대향하는 타면을 갖는 반도체칩; 및
상기 기판의 상면 및 상기 반도체칩의 일면 사이에 개재된 강자성체를 갖는 접착제;
를 포함하는 반도체 패키지. A substrate having a top surface and a bottom surface opposite the top surface, the substrate comprising a magnet;
A semiconductor chip disposed on an upper surface of the substrate and having one surface facing the upper surface of the substrate and the other surface opposite to the one surface; And
An adhesive having a ferromagnetic body interposed between an upper surface of the substrate and one surface of the semiconductor chip;
Semiconductor package comprising a. 제 1 항에 있어서,
상기 자석은 상기 기판의 상면에 배치된 것을 특징으로 하는 반도체 패키지. The method of claim 1,
The magnet is a semiconductor package, characterized in that disposed on the upper surface of the substrate. 제 1 항에 있어서,
상기 자석은 상기 강자성체보다 큰 크기를 갖는 것을 특징으로 하는 반도체 패키지. The method of claim 1,
The magnet package has a larger size than the ferromagnetic material. 제 1 항에 있어서,
상기 강자성체는 상기 자석과 대응하는 부분에 삽입된 것을 특징으로 하는 반도체 패키지.
The method of claim 1,
The ferromagnetic material is a semiconductor package, characterized in that inserted into the portion corresponding to the magnet.
제 1 항에 있어서,
상기 강자성체는 다수의 전도성 필러로 구성된 것을 특징으로 하는 반도체 패키지. The method of claim 1,
The ferromagnetic material is a semiconductor package, characterized in that consisting of a plurality of conductive fillers. 제 1 항에 있어서,
상기 자석 및 상기 강자성체는 각각 상기 반도체칩의 적어도 마주하는 양측 가장자리에 대응하는 부분들에 배치되는 것을 특징으로 하는 반도체 패키지. The method of claim 1,
And the magnet and the ferromagnetic material are disposed in portions corresponding to at least opposite edges of the semiconductor chip, respectively. 제 6 항에 있어서,
상기 자석 및 상기 강자성체는 각각 상기 반도체칩의 각 모서리 부분에 대응하는 부분들에 배치되는 것을 특징으로 하는 반도체 패키지. The method according to claim 6,
The magnet and the ferromagnetic material is a semiconductor package, characterized in that disposed in portions corresponding to each corner portion of the semiconductor chip. 제 1 항에 있어서,
상기 기판과 상기 반도체칩들 간을 전기적으로 연결하는 연결부재를 더 포함하는 것을 특징으로 하는 반도체 패키지. The method of claim 1,
And a connection member electrically connecting the substrate and the semiconductor chips.
KR1020100110238A 2010-11-08 2010-11-08 Semiconductor package KR20120048840A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150121398A (en) * 2014-04-18 2015-10-29 에스케이하이닉스 주식회사 Semiconductor package and the method for fabricating of the same
US9402315B2 (en) 2013-10-29 2016-07-26 Samsung Electronics Co., Ltd. Semiconductor package having magnetic connection member
US9437554B2 (en) 2013-11-12 2016-09-06 Samsung Electronics Co., Ltd. Semiconductor package having magnetic substance and related equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9402315B2 (en) 2013-10-29 2016-07-26 Samsung Electronics Co., Ltd. Semiconductor package having magnetic connection member
US9437554B2 (en) 2013-11-12 2016-09-06 Samsung Electronics Co., Ltd. Semiconductor package having magnetic substance and related equipment
KR20150121398A (en) * 2014-04-18 2015-10-29 에스케이하이닉스 주식회사 Semiconductor package and the method for fabricating of the same

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