KR20120044071A - Method for step patterning of semiconductor devices - Google Patents

Method for step patterning of semiconductor devices Download PDF

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Publication number
KR20120044071A
KR20120044071A KR1020100105462A KR20100105462A KR20120044071A KR 20120044071 A KR20120044071 A KR 20120044071A KR 1020100105462 A KR1020100105462 A KR 1020100105462A KR 20100105462 A KR20100105462 A KR 20100105462A KR 20120044071 A KR20120044071 A KR 20120044071A
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KR
South Korea
Prior art keywords
hard mask
pattern
layer
spacer
mask layer
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KR1020100105462A
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Korean (ko)
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박찬하
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에스케이하이닉스 주식회사
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Priority to KR1020100105462A priority Critical patent/KR20120044071A/en
Publication of KR20120044071A publication Critical patent/KR20120044071A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • G03F7/2014—Contact or film exposure of light sensitive plates such as lithographic plates or circuit boards, e.g. in a vacuum frame
    • G03F7/2016—Contact mask being integral part of the photosensitive element and subject to destructive removal during post-exposure processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A pattern formation method of a semiconductor device is provided to arrange a fine pattern which has a size less than 20nm without performing a double patterning process in which a spacer patterning processes is performed for two times or a two photo is used for two times. CONSTITUTION: A second spacer pattern(112a) is formed on side parts of a second hard mask pattern and a first hard mask pattern(102a). The first hard mask pattern is removed. The second hard mask pattern formed on a region excluding the lower part of the second spacer pattern is removed. A third hard mask pattern is formed by etching a third hard mask layer. An etching target layer(100) is etched using the third hard mask pattern as an etching barrier.

Description

Method for forming pattern of semiconductor device {Method for step patterning of semiconductor devices}

The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly to a pattern forming method of a semiconductor device capable of realizing a fine pattern.

In general, semiconductor devices have various types of films such as an oxide film, a nitride film, a metal film, and a polysilicon film formed on a silicon wafer in a multi-layered structure. There are several processes. A lithography process is an exposure process for patterning a deposited metal film, an oxide film, etc. to a desired form. That is, a photoresist film is formed on the target film to be patterned on the wafer. After performing exposure using a photomask on the photoresist film, the exposed photoresist film is developed to form a photoresist film pattern exposing a part of the surface of the target film. Next, patterns are formed on the wafer by removing the exposed portion of the target film by etching using the photoresist film pattern as an etching mask.

As the integration of semiconductor devices increases, the resolution required for semiconductor devices becomes smaller than the minimum resolution that can be resolved using photolithography equipment. For example, when the minimum resolution that can be resolved through a single exposure using photolithography equipment is 45 nm, the resolution required in the semiconductor device requires a resolution smaller than 40 nm. Various techniques for forming ultra fine patterns by overcoming the limitations of the photolithography equipment have been proposed. One of the techniques is a patterning technique using a spacer. Patterning techniques using spacers are highly feasible because they are self-aligned without being affected by overlay. When patterning with single exposure technology using ArF Immersin exposure equipment, the minimum half pitch of Dense Pattern is 40nm. Therefore, the technical limitations of DRAM and FLASH memory products, which consist of Dence Pattern, have remained at 40nm level. However, with the introduction of spacer patterning technology, pitch doubling has become possible. In other words, the patterning technology of 40nm, which could be realized by the existing single exposure technology, is now expanding to 20nm.

1 is a process flowchart showing a pattern forming method according to the prior art.

Referring to FIG. 1, first, the third hard mask layer 16, the second hard mask layer 14, and the first hard mask layer 12 are sequentially stacked on the etching target layer 10, and then sequentially stacked thereon. The photoresist pattern 18 is formed (FIG. 1A). At this time, the distance (pitch) between the photoresist patterns is represented by P.

Next, the first hard mask layer 12 is etched using the photoresist pattern 18 as an etch barrier to form a first hard mask pattern 12a (FIG. 1B). Thereafter, the photoresist pattern 18 is removed.

Next, the spacer pattern 20 is formed on the sidewall of the first hard mug pattern 12a (FIG. 1C).

Next, the first hard mask pattern 12a is removed, and the second hard mask layer 14 is etched using the spacer pattern 20 as an etch barrier to form a second hard mask pattern 14a (FIG. 1D). ).

Subsequently, the third hard mask layer 16 is etched using the second hard mask pattern 14a as an etch barrier, and the etching target layer 10 is etched.

It can be seen that the pitch of the pattern formed through the spacer patterning process is reduced by half when comparing the arrows of the same size in FIGS. 1A and 1D. However, with the current technology, since the pitch of a pattern that can be implemented in a single exposure is only about 40 nm, it is impossible to form a half pitch of less than 20 nm even if the spacer patterning technique is applied. This requires either applying the same spacer patterning technology once again or using an Extreme Ultraviolet (EUV) source (13.5 nm) shorter than the ArF 193 nm wavelength. However, both of these methods have the disadvantage of greatly increasing the complexity of the process and costing too much to apply to mass production. Moreover, in the case of EUV, development maturity in the exposure apparatus, mask, photoresist, and inspection remains low.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a pattern of a semiconductor device capable of implementing a fine pattern using a single exposure technique.

In addition, the present invention provides a method of forming a pattern of a semiconductor device capable of realizing a fine pattern of 20 nm or less without applying EUV or two spacer patterning processes.

In the method of forming a pattern of a semiconductor device according to an embodiment of the present invention, the step of sequentially stacking a third hard mask layer, a second hard mask layer and a first hard mask layer on the etching target layer, the first hard mask layer Etching to form a first hard mask pattern, forming a first spacer pattern on a side of the first mask pattern, and a second hard mask exposed by the first mask pattern and the first spacer pattern. Etching the layer to form a second hard mask pattern, removing the first spacer pattern, and forming a second spacer pattern on a side of the first hard mask pattern and on a side of the second mask. And removing the second hard mask pattern except for the second hard mask pattern existing under the second spacer pattern. Forming a third hard mask pattern by etching the third hard mask layer using the second spacer pattern and the second hard mask pattern remaining as the etch barrier; and forming a third hard mask pattern as an etch barrier. And etching the etching target layer.

In one embodiment, the first hard mask layer, the second hard mask layer or the third hard mask layer may include an organic material.

In an embodiment, the first hard mask layer, the second hard mask layer, or the third hard mask layer may include an organic material including a polyamic acid or a silicon-containing organic material.

In one embodiment, the first hard mask layer, the second hard mask layer and the third hard mask layer may be made of different materials.

In some embodiments, the first hard mask layer, the second hard mask layer, or the third hard mask layer may include at least one of silicon nitride, silicon oxynitride, polysilicon, titanium nitride, amorphous carbon, and tungsten (W). It may include.

In an embodiment, the first spacer pattern or the second spacer pattern may include silicon oxide, silicon nitride, or polysilicon.

In an embodiment, the forming of the first spacer pattern or the forming of the second spacer pattern may be performed by chemical vapor deposition (CVD).

In an embodiment, the forming of the first spacer pattern may include forming a first spacer layer on the upper portion of the first hard mask pattern and on the second hard mask layer, and etching back the first spacer layer. It may include.

In example embodiments, the forming of the second spacer pattern may include a third hard mask layer exposed through an upper portion of the first hard mask pattern, an upper portion of the second hard mask pattern, and an opening of the second hard mask pattern. The method may include forming a second spacer layer on the top of the second spacer layer and etching back the second spacer layer.

The method of forming a pattern of a semiconductor device of the present invention has an advantage of realizing a fine pattern of a semiconductor device by using a single exposure technique.

In addition, there is an advantage in that a fine pattern of 20 nm or less (10 nm class) can be realized without applying a double spacer patterning process (Double SPT) and a double patterning process using a photomask twice.

1A to 1D are process flowcharts illustrating a pattern forming method according to the prior art.
2A to 2K are flowcharts illustrating a method of forming a pattern of a semiconductor device according to an embodiment of the present invention.
3 is a cross-sectional view illustrating a method of forming a pattern of a semiconductor device in accordance with another embodiment of the present invention, in which a third hard mask pattern is formed.

2A to 2K are flowcharts illustrating a method of forming a pattern of a semiconductor device according to an embodiment of the present invention. Hereinafter, a description will be given with reference to FIGS. 2A to 2K.

First, the third hard mask layer 106, the second hard mask layer 104, and the first hard mask layer 102 are sequentially stacked on the etching target layer 100, and the first hard mask layer 102 is stacked on the first hard mask layer 102. The photoresist is coated and the photoresist pattern 108 is formed through known lithography processes such as exposure, development, and the like (FIG. 2A). In this case, the distance (pitch) between the photoresist patterns is represented by P, which is the same as the pitch P shown in FIG. 1A.

The etching target layer 100 may be a layer for forming a pattern such as a gate, a bit line, an active pattern, or the like that constitutes a semiconductor device (device). For example, in the case of a layer for an active pattern, the etching target layer 100 may be a silicon wafer itself, and in the case of a gate forming layer, a conductive layer or a metal layer, such as a conductive polysilicon layer, a tungsten layer, or a tungsten silicide layer, may be used. Can be. In the case of forming a bit line, the layer may be a metal layer such as aluminum, copper, or tungsten. In addition, the etching target layer 100 may be a layer for forming a hard mask for forming various patterns constituting the semiconductor device, or a layer for forming a damascene pattern. For example, it may be a silicon oxide layer, silicon nitride layer, silicon oxynitride layer, SiBN layer, BN layer. When the etching target layer 100 is a layer for forming a hard mask, a layer existing below the metal layer, such as a polysilicon layer, a tungsten (W), aluminum (Al), or titanium (Ti), in which a pattern is formed by a hard mask, or A metal nitride layer such as tungsten nitride (WN) or titanium nitride (TiN) may be a metal silicide layer such as tungsten silicide (WSix) or titanium silicide (TiSix).

The hard mask constituting the first hard mask layer 102, the second hard mask layer 104, or the third hard mask layer 106 may include silicon nitride, silicon oxynitride, polysilicon, titanium nitride, amorphous carbon, and tungsten ( W) may include any one or more, and may be formed by chemical vapor deposition (CVD). In addition, the first hard mask layer 102, the second hard mask layer 104, or the third hard mask layer 106 may be formed of a material including an organic material. For example, the organic material may include a polyamic acid and a silicon-containing organic material. The silicon-containing organic material may be a condensation reactant of a silane compound such as R a Si (OR) 4-a (a = 2, 3 or 4, R is methyl, ethyl, etc.). The hard mask including the organic material may be formed by spin coating, sol-gel coating, or the like.

Although not shown in the drawings, an anti-reflection layer may further exist between the first hard mask layer 102 and the photoresist pattern 108. The antireflection layer is formed to prevent diffuse reflection during the exposure process and may be formed of silicon oxynitride (SiON), an organic material, or the like. However, when the first hard mask layer 102 has an antireflection function, the antireflection layer may not exist.

Next, the first hard mask layer 102 is etched using the photoresist pattern 108 as an etch barrier to form the first hard mask pattern 102a (FIG. 2B). The first hard mask layer 102 may be removed by anisotropic etching. For example, when the first hard mask layer 102 is a carbon-based material such as amorphous carbon, the first hard having a vertical profile by performing dry etching using N 2 , O 2, and H 2 gases The mask pattern 102a may be formed. In the case where the first hard mask layer 102 is a nitride, the etched shape has a vertical profile by using a CF gas selected from CF 4 or C 2 F 6 , a CHF gas such as CHF 3 , O 2 and Ar gas. One hard mask pattern 102a may be formed. When the first hard mask layer 102 is an organic material, a first hard mask pattern 102a having a vertical profile may be formed through dry etching using a CF-based gas and / or dry plasma using an O 2 plasma. The foregoing example is one embodiment and the present invention is not limited thereto.

Next, a first spacer layer 110 is formed on the second hard mask layer 104 exposed between the first hard mask pattern 102a and the first hard mask pattern 102a (FIG. 2C). The first spacer layer 110 may form silicon oxide (SiOx), silicon nitride (SiNx), polysilicon, or the like by chemical vapor deposition (CVD), but the material and method of forming the first spacer layer 110 may be used. There is no limit.

Next, the first spacer layer 110 is etched back to form a first spacer pattern 110a. The first spacer layer 110 may be etched back, leaving the first spacer layer on the side of the first hard mask pattern 102a and remaining portions of the first spacer layer 110 to form the first spacer pattern 110a having the opening. The etch back may use an etching using plasma, and an etching gas including fluorine-containing gas such as CHF 3 , Cl 2 , HBr, O 2, or the like may be used according to the material of the first spacer layer 110.

Next, the second hard mask layer 104 exposed through the opening of the first spacer pattern 110a is etched to form a second hard mask pattern 104a (FIG. 2E). An etching of the second hard mask layer 104 is preferably anisotropic etching, and may form an opening having a vertical profile through the anisotropic etching. For example, when the second hard mask layer 104 is a carbon-based material such as amorphous carbon, the second hard having a vertical profile by performing dry etching using N 2 , O 2 and H 2 gases. The mask pattern 104a may be formed. In the case where the second hard mask layer 104 is a nitride, the etched shape has a vertical profile by using a CF gas selected from CF 4 or C 2 F 6 , a CHF gas such as CHF 3 , O 2 and Ar gas. Two hard mask patterns 104a may be formed. When the second hard mask layer 104 is an organic material, a second hard mask pattern 104a having a vertical profile may be formed through dry etching using a plasma based on CF gas and / or O 2 plasma. The above-described example is an embodiment, and other etching methods may be used, of course.

Next, the first spacer pattern 110a is removed (FIG. 2F). The removal of the first spacer pattern 110a may be performed by adjusting the etching selectivity of the material constituting the first spacer pattern 110a and the material constituting the first hard mask pattern 102a and the third hard mask layer 106. It can be removed, but there is no limit to the method of removal.

Next, a second spacer layer 112 is formed (FIG. 2G). The second spacer layer 112 is exposed through the openings (space portions of the line and space) of the upper portion of the first hard mask pattern 102a, the upper portion of the second hard mask pattern 104a, and the second hard mask pattern 104a. The second spacer layer 112 may be formed by depositing a material having a predetermined thickness on the third hard mask layer 106. The second spacer layer 112 may form silicon oxide, silicon nitride, polysilicon, or the like by chemical vapor deposition (CVD), but the material and the method of forming the second spacer layer 112 are not limited. In addition, the second spacer layer 112 may be made of the same material as or different from the first spacer layer 110.

Next, the second spacer layer 112 is etched back to form a second spacer pattern 112a (FIG. 2H). The second spacer layer 112 is etched back, leaving the second spacer layer on the side of the first hard mask pattern 102a and the side (opening side) of the second hard mask pattern 104a, and removing the rest of the second spacer layer ( 112a). That is, the second spacer pattern 112a may have a two-stage structure of the side portion of the second hard mask pattern 104a and the side portion of the first hard mask pattern 102a. The etch back may use an etching using plasma, and an etching gas including fluorine-containing gas such as CHF 3 , Cl 2 , HBr, O 2, or the like may be used according to the material of the second spacer layer 112.

Next, the first hard mask pattern 102a is removed (FIG. 2I). Removal of the first hard mask pattern 102a controls the etching selectivity of the material constituting the first hard mask pattern 102a and the material constituting the second spacer pattern 112a and the second hard mask pattern 104a. Can be removed, but the removal method is not limited. For this purpose, the material constituting the first hard mask layer 102 may be different from the material constituting the second hard mask layer 104 and the material constituting the second spacer layer 112.

Next, the second hard mask pattern 104a is etched using the second spacer pattern 112a as an etch barrier, and the remaining second hard mask pattern is removed except for the second hard mask pattern under the second spacer pattern 112a. Remove (FIG. 2J). The remaining second hard mask pattern is indicated by reference numeral 104b.

The etching of the second hard mask pattern 104a is preferably anisotropic etching. For example, when the second hard mask pattern 104a or the second hard mask layer 104 is made of nitride, a CF gas selected from CF 4 or C 2 F 6 , a CHF gas such as CHF 3 , O 2 And the second hard mask pattern 104b having an etched profile having a vertical profile by using Ar gas. When the second hard mask pattern 104a is an organic material, a second hard mask pattern 104b having a vertical profile may be formed through dry etching using a plasma based on CF gas and / or O 2 plasma. The above-described example is an embodiment, and other etching methods may be used, of course.

Next, the third hard mask layer 106 is etched using the second spacer pattern 112a and the remaining second hard mask pattern 104b as an etch barrier to form a third hard mask pattern 106a (FIG. 2K). ). The etching of the third hard mask layer 106 is preferably anisotropic etching. For example, when the third hard mask layer 106 is formed of nitride, the etched shape may be changed by using a CF gas selected from CF 4 or C 2 F 6 , a CHF gas such as CHF 3 , O 2 and Ar gas. A third hard mask pattern 106a having a vertical profile may be formed. When the third hard mask layer 106 is an organic material, a third hard mask pattern 106a having a vertical profile may be formed through dry etching using a CF-based gas and / or dry plasma using an O 2 plasma. The above-described example is an embodiment, and other etching methods may be used, of course. Thereafter, the etching target layer 100 is etched using the third hard mask pattern 106a as an etching barrier using a known semiconductor process technology.

FIG. 2K illustrates a case where the widths W 1 , W 2 , W 3 , W 4 , W 5 , W 6 , and W 7 of the third hard mask pattern 106a are all different or only partially different. However, as shown in FIG. 3, the width W of the third hard mask pattern may be constant by adjusting the etch back process of the spacer.

The length (size, P) of the arrow shown in FIG. 3 is the same as the length (P of FIG. 1A) mentioned in the prior art, compared to the initial photoresist pattern when comparing the number of patterns (line & space structure) made in the same space. 3 times, 1.5 times more than the spacer pattern can be seen that. That is, it is possible to obtain a 13 nm half pitch pattern from the 40 nm half pitch pattern by reducing the 1/3 of the pitch of the pattern embodied in the single exposure. That is, it is possible to form a fine pattern of 20 nm or less (10 nm class) without using EUV, Double Spacer Patterning technology or Double Patterning technology.

100 ... etched layer 102 ... first hard mask layer
102a ... first hard mask pattern 104 ... second hard mask layer
104a. 104b ... second hardmask pattern 106a ... third hardmask pattern
108 ... photoresist pattern 110 ... first spacer layer
110a ... First spacer pattern 112 ... Second spacer layer
112a ... Second Spacer Pattern

Claims (9)

Sequentially stacking a third hard mask layer, a second hard mask layer, and a first hard mask layer on the etching target layer;
Etching the first hard mask layer to form a first hard mask pattern;
Forming a first spacer pattern on a side of the first mask pattern;
Etching a second hard mask layer exposed by the first mask pattern and the first spacer pattern to form a second hard mask pattern;
Removing the first spacer pattern;
Forming a second spacer pattern on a side of the first hard mask pattern and on a side of the second hard mask pattern;
Removing the first hard mask pattern;
Removing the second hard mask pattern except for the second hard mask pattern existing under the second spacer pattern;
Forming a third hard mask pattern by etching a third hard mask layer using the second hard mask pattern remaining as the etch barrier as the second spacer pattern; And
Etching the etching target layer using the third hard mask pattern as an etching barrier;
Pattern formation method of a semiconductor device comprising a. The method of claim 1,
The method of claim 1, wherein the first hard mask layer, the second hard mask layer, or the third hard mask layer comprises an organic material. The method of claim 1,
The method of claim 1, wherein the first hard mask layer, the second hard mask layer, or the third hard mask layer is an organic material containing polyamic acid or a silicon-containing organic material. The method of claim 1,
The first hard mask layer, the second hard mask layer and the third hard mask layer is a pattern forming method of a semiconductor device made of different materials. The method of claim 1,
The first hard mask layer, the second hard mask layer, or the third hard mask layer may include at least one of silicon nitride, silicon oxynitride, polysilicon, titanium nitride, amorphous carbon, and tungsten (W). Pattern Formation Method The method of claim 1,
The method of claim 1, wherein the first spacer pattern or the second spacer pattern includes silicon oxide, silicon nitride, or polysilicon. The method of claim 1,
The forming of the first spacer pattern or the forming of the second spacer pattern is performed by chemical vapor deposition (CVD). The method of claim 1,
The forming of the first spacer pattern may include forming a first spacer layer on an upper portion of the first hard mask pattern and on an upper portion of the second hard mask layer; And etching back the first spacer layer. The method of claim 1,
The forming of the second spacer pattern may include forming a second spacer on an upper portion of the first hard mask pattern, an upper portion of the second hard mask pattern, and an upper portion of the third hard mask layer exposed through the opening of the second hard mask pattern. Forming a spacer layer; And etching back the second spacer layer.


KR1020100105462A 2010-10-27 2010-10-27 Method for step patterning of semiconductor devices KR20120044071A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150065608A (en) * 2013-12-05 2015-06-15 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Self-aligned double spacer patterning process
KR20160030430A (en) * 2014-09-10 2016-03-18 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Method of semiconductor integrated circuit fabrication

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150065608A (en) * 2013-12-05 2015-06-15 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Self-aligned double spacer patterning process
US9831117B2 (en) 2013-12-05 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned double spacer patterning process
KR20160030430A (en) * 2014-09-10 2016-03-18 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Method of semiconductor integrated circuit fabrication
US9941139B2 (en) 2014-09-10 2018-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication

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