KR20120041439A - Nitride semiconductor device and method for manufacturing thereof - Google Patents

Abstract

PURPOSE: A nitride type semiconductor device and a manufacturing method thereof are provided to reduce crystal defects by securing good lattice consistency with another layer which is adjacent to a corresponding layer. CONSTITUTION: A base substrate is prepared(S21). A nitride nucleation layer is formed on the base substrate(S23). A buffer layer is formed on the base substrate based on the nitride nucleation layer(S25). An n-type semiconductor layer is formed on the buffer layer(S27). An n-type clad layer is formed on the n-type semiconductor layer(S29). An active layer is formed on the n-type clad layer(S31). A p-type cladding layer is formed on the active layer(S33). A p-type semiconductor layer is formed on the p-type cladding layer(S35).

Description

Nitride-based semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to determine a total supply amount of a plurality of Group III sources when forming a layer of a nitride material constituting a nitride-based semiconductor device, and to select at least one of a plurality of Group III sources. A nitride-based semiconductor device and a method for manufacturing the same, which provide a lattice match between layers of a nitride material constituting a nitride-based semiconductor device by varying one supply amount into a stepped or curved shape, thereby forming a layer.

Generally gallium nitride (GaN), aluminum nitride (AlN), indium nitride containing a Group V source such as nitrogen (N) and a Group III source such as gallium (Ga), aluminum (Al), or indium (In) Nitride semiconductor materials such as (InN) have excellent thermal stability and have a direct transition type energy band structure, and thus are widely used for nitride-based semiconductor devices such as nitride-based semiconductor light emitting devices and solar cells in the ultraviolet region. . Indium aluminum nitride (AlInN) -based materials have a wide energy bandgap of 0.7 eV to 6.2 eV, and thus are widely used as materials for solar cell devices due to their characteristics consistent with the solar spectrum region. In particular, UV light emitting devices using aluminum gallium nitride (AlGaN) are used in various industrial fields such as curing devices, medical analyzers and treatment devices, and sterilization, water purification, and purification systems. It is getting attention.

Among such nitride semiconductor devices, a nitride semiconductor light emitting device has a structure of a buffer layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and an electrode on a base substrate.

At this time, the buffer layer is formed in order to suppress the occurrence of cracks, warpages or dislocations in the n-type semiconductor layer due to the difference in lattice constant and thermal expansion coefficient between the base substrate and the n-type semiconductor layer. The buffer layer is formed in multiple layers so as to be gradually changed.

The active layer is a region where electrons and holes are recombined, and has a structure in which a quantum well layer is disposed between quantum barrier layers. The wavelength of light emitted from the nitride semiconductor light emitting device is determined according to the type of the material forming the active layer.

The active layer includes a single quantum well (SQW) structure having one quantum well layer, a multi quantum well (MQW) structure having a plurality of quantum well layers, a superlattice (SL) structure, and the like. have. Among these, in particular, the active layer of the multi-quantum well structure is actively used because it has better luminous efficiency compared to the current and has a high luminous output compared to the single quantum well structure.

The luminous efficiency of the nitride-based semiconductor device is determined by the probability of recombination of electrons and holes that are primarily involved in light emission in the active layer, that is, internal quantum efficiency (IQE). The internal quantum efficiency refers to the number of photons compared to the number of recombined electrons.In order to improve the internal quantum efficiency, electrons and holes flow into the active layer when a voltage is applied, and they effectively trap electrons and holes in the active layer. In other words, the characteristics of recombination of electrons and holes in the active layer should be considered as a whole.

In order to improve the internal quantum efficiency, research has been conducted mainly toward improving the structure of the active layer itself or increasing the number of electrons and holes participating in the emission process. For example, in order to improve the internal quantum efficiency of a nitride semiconductor light emitting device, a method of providing a symmetrical superlattice structure as a cladding layer between an active layer and an n-type semiconductor layer or between an active layer and a p-type semiconductor layer has been proposed.

In addition, an n-type semiconductor layer and a p-type semiconductor layer have been introduced to form a multilayer in order to improve the performance of the nitride semiconductor light emitting device.

As described above, since the components constituting the nitride semiconductor light emitting device according to the prior art, for example, a buffer layer, an n-type semiconductor layer, an n-type cladding layer, an active layer, a p-type cladding layer and a p-type semiconductor layer are each formed in multiple layers, nitride The manufacturing process of the semiconductor semiconductor light emitting device is complicated, and a process time is required to manufacture the nitride semiconductor light emitting device. In addition, it takes a long time to manufacture a solar cell device, such as the nitride-based semiconductor light emitting device described above.

In addition, since each component is formed in multiple layers, there is a possibility that a problem occurs at the interface between the layers constituting the component, and there is a need to consider the interface compatibility between the layers constituting the component.

Accordingly, an object of the present invention is to provide a nitride-based semiconductor device and a method of manufacturing the same that can improve lattice match between layers constituting the nitride-based semiconductor device.

Another object of the present invention is to provide a nitride-based semiconductor device having a single structure and a method for manufacturing the same, which can solve the interlayer interfacial compatibility problem of the multi-layered component.

In order to achieve the above object, the present invention is a method of manufacturing a nitride-based semiconductor device to form a nitride layer by supplying a Group V source and a plurality of Group III source, the total supply amount of the plurality of Group III source is determined, A method of manufacturing a nitride-based semiconductor device is provided by variably supplying at least one of a group III source in a stepped or curved form.

In the method of manufacturing a nitride-based semiconductor device according to the present invention, the nitride layer includes at least one of a buffer layer, an n-type semiconductor layer, an n-type cladding layer, an active layer, a p-type cladding layer and a p-type semiconductor layer.

In the method for manufacturing a nitride-based semiconductor device according to the present invention, the plurality of group III sources contain at least two of B, Al, Ga, and In, and the group V source contains N.

In the method of manufacturing a nitride-based semiconductor device according to the present invention, the material of the nitride layer is Al _x In _y Ga _z B _w N (0≤x, y, z, w≤1, x + y + z + w = 1).

The present invention also provides a nitride-based semiconductor device comprising a nitride group formed by supplying a Group V source and a plurality of Group III sources, wherein at least one of the plurality of nitride layers is a total supply amount of the plurality of Group III sources. According to the present invention, a nitride-based semiconductor device is formed by variably supplying at least one of the plurality of group III sources in a stepped shape or a curved shape.

The present invention also provides a method of preparing a base substrate, a buffer layer forming step of forming a buffer layer on the base substrate, an n-type semiconductor layer forming step of forming an n-type semiconductor layer on the buffer layer, and the n-type semiconductor layer. It provides an active layer forming step of forming an active layer, and a p-type semiconductor layer forming step of forming a p-type semiconductor layer on the active layer. In this case, in at least one of the buffer layer forming step, the n-type semiconductor layer forming step, the active layer forming step, and the p-type semiconductor layer forming step, a Group V source and a plurality of Group III sources are supplied. A total supply amount of the group source is determined, and at least one of the plurality of group III sources is variably supplied in a stepped or curved form to form a corresponding layer.

In the method of manufacturing a nitride-based semiconductor device according to the invention, forming an n-type cladding layer on the n-type semiconductor layer before forming the active layer, or p-type on the active layer before forming the p-type semiconductor layer At least one step of forming the cladding layer may be further included. The forming of the n-type or p-type cladding layer may include supplying a Group V source and a plurality of Group III sources, determining a total supply amount of the plurality of Group III sources, and selecting at least one of the plurality of Group III sources. It is formed by variable supply in step or curve shape.

The present invention also provides a nitride-based semiconductor device comprising a base substrate, a buffer layer, an n-type semiconductor layer, an active layer and a p-type semiconductor layer. The buffer layer is formed on the base substrate. The n-type semiconductor layer is formed on the buffer layer. The active layer is formed on the n-type semiconductor layer. The p-type semiconductor layer is formed on the active layer. In particular, at least one of the buffer layer, the n-type semiconductor layer, the active layer, and the p-type semiconductor layer supplies a Group V source and a plurality of Group III sources, and determines a total supply amount of the plurality of Group III sources, Provided is a nitride-based semiconductor device characterized in that the layer is formed by variably supplying at least one of the group III source in step or curve shape.

The nitride-based semiconductor device according to the present invention may further include at least one of an n-type cladding layer formed between the n-type semiconductor layer and the active layer, or a p-type cladding layer formed between the active layer and the p-type semiconductor layer. Can be. In this case, the n-type or p-type cladding layer supplies a Group V source and a plurality of Group III sources, determines a total supply amount of the plurality of Group III sources, and at least one of the plurality of Group III sources is stepped or curved. It is formed by variable supply in a mold.

According to the structure of the present invention, when a buffer layer, an n-type semiconductor layer, an n-type cladding layer, an active layer, a p-type cladding layer, or a p-type semiconductor layer of a nitride material is formed on a base substrate, the total supply amount of a plurality of Group III sources is determined. And forming the layer by varying the supply amount of at least one of the plurality of group III sources into a stepped shape or a curved shape, so that the composition inside the layer can be changed while forming the layer integrally, and therefore, Good lattice match between the layer and other neighboring layers can be ensured, including lattice match. As a result, it is possible to reduce the occurrence of cracks, distortions, and dislocations due to differences in lattice constants and coefficients of thermal expansion between the layer and other layers formed above and below the layer.

In addition, by ensuring good lattice matching between the layer and other neighboring layers, including good lattice matching in the layer, the crystal defects are reduced, ultimately improving the internal quantum efficiency, thereby improving the luminous efficiency of the nitride semiconductor device. You can.

1 is a cross-sectional view illustrating a nitride based semiconductor device according to an exemplary embodiment of the present invention.
2 is a flowchart illustrating a method of manufacturing the nitride-based semiconductor device of FIG. 1.
3 to 7 are cross-sectional views showing each step according to the manufacturing method of FIG.
8 is a waveform diagram illustrating an example of supply conditions of a plurality of group III sources for forming the active layer of FIG. 2.
9 is a waveform diagram illustrating another example of supply conditions of a plurality of group III sources for forming the active layer of FIG. 2.

It should be noted that in the following description, only parts necessary for understanding the embodiments of the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

The terms or words used in the specification and claims described below should not be construed as being limited to the ordinary or dictionary meanings, and the inventors are appropriate to the concept of terms in order to explain their invention in the best way. It should be interpreted as meanings and concepts in accordance with the technical spirit of the present invention based on the principle that it can be defined. Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely preferred embodiments of the present invention, and are not intended to represent all of the technical ideas of the present invention, so that various equivalents And variations are possible.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present embodiment, a nitride semiconductor light emitting device among the nitride semiconductor devices is described as an example.

1 is a cross-sectional view illustrating a nitride based semiconductor device 10 according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the nitride-based semiconductor device 10 according to the embodiment of the present invention may include a base substrate 11, a buffer layer 13, an n-type semiconductor layer 14, an active layer 15, and a p-type semiconductor layer ( 16), and may further include a nitride nucleus growth layer 12, an n-type cladding layer 14a, and a p-type cladding layer 16a.

The nitride semiconductor device 10 according to the present embodiment includes a base substrate 11, a nitride nucleus growth layer 12, a buffer layer 13, and an n-type semiconductor layer 14 sequentially formed on the base substrate 11. and an n-type cladding layer 14a, an active layer 15, a p-type cladding layer 16a and a p-type semiconductor layer 16. In addition, the p-type electrode and the n-type electrode are formed in the nitride-based semiconductor device 10 to be connected to the outside. For example, in the nitride-based semiconductor device 10, a portion of the p-type semiconductor layer 16, the p-type cladding layer 16a, and the active layer 15 is removed by a mesa etching process, and the n-type semiconductor layer is removed. It may have a structure that part of the upper surface of (14) is exposed. An n-type electrode is formed on the exposed n-type semiconductor layer 14. A transparent electrode layer made of indium tin oxide (ITO) or the like is formed on the p-type semiconductor layer 16, and a p-type electrode may be formed thereon.

At this time, the nitride nucleus growth layer 12, the buffer layer 13, the n-type semiconductor layer 14, the n-type cladding layer 14a, the active layer 15, the p-type cladding layer and the p-type semiconductor layer 16 are group III. And a group V source. In this case, B, Al, Ga, In, etc. may be used as the group III source. N, P, As, Sb, etc. may be used as the group V source, and a source containing N is used in this embodiment. Each layer may be made of Al _x In _y Ga _z B _w N (0 ≦ x, y, z, _w ≦ 1, x + y + z + w = 1) and have different chemical compositions. As the group III source, TMAl (trimethylaluminum) containing Al, TMIn (trimethylindium) containing In, TMGa (trimethylgallium) containing Ga, etc. may be used. NH ₃ containing N may be used as the Group V source.

The base substrate 11 may be made of a material suitable for growing a nitride semiconductor single crystal. In this case, the base substrate 11 includes sapphire, silicon (Si), zinc oxide (ZnO), gallium nitride (GaN), gallium arsenide (GaAs), silicon carbide (SiC), and aluminum knight. It may be made of an element or a compound such as lide (AlN), magnesium oxide (MgO). For example, the base substrate 11 includes a sapphire substrate having a c plane ({0001} plane), an R plane ({1-102}), an M plane ({1-100}), and an A plane ({11-20}). Etc. may be used, and c surface is used as the base substrate 11 in this embodiment. The nitride nucleus growth layer 12, the buffer layer 13, the n-type cladding layer 14a, the n-type semiconductor layer 14, the active layer 15, the p-type cladding layer 16a, and the c-plane base substrate 11 The p-type semiconductor layer 16 may be formed sequentially.

The nitride nucleus growth layer 12 is formed on the base substrate 11. In this case, the nitride nucleus growth layer 12 may be made of GaN, AlN, AlGaN, InGaN, AlInN, AlGaInN, AlGaInBN, or the like.

The buffer layer 13 is to reduce the lattice constant difference between the base substrate 11 and the n-type semiconductor layer 14 and is formed on the base substrate 11 based on the nitride nucleus growth layer 12. In addition, the buffer layer 13 functions to alleviate stress between the base substrate 11 and the n-type semiconductor layer 14, such as to prevent melt-back etching due to the chemical action of the base substrate 11. Perform. In this case, the buffer layer 13 may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE) or metal organic chemical vapor phase epitaxy (MBE), metal It may be formed using a metal organic chemical vapor phase epitaxy (MOCVPE) and the like.

The n-type semiconductor layer 14 is formed on the buffer layer 13. The n-type semiconductor layer 14 is formed of aluminum gallium nitride (AlGaN) -based, and silicon may be doped to lower the driving voltage.

The n-type cladding layer 14a is formed on the n-type semiconductor layer 14. In this case, the n-type cladding layer 14a may be formed in a superlattice structure, and the superlattice structure may be formed symmetrically or asymmetrically.

The active layer 15 is formed on the n-type cladding layer 14a. The active layer 15 may be formed in a quantum well structure using a method such as MOCVD, HVPE, MBE, MOCVPE, and the like. In the active layer 15, light is generated by combining holes flowing through the p-type semiconductor layer 16 and electrons flowing through the n-type semiconductor layer 14, where a quantum well corresponds to an excitation level or an energy band gap difference. Light of energy is emitted.

The p-type cladding layer 16a is formed on the active layer 15. In this case, the p-type cladding layer 16a may be formed in a superlattice structure, and the superlattice structure may be formed symmetrically or asymmetrically.

In this case, the n-type and p-type cladding layers 14a and 16a are formed in a superlattice structure having a symmetrical or asymmetrical energy bandgap, thereby controlling the inflow of electrons and holes into the active layer 15 participating in the emission process. Internal quantum efficiency can be improved. That is, through the n-type and p-type cladding layers 14a and 16a, the efficiency of inflow of holes and the efficiency of binding into the active layer 15 of the introduced electrons and holes may be improved, thereby ultimately improving the internal quantum efficiency.

The p-type semiconductor layer 16 is formed on the p-type cladding layer 16a. The p-type semiconductor layer 16 is a semiconductor layer made of a nitride material doped with p-type conductive impurities such as Mg, Zn, Be, and the like. The p-type semiconductor layer 16 has a p-type AlGaN layer adjacent to the light emitting region and serves as an electron blocking layer (EBL), and p-type GaN and (Al) Ga (In) adjacent to the p-type AlGaN layer. It may consist of N layers.

In particular, in the present embodiment, among the buffer layer 13, the n-type semiconductor layer 14, the n-type cladding layer 14a, the active layer 15, the p-type cladding layer, and the p-type semiconductor layer 16, which were formed as a conventional multilayer, At least one is formed by determining the total supply amount of the plurality of group III sources, and at least one of the plurality of group III sources is variably supplied in a step type (Fig. 8) or a curve type (Fig. 9).

As described above, in the nitride-based semiconductor device 10 according to the present exemplary embodiment, the nitride layer buffer layer 13, the n-type semiconductor layer 14, the n-type cladding layer 14a, the active layer 15, and the like are formed on the base substrate 11. When the p-type cladding layer 16a or the p-type semiconductor layer 16 is formed, the total supply amount of the plurality of Group III sources is determined, and at least one of the plurality of Group III sources is variably supplied in a stepped or curved form to provide By forming a layer, the composition inside the layer can be changed while integrally forming the layer. This ensures good lattice match between the layer and other neighboring layers, including good lattice match within the layer. In addition, it is possible to reduce the occurrence of cracks, distortions, and dislocations due to the difference in lattice constants and thermal expansion coefficients between the layer and other layers formed above and below the layer.

In addition, by ensuring good lattice match between the layer and other neighboring layers, including good lattice match in the layer, reducing crystal defects, ultimately improving internal quantum efficiency to emit light of the nitride-based semiconductor device 10 The efficiency can be improved.

The nitride-based semiconductor device 10 according to the present embodiment determines the total supply amount of a plurality of group III sources, and forms at least one of the plurality of group III sources by varying stepwise or curved shapes to form the active layer 15. Started. For example, when the material of the formed active layer 15 is AlInGaN, the total supply amount of the Al source, the In source, and the Ga source is determined, and at least one of the Al source, the In source, and the Ga source is variably supplied in a stepped or curved shape to the active layer. (15) can be formed.

As shown in FIG. 8, the group III source involved in the formation of the active layer 15 can be continuously supplied by varying the supply amount of the Al source and the Ga source in a step shape while the In source is constantly supplied. In other words, assuming that the active layer 15 is formed at t3 time, the Al source of each of the Al source is in the range of 0 to t1, t1 to t2 and t2 to t3 while the supply amount Q4 of the In source is kept constant for t3 time. The supply amounts Q1, Q2 and Q3 and the supply amounts Q1 ', Q2' and Q3 'of the Ga source are varied stepwise to form the active layer 15. And the total supply amount of the Al source, In source and Ga source respectively supplied in the interval 0 ~ t1, t1 ~ t2 and t2 ~ t3 is constant. At this time, since there is a difference between the supply amount of the Al source (Q1, Q2, Q3) and the supply amount of the Ga source (Q1 ', Q2', Q3 ') in the intervals 0 to t1, t1 to t2, and t2 to t3, 0 to t1. The internal composition of the portions 15a, 15b, and 15c formed in the sections t1 to t2 and t2 to t3 are changed. However, since a plurality of group III sources are continuously supplied in a stepped form, the active layer 15 formed is integrally formed with a change in the internal composition. Therefore, good lattice matching in the active layer 15 can be ensured. In addition, the supply amount of the group V source and the plurality of group III sources is varied stepwise in consideration of lattice match between the neighboring layer, for example, the n-type cladding layer 14a and the p-type cladding layer 16a, so that the active layer 15 And good lattice matching between the n-type cladding layer 14a, the active layer 15 and the p-type cladding layer 16a can be ensured.

Alternatively, the group III source involved in the formation of the active layer 15 can be continuously supplied by continuously varying the supply amounts of the Al source and the Ga source in a state of constantly supplying the In source, as shown in FIG. 9. . In addition, the Group III source involved in the formation of the active layer 15 continuously supplies the Al source and the Ga source in a state where the In source is constantly supplied in a form where the step type and the curve type are mixed. Can be.

On the other hand, the nitride nucleus growth layer 12 and the buffer layer 13 may be formed by sequentially stacking by going through separate processes. Alternatively, the nitride nucleus growth layer 12 and the buffer layer 13 may be continuously processed in one process to form the nitride nucleus growth layer 12 and the buffer layer 13 of the III-V material in a row in a row. . That is, as described above, the total supply amount of the plurality of Group III sources is determined, and at least one of the plurality of Group III sources is variably supplied in a stepped or curved manner to form the nitride nucleus growth layer 12 and the buffer layer of the Group III-V material. (13) can be formed continuously and collectively.

A method of manufacturing the nitride semiconductor device 10 according to the present embodiment will be described with reference to FIGS. 2 to 9 as follows. 2 is a flowchart illustrating a method of manufacturing the nitride based semiconductor device 10 of FIG. 1. 3 to 7 are cross-sectional views showing each step according to the manufacturing method of FIG. 8 is a waveform diagram illustrating an example of supply conditions of a group III source for forming the active layer 15 of FIG. 2. FIG. 9 is a waveform diagram illustrating another example of a supply condition of a group III source for forming the active layer 15 of FIG. 2. On the other hand, in the manufacturing method according to the present embodiment, the buffer layer 13, the n-type semiconductor layer 14, the n-type cladding layer 14a, the active layer 15, the p-type cladding layer 16a and the p-type semiconductor layer 16 ), An example in which the total amount of supply of the plurality of group III sources is determined by the active layer 15 and at least one of the plurality of group III sources is variably supplied in a stepped or curved form is disclosed.

First, as shown in FIG. 3, the base substrate 11 is prepared in step S21. The base substrate 11 may include sapphire, silicon (Si), zinc oxide (ZnO), gallium nitride (GaN), gallium arsenide (GaAs), silicon carbide (SiC), aluminum nitride (AlN), magnesium oxide ( Substrates made of an element or compound material such as MgO) may be used. In this embodiment, a sapphire substrate having a c surface ({0001} surface) is used as the base substrate 11.

Next, as shown in FIG. 4, the nitride nucleus growth layer 12 is formed on the base substrate 11 in step S23. In this case, the nitride nucleus growth layer 12 may be formed using MOCVD, HVPE, MBE, or MOCVPE. For example, the nitride nucleus growth layer 12 formed using a group V source and a plurality of group III sources may be made of a material such as GaN, AlN, AlGaN, InGaN, AlInN, AlInGaN, AlInGaBN, or the like.

Next, as shown in FIG. 4, in step S25, the buffer layer 13 covering the nitride nucleus growth layer 12 is formed on the base substrate 11. The buffer layer 13 is used to reduce the lattice constant difference between the base substrate 11 and the n-type semiconductor layer 14. The nitride nucleus growth layer 12 is formed on the base substrate 11 based on the nitride nucleus growth layer 12. ) Is formed to cover.

In this case, the forming of the nitride nucleus growth layer 12 (S23) and the forming of the buffer layer 13 may be performed in separate steps as described above, or the nitride nucleus growth may be continuously performed in one process. The layer 12 and the buffer layer 13 can be formed continuously and collectively. That is, the total supply amount of the plurality of Group III sources is determined, and at least one of the plurality of Group III sources is variably supplied in a stepped or curved form to form the nitride nucleus growth layer 12 and the buffer layer 13 in a row in a row. Can be.

Next, as shown in FIG. 5, the n-type semiconductor layer 14 is formed on the buffer layer 13 in step S27. In this case, the n-type semiconductor layer 14 is formed of aluminum gallium nitride (AlGaN) -based, silicon may be doped to lower the driving voltage.

Next, as shown in FIG. 5, the n-type cladding layer 14a is formed on the n-type semiconductor layer 14 in step S29. In this case, the n-type cladding layer 14a may be formed in a superlattice structure, and the superlattice structure may be formed symmetrically or asymmetrically.

Next, as shown in FIG. 6, the active layer 15 is formed on the n-type cladding layer 14a in step S31. In this case, the active layer 15 may be formed in a quantum well structure. In the active layer 15, holes flowing through the p-type semiconductor layer (16 in FIG. 7) to be formed next and electrons flowing through the n-type semiconductor layer 14 are combined to generate light.

In particular, the active layer 15 is formed by determining the total supply amount of the plurality of group III sources and variably supplying at least one of the plurality of group III sources in a step type (FIG. 8) or a curve type (FIG. 9). For example, when the material of the formed active layer 15 is Al _x In _y Ga _z N (0 ≦ x, y, _z ≦ 1, x + y + z = 1), the total supply amount of Al source, In source and Ga source The active layer 15 may be formed by variably supplying at least one of an Al source, an In source, and a Ga source in a stepped shape or a curved shape. At this time, TMAl containing Al was used as the Al source, TMIn containing In was used as the In source, and TMGa containing Ga was used as the Ga source. NH ₃ containing N was used as the group V source.

As shown in FIG. 8, the group III source involved in the formation of the active layer 15 can be continuously supplied by varying the supply amount of the Al source and the Ga source in a step shape while the In source is constantly supplied. In other words, assuming that the active layer 15 is formed at t3 time, the Al source of each of the Al source is in the range of 0 to t1, t1 to t2 and t2 to t3 while the supply amount Q4 of the In source is kept constant for t3 time. The supply amounts Q1, Q2 and Q3 and the supply amounts Q1 ', Q2' and Q3 'of the Ga source are varied stepwise to form the active layer 15. And the total supply amount of the Al source, In source and Ga source respectively supplied in the interval 0 ~ t1, t1 ~ t2 and t2 ~ t3 is constant. At this time, since there is a difference between the supply amount of the Al source (Q1, Q2, Q3) and the supply amount of the Ga source (Q1 ', Q2', Q3 ') in the intervals 0 to t1, t1 to t2, and t2 to t3, 0 to t1. The internal composition of the portions 15a, 15b, and 15c formed in the sections t1 to t2 and t2 to t3 are changed. However, since a plurality of group III sources are continuously supplied in a stepped form, the active layer 15 formed is integrally formed with a change in the internal composition.

As a result, good lattice matching in the active layer 15 can be ensured. In addition, the supply amount of the Group V source and the plurality of Group III sources is varied in a stepped manner in consideration of lattice match between the n-type cladding layer 14a and the p-type cladding layer (16a in FIG. 7), thereby providing an active layer. Good lattice matching between (15) and n-type cladding layer 14a, active layer 15, and p-type cladding layer (16a in FIG. 7) can be ensured.

Alternatively, the group III source involved in the formation of the active layer 15 can be continuously supplied by continuously varying the supply amounts of the Al source and the Ga source in a state of constantly supplying the In source, as shown in FIG. 9. .

Next, as shown in FIG. 7, the p-type cladding layer 16a is formed on the active layer 14 in step S33. In this case, the p-type cladding layer 16a may be formed in a superlattice structure, and the superlattice structure may be formed symmetrically or asymmetrically.

As shown in FIG. 7, the p-type semiconductor layer 16 is formed on the p-type cladding layer 16a in step S35. At this time, the p-type semiconductor layer 16 is a semiconductor layer of a nitride material doped with p-type conductive impurities such as Mg, Zn, Be and the like. The p-type semiconductor layer 16 may be formed of a p-type AlGaN layer adjacent to the light emitting region and serving as an electron barrier layer (EBL), and a p-type AlGaInN layer, which is an ohmic contact layer adjacent to the p-type AlGaN layer.

Thereafter, a process of forming an external connection terminal of the nitride semiconductor element 10 is performed. In other words, the p-type semiconductor layer 16, the p-type cladding layer 16a and the active layer 15 are removed by a mesa etching process to form a structure in which a part of the upper surface of the n-type semiconductor layer 14 is exposed. do. An n-type electrode is formed on the exposed n-type semiconductor layer 14. A transparent electrode layer made of ITO or the like is formed on the p-type semiconductor layer 16, and a p-type electrode is formed thereon.

In this case, the transparent electrode layer is formed on the p-type semiconductor layer 16. The transparent electrode layer is a kind of electrode contact layer, so that current can be well transmitted to the p-type semiconductor layer. Such a transparent electrode layer may be made of, for example, ITO, ZnO, RuOx, TiOx, IrOx, or the like as a transparent oxide film. When the basic laminated structure from the base substrate 11 to the transparent electrode layer is completed as described above, a part of the n-type semiconductor layer 14 is exposed by performing wet etching, for example, anisotropic wet etching, from the surface. After the etching process is performed, titanium (Ti), gold (Au), etc. are deposited on the n-type semiconductor layer 14 to form an n-type electrode, and nickel (Ni), platinum (Pt), and gold ( Au) and the like are deposited to form a p-type electrode.

On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding, and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented.

10: nitride semiconductor element
11: base substrate
12: nitride nucleus growth layer
13: buffer layer
14: n-type semiconductor layer
14a: n-type cladding layer
15: active layer
16a: p-type cladding layer
16: p-type semiconductor layer

Claims (9)

In the method of manufacturing a nitride-based semiconductor device to form a nitride layer by supplying a Group V source and a plurality of Group III source,
And determining a total supply amount of the plurality of group III sources, and varyingly supplying at least one of the plurality of group III sources in a stepped or curved form to form the nitride layer. The method of claim 1, wherein the nitride layer,
A method of manufacturing a nitride based semiconductor device comprising at least one of a buffer layer, an n-type semiconductor layer, an n-type cladding layer, an active layer, a p-type cladding layer and a p-type semiconductor layer. The method of claim 1,
The plurality of group III sources contain at least two of B, Al, Ga, and In, and the group V source contains N. The method of claim 1,
The material of the nitride layer is Al _x In _y Ga _z B _w N (0≤x, y, z, w≤1, x + y + z + w = 1)
The manufacturing method of the nitride type semiconductor element characterized by the above-mentioned. A nitride-based semiconductor device comprising a plurality of nitride layers formed by supplying a group V source and a plurality of group III sources,
And at least one of the plurality of nitride layers defines a total supply amount of the plurality of group III sources, and is formed by variably supplying at least one of the plurality of group III sources in a stepped or curved form. Preparing a base substrate;
A buffer layer forming step of forming a buffer layer on the base substrate;
An n-type semiconductor layer forming step of forming an n-type semiconductor layer on the buffer layer;
An active layer forming step of forming an active layer on the n-type semiconductor layer;
A p-type semiconductor layer forming step of forming a p-type semiconductor layer on the active layer;
In at least one of the buffer layer forming step, the n-type semiconductor layer forming step, the active layer forming step and the p-type semiconductor layer forming step,
Supplying a Group V source and a plurality of Group III sources, determining a total supply amount of the plurality of Group III sources, and varyingly supplying at least one of the plurality of Group III sources in a stepped or curved manner to form a corresponding layer. Characterized in that the method for producing a nitride-based semiconductor device. The method of claim 6,
Forming an n-type cladding layer on the n-type semiconductor layer before forming the active layer; or
Forming a p-type cladding layer on the active layer before forming the p-type semiconductor layer;
At least one step of the more,
The forming of the n-type or p-type cladding layer may include supplying a Group V source and a plurality of Group III sources, determining a total supply amount of the plurality of Group III sources, and performing at least one of the plurality of Group III sources. A method of manufacturing a nitride-based semiconductor device, characterized in that formed by variable supply in the form of a die or curve. A base substrate;
A buffer layer formed on the base substrate;
An n-type semiconductor layer formed on the buffer layer;
An active layer formed on the n-type semiconductor layer;
It includes; a p-type semiconductor layer formed on the active layer,
At least one of the buffer layer, the n-type semiconductor layer, the active layer, and the p-type semiconductor layer supplies a Group V source and a plurality of Group III sources, and determines a total supply amount of the plurality of Group III sources, A nitride-based semiconductor device, wherein a layer is formed by variably supplying at least one group III source in a stepped or curved shape. The method of claim 7, wherein
An n-type cladding layer formed between the n-type semiconductor layer and the active layer; or
A p-type cladding layer formed between the active layer and the p-type semiconductor layer;
At least one of:
The n-type or p-type cladding layer supplies a Group V source and a plurality of Group III sources, determines a total supply amount of the plurality of Group III sources, and at least one of the plurality of Group III sources is stepped or curved. A nitride-based semiconductor device, characterized in that formed by variable supply.

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