KR20120037069A - Solar cell - Google Patents

Abstract

PURPOSE: A solar battery is provided to improve efficiency of the solar battery by forming a curved surface on an edge portion and top portion of a pyramid formed on one side of a crystalline semiconductor substrate. CONSTITUTION: A first amorphous silicon layer(121) is formed on a crystalline semiconductor substrate(110). A first electrode(141) is formed on the first amorphous silicon layer. A second amorphous silicon layer(172) is formed on the crystalline semiconductor substrate. A second electrode(142) is formed on the second amorphous silicon layer. An entrance face of the crystalline semiconductor substrate comprises a plurality of protrusion parts of a pyramid shape. A front protection part including amorphous silicon materials is formed on the protrusion parts of the pyramid shape.

Description

Solar cell {SOLAR CELL}

The present invention relates to a solar cell.

Recently, as energy resources such as oil and coal are expected to be depleted, interest in alternative energy to replace them is increasing, and solar cells that produce electric energy from solar energy are attracting attention.

Typical solar cells have a semiconductor portion that forms a p-n junction by different conductive types, such as p-type and n-type, and electrodes connected to semiconductor portions of different conductivity types, respectively.

When light is incident on the solar cell, a plurality of electron-hole pairs are generated in the semiconductor, and the generated electron-hole pairs are separated into electrons and holes charged by the photovoltaic effect, respectively, and the electrons are n-type. It moves toward the semiconductor portion and holes move toward the p-type semiconductor portion. The transferred electrons and holes are collected by the different electrodes connected to the p-type semiconductor portion and the n-type semiconductor portion, respectively, and the electrodes are connected by a wire to obtain electric power.

The present invention is to improve the efficiency of the solar cell by forming a curved surface in the corner portion and the top portion of the pyramid formed on one surface of the crystalline semiconductor substrate.

One example of a solar cell according to the present invention includes a crystalline semiconductor substrate of a first conductivity type; A first amorphous silicon layer formed on the crystalline semiconductor substrate, the first amorphous silicon layer having a second conductivity type opposite to the first conductivity type; A first electrode formed on the first amorphous silicon layer; A second amorphous silicon layer formed on the crystalline semiconductor substrate and having the same polarity as the first conductivity type; And a second electrode formed on the second amorphous silicon layer, wherein the incident surface of the crystalline semiconductor substrate includes a plurality of protrusions having a pyramid shape, and the corner portion of the inclined surface in the pyramid of the protrusion has a curved surface. Have

Here, the top portion of the pyramid in the pyramid of the protrusion may have a curved surface.

In addition, the diameter of the curved surface of the corner portion and the top portion of the inclined surface in the pyramid of the protrusion may be 5nm or more and 15nm or less.

In addition, the width of the bottom of the pyramid in the pyramid of the protrusion may be more than 5um 15um.

In addition, the angle between the inclined surface and the bottom surface in the pyramid of the protrusion may have an angle between 45 degrees and less than 54.7 degrees.

 Here, the inclined edge edge surface in the pyramid of the protrusion may be formed by performing anisotropic etching and then isotropic etching.

In addition, a plurality of protrusions may not be included on the opposite surface of the incident surface of the crystalline semiconductor substrate.

 In addition, the solar cell may further include a front surface protection portion that performs a passivation function on the pyramidal protrusion on the crystalline semiconductor substrate.

Here, the thickness of the front protective part may be uniform at the top of the inclined surface edge portion or the top portion of the pyramid having a curved surface.

In addition, the solar cell may further include a front surface electric field part of the first conductivity type that is more heavily doped than the crystalline semiconductor substrate on the front surface protection part.

In addition, the first amorphous silicon layer and the second amorphous silicon layer may be formed on opposite surfaces of the incident surface of the crystalline semiconductor substrate.

Further, an intrinsic silicon semiconductor layer is provided between the first amorphous silicon layer and / or the second amorphous silicon layer and the substrate, and the first amorphous silicon layer and / or the second amorphous silicon layer and the substrate further include an intrinsic silicon semiconductor layer. can do.

The solar cell according to the present invention has a curved surface at the corners and the top portion of the pyramid can make the front protective portion or the front electric field uniform on one surface of the crystalline semiconductor substrate has the effect of further increasing the efficiency of the solar cell.

1 is a partial perspective view of a solar cell according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the solar cell illustrated in FIG. 1 taken along line II-II.
3 is a view for explaining an example in which a plurality of protrusions having a pyramid shape according to the present invention has a curved surface at the corner portion of the inclined surface.
4 and 5 are diagrams for explaining the effect that the top portion of the pyramid and the corner portion of the inclined surface according to Figure 3 has a curved surface.
6 is a view for explaining an example having a curved surface in the valley portion as well as the top portion and the corner portion of the inclined surface in the plurality of protrusions having a pyramid shape according to the present invention.
7 to 9 illustrate an example of a method of forming a curved surface on the inclined surface, the top portion and the valley portion of the pyramid as in the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. On the contrary, when a part is "just above" another part, there is no other part in the middle. In addition, when a part is formed “overall” on another part, it means that it is not only formed on the entire surface (or front) of the other part but also on the edge part.

Next, a solar cell as an embodiment of the present invention will be described with reference to the accompanying drawings.

First, a solar cell according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a partial perspective view of a solar cell according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the solar cell illustrated in FIG. 1 taken along line II-II.

1 and 2, a solar cell 1 according to an exemplary embodiment of the present invention has an incident surface that is a surface of a crystalline semiconductor substrate 110 and a crystalline semiconductor substrate 110 to which light is incident. front surface portion 191 positioned above the front surface portion 191, front surface field (FSF) 171 positioned above the front surface protection portion 191, the front field portion 171 Anti-reflective unit 130, back protection unit 192, which is located on the surface of the crystalline semiconductor substrate 110 (hereinafter referred to as a 'rear surface') that is opposite to the incident surface without light incident, back protection A plurality of first amorphous silicon layers 121 positioned on the portion 192, and a plurality of second amorphous silicon layers disposed on the rear protective part 192 and spaced apart from the plurality of first amorphous silicon layers 121. field, BSF) 172, and a plurality of first electrodes 141 and a plurality of emitters respectively positioned on the plurality of emitter portions 121 2 may include an amorphous silicon layer 172, a plurality of second electrodes 142 respectively positioned above.

Meanwhile, FIGS. 1 and 2 here illustrate an example in which the solar cell 1 according to the present invention is disposed with the front electric field part 171, the second amorphous silicon layer 172, and the rear protection part 192. However, the front electric field unit 171, the rear electric field unit 172, and the rear protection unit 192 may be omitted.

However, when the front electric field unit 171, the second amorphous silicon layer 172, and the rear protection unit 192 are formed, the photoelectric efficiency of the solar cell may be further improved. Hereinafter, the front electric field unit 171, As an example, the second amorphous silicon layer 172 and the rear protective part 192 are included in the solar cell 1.

In addition, the first amorphous silicon layer 121 may be represented by the emitter portion 121, and the second amorphous silicon layer 172 may be represented by the rear electric field portion 172. Hereinafter, the first amorphous silicon layer 121 is represented by the emitter portion 121, and the second amorphous silicon layer 172 is represented by the rear electric field portion 172.

The crystalline semiconductor substrate 110 is a crystalline semiconductor substrate made of silicon of a first conductivity type, for example, an n-type conductivity. At this time, the silicon is crystalline silicon such as monocrystalline silicon or polycrystalline silicon. When the crystalline semiconductor substrate 110 has an n-type conductivity type, impurities of pentavalent elements such as phosphorus (P), arsenic (As), antimony (Sb), and the like are doped into the crystalline semiconductor substrate 110. Alternatively, the crystalline semiconductor substrate 110 may be of a p-type conductivity type or may be made of a semiconductor material other than silicon. When the crystalline semiconductor substrate 110 has a p-type conductivity type, the crystalline semiconductor substrate 110 may include impurities of trivalent elements such as boron (B), gallium (Ga), and indium (In). Doped).

The crystalline semiconductor substrate 110 has a textured surface where the incidence surface is textured to be an uneven surface. For convenience, in FIG. 1, only the edge portion of the crystalline semiconductor substrate 110 is shown as a texturing surface, and the front protection portion 191, the front electric field portion 171, and the anti-reflection portion 130, which are positioned thereon, also have irregular edge portions thereof. It is shown by the side. However, substantially the entire front surface of the crystalline semiconductor substrate 110 has a texturing surface, which causes the front surface protection portion 191, the front surface field portion 171, and the anti-reflection portion () which are located on the front surface of the crystalline semiconductor substrate 110. 130 also has an uneven surface.

The uneven surface positioned on the incident surface of the crystalline semiconductor substrate 110 includes a plurality of protrusions having a pyramid shape, and the corner portion of the inclined surface in the pyramid of the protrusion has a curved surface. The description that the inclined edge portion of the protrusion having a pyramid shape as described above will be described in more detail with reference to FIG. 3 to be described later.

1 and 2, the crystalline semiconductor substrate 110 may have a texturing surface on the rear surface as well as the front surface. In this case, the rear protective part 192, the plurality of emitter parts 121, the rear electric field part 172, and the first and second electrodes 141 and 142 located on the rear surface of the crystalline semiconductor substrate 110 are also uneven. Has a face.

However, as shown in FIGS. 1 and 2, when the back surface of the crystalline semiconductor substrate 110 does not include a plurality of protrusions because the opposite surface of the incident surface is not textured in the crystalline semiconductor substrate 110. The rear protection unit 192, the emitter unit 121 and the rear electric field unit 172 on the rear of the 110 can be formed in a more uniform and stable close contact, the emitter unit 121 and the rear electric field unit 172 ) And the contact resistance between the first and second electrodes 141 and 142 can be reduced.

That is, when the uneven surface is not formed on the rear surface of the crystalline semiconductor substrate 110 and thus does not include a plurality of protrusions, the rear protection portion 192 and the plurality of emitter portions 121 that are deposited on the rear surface of the crystalline semiconductor substrate 110. ) And the rear electric field 172 may be formed to have a more uniform thickness.

In addition, when the uneven surface is not formed on the rear surface of the crystalline semiconductor substrate 110, the emitter portion 121 and the rear electric field portion 172 also do not form the uneven surface, so that the emitter portion 121 and the rear electric field portion ( Since the first electrode 141 and the second electrode 142 disposed on the rear side of the 172 may also be more stably in close contact with the emitter unit 121 and the rear electric field unit 172, the emitter unit 121 and the rear electrode may be more stable. The contact resistance between the meter 172 and the first electrode 141 and the second electrode 142 may be further reduced.

Next, the front protective part 191 disposed on the front surface of the crystalline semiconductor substrate 110 may include any one of an intrinsic amorphous silicon (a-Si) film, a silicon nitride film (SiNx), and a silicon oxide film (SiOx). Can be formed.

The defects such as dangling bonds mainly present on and near the surface of the crystalline semiconductor substrate 110 are changed into stable bonds, and the charges moved toward the surface of the crystalline semiconductor substrate 110 by the defect disappear. A passivation function is performed that reduces the amount of charge, thereby reducing the amount of charge lost on or near the surface of the crystalline semiconductor substrate 110 by the defect.

In general, since defects are mainly present on or near the surface of the crystalline semiconductor substrate 110, in the case of the embodiment, the front protection part 191 is directly in contact with the surface of the crystalline semiconductor substrate 110, thereby further improving the passivation function. As a result, the amount of charge loss further increases.

In the present embodiment, the front protection portion 191 may have a thickness of about 1 nm to 30 nm.

If the thickness of the front protection part 191 is about 1 nm or more, the front protection part 191 is uniformly applied to the entire surface of the crystalline semiconductor substrate 110, and thus, the passivation function may be satisfactorily performed. The amount of light absorbed in 191 may be reduced to increase the amount of light incident into the crystalline semiconductor substrate 110.

The front electric field part 171 positioned on the front protection part 191 is an impurity part in which impurities of the same conductivity type (eg, n-type) as the crystalline semiconductor substrate 110 are contained at a higher concentration than the crystalline semiconductor substrate 110. In this embodiment, the impurity doping concentration of the front surface electric field portion 171 may be about 10 ¹⁰ to 10 ²¹ atoms / cm 3.

The front field unit 171 of the present exemplary embodiment may include any one of amorphous silicon, amorphous silicon oxide (a-SiOx), and amorphous silicon silicon (a-SiC).

Due to the difference in the impurity concentration between the crystalline semiconductor substrate 110 and the front electric field unit 171, a potential barrier is formed to have an electric field effect that prevents charge (eg, hole) movement toward the front surface of the crystalline semiconductor substrate 110.

Therefore, a front field effect is obtained in which holes moving toward the front surface of the crystalline semiconductor substrate 110 are returned to the rear surface of the crystalline semiconductor substrate 110 by the potential barrier, whereby the output amount of charge output to the external device is obtained. The amount of charge lost by recombination or defects in the front surface of the crystalline semiconductor substrate 110 is decreased.

In general, the energy band gaps of amorphous silicon oxide (a-SiOx) and amorphous silicon silicon (a-SiC) are about 2.1 and about 2.8, respectively, and the energy band gap is an energy band gap of about 1.7 to 1.9. Wider than amorphous silicon with Therefore, when the front field unit 171 is made of amorphous silicon oxide (a-SiOx) or amorphous silicon silicon (a-SiC), the wavelength region of light absorbed by the front field unit 171 is reduced, thereby The amount of light absorbed by the front field unit 171 itself is also reduced, so that the amount of light incident toward the crystalline semiconductor substrate 110 is further increased.

In this embodiment, the front surface field portion 171 is changed continuously or discontinuously within the range of about 10 ¹⁰ to 10 ²¹ atoms / cm 3 in the thickness direction, or substantially within the range of about 10 ¹⁶ to 10 ²¹ atoms / cm 3. It has a uniform impurity doping concentration.

When the impurity doping concentration of the front electric field unit 171 varies within the range of 10 ¹⁰ to 10 ²¹ atoms / cm 3 along the thickness direction, a part of the front electric field unit 171 has the same passivation function as the front protective unit 191. Perform.

At this time, the doping concentration of the impurity is changed from the portion of the front field portion 171 in contact with the front protection portion 191 to the portion of the front field portion 171 in contact with the anti-reflection portion 130.

Therefore, the impurity doping concentration decreases as the adjoining front protection part 191 decreases. On the contrary, the impurity doping concentration increases as adjoining the anti-reflection part 130 increases. The portion located at the minimum distance from the surface of the substrate 110 to the front electric field portion 171 is the lowest doping concentration portion having the lowest impurity doping concentration and is in contact with the antireflection portion 130, that is, the crystalline semiconductor substrate. The portion located at the minimum distance from the surface of the 110 to the anti-reflection portion 130 is the highest doping concentration portion having the highest impurity doping concentration. In this case, it can be seen that the two minimum distances are measured from the same portion of the crystalline semiconductor substrate 110.

Thus, the lowest doping concentration portion has an impurity concentration of about 10 ¹⁰ atoms / cm 3 and the highest doping concentration portion has an impurity concentration of about 10 ²¹ atoms / cm 3.

In this case, since the front electric field unit 171 performs the passivation function as well as the front electric field function, the front electric field unit 171 should have a thicker thickness than the front electric field function, and conversely, the thickness of the front protective unit 191 may be further reduced. In this case, the front protection part 191 may have a thickness of about 1 nm to 10 nm, and the front electric field part 171 may have a thickness of about 3 nm to 30 nm.

 If the thickness of the front protection part 191 is 1 nm or more, the front protection part 191 is uniformly applied to the rear surface of the crystalline semiconductor substrate 110, so that the passivation efficiency can be obtained more, and the thickness of the front protection part 191 is 10. When the thickness is less than or equal to nm, since the device performs a passivation function without absorbing light, the amount of light incident on the crystalline semiconductor substrate 110 may be further increased.

If the thickness of the front electric field unit 171 is 3 nm or more, a portion of the front electric field unit 171 generates a front electric field intensity capable of performing a stable front electric field function even though a part of the front electric field unit 171 performs the passivation function, and the crystalline semiconductor substrate 110 And the front electric field 171 are formed between the front electric field unit 171 to form a front electric field of normal size irrespective of the influence of the front protective unit 191 adversely affecting the front electric field strength acting on the crystalline semiconductor substrate 110. When the thickness of the front electric field unit 171 is 30 nm or less, the front electric field function may be performed without absorbing light in itself, and thus the amount of light incident on the crystalline semiconductor substrate 110 may be further increased. have.

In an alternative example, when the front field portion 171 has a substantially uniform impurity doping concentration, the impurity concentration of the front field portion 171 is substantially uniform regardless of the thickness change.

In this case, the front electric field unit 171 substantially performs the front electric field function for substantially the front electric field effect rather than the passivation function, so that the front electric field function using the impurity concentration difference with the crystalline semiconductor substrate 110 can be smoothly performed. It must have an impurity concentration. Therefore, when the front electric field unit 171 mainly performs the front electric field function, the front electric field unit 171 has a higher impurity concentration than when a part of the front electric field unit 171 performs the passivation function. In addition, the front electric field part 171 may have a higher impurity doping concentration than the crystalline semiconductor substrate 110. In this example, the front surface field portion 171 has a substantially uniform impurity doping concentration in the range of about 10 ¹⁶ to 10 ²¹ atoms / cm 3.

Compared with a portion of the front electric field unit 171 which performs not only the front electric field function but also the passivation function, in this case, the front electric field unit 171 mainly performs the front electric field function rather than the passivation function. The front protection part 191 disposed below the 171 has a thicker thickness to perform a stable passivation function, and the front electric field part 171 may have a thinner thickness because only the front electric field function is performed. For this reason, the front protection part 191 may have a thickness of about 2 nm to 20 nm, and the front electric field part 171 may have a thickness of about 1 nm to 20 nm.

If the thickness of the front protection part 191 is about 2 nm or more, the front protection part 191 alone can stably remove defects on and around the surface of the crystalline semiconductor substrate 110, so that the passivation function can be better performed. In addition, when the thickness of the front protective part 191 is about 20 nm or less, since the passivation function is performed without light absorption by itself, the amount of light incident on the crystalline semiconductor substrate 110 may be further increased.

In addition, when the thickness of the front electric field part 171 is about 1 nm or more, it is located between the crystalline semiconductor substrate 110 and the front electric field part 171 to adversely affect the front electric field strength acting on the crystalline semiconductor substrate 110. Irrespective of the influence of the front protective part 191, the front electric field of a normal size can be formed stably to perform the front electric field function stably. If the thickness of the front electric field 171 is about 20 nm or less, no light is absorbed by itself. Since the front surface electric field function is performed, the amount of light incident on the crystalline semiconductor substrate 110 may be further increased.

The anti-reflection unit 130 located on the front electric field unit 171 reduces the reflectivity of light incident on the solar cell 1 and increases the selectivity of a specific wavelength region, thereby increasing the efficiency of the solar cell 1. The anti-reflection portion 130 is made of a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like. In the present embodiment, the anti-reflection unit 130 may have a single layer structure but may have a multilayered layer structure such as a double layer, and may be omitted as necessary.

The rear protective part 192 located directly on the rear side of the crystalline semiconductor substrate 110 performs the passivation function in the same manner as the front protective part 191, so that the charges moved toward the rear side of the crystalline semiconductor substrate 110 disappear by the defect. Decreases

The rear protection unit 192 may be formed to include amorphous silicon and the like, similar to the front protection unit 191.

The rear protection unit 192 may have a thickness such that charges moved toward the rear surface of the crystalline semiconductor substrate 110 may move to the plurality of rear electric field units 172 or the plurality of emitter units 121 through the rear protection unit 192. Has In this embodiment, one example of the thickness of the rear protective portion 192 may be about 1 to 10 nm.

If the thickness of the rear protective part 192 is about 1 nm or more, the rear protective part 192 is uniformly applied to the rear surface of the crystalline semiconductor substrate 110, so that a passivation effect may be further obtained. The amount of light that passes through the rear protection unit 192 may be reduced to increase the amount of light that is re-incident into the crystalline semiconductor substrate 110.

The plurality of backside electric fields 172 are regions in which impurities of the same conductivity type as those of the crystalline semiconductor substrate 110 are more heavily doped than the crystalline semiconductor substrate 110. For example, the plurality of backside electric fields 172 may be n + impurity regions.

The plurality of rear electric field parts 172 are spaced apart from each other on the rear protection part 192 and extend in parallel to each other. In the present embodiment, the plurality of backside electric fields 172 are made of an amorphous semiconductor such as amorphous silicon (a-Si).

Similar to the front electric field 171, the rear electric field 172 is a rear electric field that is a direction of movement of electrons by a potential barrier due to a difference in impurity concentration between the crystalline semiconductor substrate 110 and the rear electric field 172. Interfering with hole movement toward 172, while facilitating charge (e.g., electron) movement toward backside field 172. Accordingly, the amount of electric charge lost due to the recombination of electrons and holes in the rear electric field 172 and the vicinity of the first and second electrodes 141 and 142 and accelerated electron movement to the rear electric field 172. Increase the amount of electron transfer.

Each back surface field portion 172 may have a thickness of about 10 nm to 25 nm. If the thickness of the rear electric field 172 is greater than or equal to about 10 nm, a potential barrier that prevents the movement of holes can be better formed, thereby further reducing the charge loss. If the thickness of the rear electric field 172 is less than about 25 nm, the rear electric field 172 may be formed within the rear electric field 172. The amount of light absorbed may be reduced to increase the amount of light re-incident into the crystalline semiconductor substrate 110.

The plurality of emitter parts 121 are spaced apart from the plurality of rear electric field parts 172 on the rear surface of the crystalline semiconductor substrate 110 and extend in parallel with the plurality of rear electric field parts 172.

As shown in FIGS. 1 and 2, the rear electric field part 172 and the emitter part 121 are alternately positioned on the crystalline semiconductor substrate 110.

Each emitter portion 121 is formed on the rear surface of the crystalline semiconductor substrate 110 and has a second conductivity type, for example, a p-type conductivity type, which is opposite to the conductivity type of the crystalline semiconductor substrate 110. Semiconductor substrate 110 and other semiconductors, for example, amorphous silicon. Accordingly, the emitter unit 121 forms a hetero junction as well as a p-n junction with the crystalline semiconductor substrate 110.

Electrons, which are charges generated by light incident on the crystalline semiconductor substrate 110 due to a built-in potential difference due to a pn junction formed between the crystalline semiconductor substrate 110 and the plurality of emitter portions 121. Hole pairs are separated into electrons and holes, electrons move toward n-type and holes move toward p-type. Therefore, when the crystalline semiconductor substrate 110 is n-type and the plurality of emitter portions 121 are p-type, the separated holes move through the rear protective portion 192 toward each emitter portion 121 and the separated electrons It penetrates the rear protective part 192 and moves toward the plurality of rear electric field parts 172 having a higher impurity concentration than the crystalline semiconductor substrate 110.

Since each emitter portion 121 forms a pn junction with the crystalline semiconductor substrate 110, unlike the present embodiment, when the crystalline semiconductor substrate 110 has a p-type conductivity type, the emitter portion 121 is n-type. It has a conductivity type of. In this case, the separated electrons move toward the plurality of emitter units 121 through the rear protection unit 192, and the separated holes move toward the plurality of rear electric fields 172 through the rear protection unit 192.

When the emitter portion 121 has a p-type conductivity type The emitter portion 121 may be doped with an impurity of a trivalent element. On the contrary, when the emitter portion 121 has an n-type conductivity type. The emitter unit 121 may be doped with impurities of a pentavalent element.

The plurality of emitter units 121 may perform a passivation function together with the rear protection unit 192, and in this case, the amount of electric charges dissipated in the rear surface of the crystalline semiconductor substrate 110 due to defects decreases, thereby reducing the amount of charges. 11) improves the efficiency.

Each emitter portion 121 may have a thickness of about 5 nm to 15 nm. If the thickness of the emitter portion 121 is about 5 nm or more, the pn junction may be better formed. If the emitter portion 121 is about 15 nm or less, the amount of light absorbed in the emitter portion 121 may be reduced to re-introduce the crystalline semiconductor substrate 110. It is possible to increase the amount of incident light.

In the present embodiment, due to the rear protection portion 192 of the intrinsic semiconductor material (intrinsic a-Si), which is located under the plurality of emitter portions 121 and the plurality of rear electric field portions 172, and has little or no impurities, The plurality of emitter portions 121 and the plurality of backside electric fields 172 are disposed on the crystalline semiconductor substrate 110 made of a crystalline semiconductor material, rather than when the plurality of emitters 121 and the plurality of backside electric fields 172 are positioned. When formed, the crystallization phenomenon is reduced. As a result, the characteristics of the plurality of emitter portions 121 and the plurality of rear electric field portions 172 positioned on the amorphous silicon are improved.

The plurality of first electrodes 141 positioned on the plurality of emitter portions 121 extend along the plurality of emitter portions 121 and are electrically connected to the plurality of emitter portions 121.

The plurality of first electrodes 141 positioned on the plurality of emitter portions 121 extend along the plurality of emitter portions 121 and are electrically and physically connected to the plurality of emitter portions 121.

Each first electrode 141 collects electric charges, for example, holes moved toward the corresponding emitter part 121.

The plurality of second electrodes 142 positioned on the plurality of rear electric field parts 172 extend along the plurality of rear electric field parts 172, and are electrically and physically connected to the plurality of rear electric field parts 172. have.

Each second electrode 142 collects charge, for example, electrons, which move toward the corresponding backside field portion 172.

1 and 2, each of the first and second electrodes 141 and 142 has a plane shape different from that of the emitter part 121 and the rear electric field part 172 located below, but has the same plane shape. Can have As the contact area between the emitter portion 121 and the rear electric field portion 172 and the first and second electrodes 141 and 142 increases, the contact resistance decreases, thereby causing charges to the first and second electrodes 141 and 142. Transmission efficiency is increased.

The first and second electrodes 141 and 142 may include nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), and titanium. It may be made of at least one conductive material selected from the group consisting of (Ti), gold (Au), and combinations thereof, but may be made of other conductive metal materials other than the above. As such, since the plurality of first and second electrodes 141 and 142 are made of a metal material, light passing through the crystalline semiconductor substrate 110 is reflected toward the crystalline semiconductor substrate 110.

In the solar cell 1 according to the present exemplary embodiment having the structure as described above, the plurality of first electrodes 141 and the plurality of second electrodes 142 are positioned on the rear surface of the crystalline semiconductor substrate 110 to which light is not incident. A solar cell in which the crystalline semiconductor substrate 110 and the plurality of emitter portions 121 are made of different types of semiconductors, the operation of which is as follows.

When light is irradiated onto the solar cell 1 and sequentially passes through the anti-reflection unit 130, the front electric field unit 171, and the front protection unit 191 and enters the crystalline semiconductor substrate 110, the crystalline semiconductor is formed by light energy. Electron-hole pairs are generated in the substrate 110. At this time, since the surface of the crystalline semiconductor substrate 110 is a texturing surface, the light reflectivity on the entire surface of the crystalline semiconductor substrate 110 is reduced, and incident and reflection operations are performed on the texturing surface to increase light absorption. The efficiency of the is improved. In addition, the reflection loss of the light incident on the crystalline semiconductor substrate 110 by the anti-reflection unit 130 is reduced, so that the amount of light incident on the crystalline semiconductor substrate 110 is further increased.

These electron-hole pairs are separated from each other by the pn junction of the crystalline semiconductor substrate 110 and the emitter portion 121 so that the holes move toward the emitter portion 121 having a p-type conductivity type, and the electrons are n-type conductivity. It moves toward the rear electric field 172 having a type, and is transferred to the first electrode 141 and the second electrode 142, respectively, and collected by the first and second electrodes 141 and 142. When the first electrode 141 and the second electrode 142 are connected with a conductive wire, a current flows, which is used as power from the outside.

In this case, since the protection parts 192 and 191 are positioned not only on the rear surface of the crystalline semiconductor substrate 110 but also on the front surface of the crystalline semiconductor substrate 110, defects existing in the front and rear surfaces of the crystalline semiconductor substrate 110 and the vicinity thereof. The amount of charge loss due to this is reduced, and the efficiency of the solar cell 1 is improved. In this case, since not only the rear protective part 192 but also the front protective part 191 directly contact the surface of the crystalline semiconductor substrate 110 having a high frequency of defects, the passivation effect is further improved.

In addition, due to the electric field parts 171 and 172 disposed on the front and rear surfaces of the crystalline semiconductor substrate 110, the amount of charge loss is further reduced, thereby further improving the efficiency of the solar cell 1.

Hereinafter, a description will be given of a curved surface of the edge portion EP1 of the inclined surface SP1 of the protrusion in the plurality of protrusions having the shape of a pyramid P1 formed on the incident surface of the crystalline semiconductor substrate 110.

As such, when the inclined surface SP1 of the protruding portion has a curved surface, the front protective portion 191 or the front electric field portion 171 formed on the incident surface of the crystalline semiconductor substrate 110 has the edge of the inclined surface SP1. It can be formed more uniformly in the portion EP1, so as to further enhance the effect of the passivation, in which charges (eg, electrons) are dissipated by dangling bonds near the incidence plane of the crystalline semiconductor substrate 110, or It is possible to further improve the electric field effect that prevents and electrons from being recombined and lost.

Therefore, the passivation effect and the electric field effect of the front protective part 191 and the front electric field part 171 can be further improved near the incidence plane of the crystalline semiconductor substrate 110, thereby further improving the photoelectric efficiency of the solar cell. have.

3 is a view for explaining an example in which a plurality of protrusions having a pyramid shape according to the present invention has a curved surface at the corner portion of the inclined surface.

In FIG. 3, (a) illustrates a plurality of protrusions having a pyramid P1 shape on the incident surface of the crystalline semiconductor substrate 110, and (b) illustrates a three-dimensional shape of the unit pyramid P1. (c) shows the cross section of the pyramid P1, (d) is the shape which looked at the unit pyramid P1 from the top.

As shown in (a) of FIG. 3, the crystalline semiconductor substrate 110 according to the present invention is textured on the front surface of the incident surface to form a plurality of protrusions, and the texturing process is performed on the rear surface of the incident surface. If not, a plurality of protrusions may not be formed.

As shown in FIG. 3B, the protrusion has a pyramid P1 shape, and the corner portion EP1 formed on the inclined surface SP1 of the pyramid P1 has a curved surface.

In addition, as shown in (b) and (c) of FIG. 3, the top portion TP1 of the pyramid P1 in the pyramid P1 of the protrusion may also have a curved shape.

As such, the front surface protection part 191 or the front electric field portion formed on the incidence surface of the crystalline semiconductor substrate 110 is formed by forming the inclined surface SP1 and the corner portion EP1 and the top portion TP1 of the protrusion. 171 may be formed more uniformly at the corner portion EP1 or the top portion TP1 of the inclined surface SP1.

Here, in the pyramid P1 of the protrusion, the diameters R1 and R2 of the corner portion EP1 of the inclined surface SP1 and the curved surface of the top portion TP1 may be 5 nm or more and 15 nm or less.

Here, the diameter R1 of the curved surface may be 5 nm or more so that the front protective portion 191 or the front electric field portion 171 may be uniformly formed at the edge portion EP1 or the top portion TP1 of the inclined surface SP1. To do this.

In addition, the diameter (R1, R2) of the curved surface to be 15nm or less to minimize the reflection to the incident light. That is, when the diameters R1 and R2 of the curved surface are 15 nm or more, the uniformity of the front protective part 191 or the front electric field part 171 formed on the upper part of the protrusion may be further improved, but the reflectivity to light may be further increased. Can be.

Here, the width WP of the bottom surface BP of the pyramid P1 in the pyramid P1 of the protrusion may be formed in a range of 5 μm or more and 15 μm or less. The size of the pyramid P1 becomes larger as the width of the bottom surface BP increases due to the characteristics of crystalline silicon, and decreases as the width WP of the bottom surface BP decreases.

Therefore, the width WP of the bottom surface BP is 5 μm or more and 15 μm or less, thereby optimally securing the size of the pyramid P1 to secure an optimal optical path for incident light, thereby improving photoelectric efficiency. . That is, the incident light is incident and reflected several times through the inclined surfaces SP1 of the plurality of pyramids P1. In this case, the light path of the incident light is long, so that a greater amount of light may be incident into the crystalline semiconductor substrate 110, thereby improving photoelectric efficiency.

In addition, as shown in (b) of FIG. 3, the angle θ between the inclined surface SP1 and the bottom surface BP in the pyramid P1 of the protrusion may have an angle between 45 ° and less than 54.7 °. have.

When the surface of the crystalline semiconductor substrate 110 is textured by a general method, the angle θ between the inclined surface SP1 and the bottom surface BP of the pyramid P1 is 54.7 °.

However, in the present invention, the isotropic etching is performed once more in addition to the anisotropic etching, which is a texturing method that is generally performed. By doing in this way, the angle (theta) between the inclined surface SP1 and the base surface BP of the pyramid P1 can be formed smaller than 54.7 degrees.

Here, the angle θ between the inclined surface SP1 and the bottom surface BP is 45 ° or more to ensure the inclination of the inclined surface SP1 of the pyramid P1 to a minimum, so that the incidence surface of the crystalline semiconductor substrate 110 is reduced. This is to minimize reflectivity. In addition, the angle θ between the inclined surface SP1 and the bottom surface BP is less than 54.7 ° so that the inclined surface SP1 of the pyramid P1 is formed more smoothly, so that the upper part of the protrusion of the pyramid P1 shape is formed. The front protection part 191 or the front electric field part 171 to be formed may be more uniformly formed.

4 and 5 are diagrams for explaining the effect that the top portion of the pyramid and the corner portion of the inclined surface according to Figure 3 has a curved surface.

As shown in FIG. 4A, when the inclined surface SP1 corner portion EP1 and the top portion TP1 of the pyramid P1 have curved surfaces, as shown in (b), the pyramid P1 It can be seen that the front protective part 191 formed on the upper surface of the upper surface of the upper surface 1) is uniformly formed at the corner portion EP1 and the top portion TP1 of the inclined surface SP1 of the pyramid P1.

However, as shown in FIG. 5A, when the inclined surface SP2 and the corner portion EP2 and the top portion TP2 of the pyramid P1 are formed to have an angle without a curved surface, in (b) As shown, it can be seen that the front protective portion 191 formed on the upper portion of the pyramid P1 is not uniformly formed at the corner portion EP1 and the top portion TP1 of the inclined surface SP1 of the pyramid P1. have.

As described above, the curved surface is not formed at the edge portion EP2 and the top portion TP2 of the inclined surface SP2 of the pyramid P2 at the upper surface of the crystalline semiconductor substrate 110, so that the front protection part 191 is not uniformly formed. Otherwise, the passivation effect may be relatively reduced at the corner portion EP2 and the top portion TP2 of the inclined surface SP2 of the pyramid P2.

That is, in order for the passivation effect by the front protective part 191 to be exerted as desired, the front protective part 191 should be formed to a minimum thickness or more, and the corner portion EP2 or the top of the inclined surface SP2 of the pyramid P2 may be formed. When the portion TP2 is formed to be angular, the portion formed to be angular is not secured to the minimum thickness, so that the passivation effect can be reduced.

Therefore, in such a case, the charge may be dissipated due to the reduction of the passivation effect at the edge portion EP2 and the top portion TP2 of the inclined surface SP2 of the pyramid P2, as shown in FIGS. When the front electric field unit 171 is further formed on the upper portion of the protection unit 191, the electric field effect is also not uniform, so that electrons and holes are formed at the corner portion EP2 and the top portion TP2 of the inclined surface SP2 of the pyramid P2. The probability of recombination is higher.

Of course, in order to secure the passivation effect at the corner portion EP2 and the top portion TP2 of the inclined surface SP2 of the pyramid P2, the front protective portion 191 is added to the entire upper portion of the pyramid P2 in a larger amount. In this case, the front protection part 191 may be excessively thick in the valley portion between the plurality of pyramids P1.

As such, when the front protection portion 191 is excessively thick in the valley portion between the pyramids P2, the amount of light absorbed by the front protection portion 191 located above the valley portion is increased, so that the crystalline semiconductor substrate ( The amount of light absorbed by 110 is reduced.

As such, when the amount of light absorbed in the valley portion of the crystalline semiconductor substrate 110 decreases, the photoelectric effect of the solar cell may be reduced.

However, as shown in the present invention, when curved surfaces are formed at the corner portion EP1 and the top portion TP1 of the inclined surface SP1 of the pyramid P1, the front protective portion 191 is excessive in the valley portion of the pyramid P1. In order not to be thickly formed, the front protection part 191 may be uniformly formed at the edge portion EP1 and the top portion TP1 of the inclined surface SP1 of the pyramid P1, so that the above-described passivation effect or electric field effect is achieved. Since it can be made uniform, there is an effect that can further improve the photoelectric efficiency of the solar cell.

Up to now, only the case where the top portion TP1 of the pyramid P1 and the corner portion EP1 of the inclined surface SP1 have a curved surface has been described as an example, but as shown in FIG. Not only the top portion TP1 and the corner portion EP1 of the inclined surface SP1, but also the lower portion of the pyramid P1, that is, the valley portion VP1 between the plurality of pyramids P1, may have a curved surface.

In this case, when the front protective portion 191 is formed on the upper portion of the pyramid (P1), as shown in Figure 6 (b), the top portion TP1 and the inclined surface SP1 of the pyramid (P1) Not only the corner portion EP1, but also the lower portion of the pyramid P1, the front protection part 191 may be uniformly formed, thereby further improving the photoelectric efficiency of the solar cell.

Hereinafter, as shown in FIG. 6, an example of a method of forming a curved surface in the valley portion VP1 of the plurality of pyramids P1, as well as the corner portion EP1 and the top portion TP1 of the inclined surface SP1 of the pyramid P1. Explain.

7 to 9 illustrate an example of a method of forming a curved surface on the inclined surface, the top portion and the valley portion of the pyramid as in the present invention.

First, as in step S1 of FIG. 7, the crystalline semiconductor substrate 110 is prepared, and one surface of the crystalline semiconductor substrate 110 is anisotropically etched. Such anisotropic etching may be performed by wet etching, for example. When anisotropic etching is performed as described above, one surface of the crystalline semiconductor substrate 110 may be textured to form a plurality of protrusions, which are uneven surfaces, as in step S2.

Here, when the wet etching is performed, the material and the etching time of the etching solution may be variously determined.

In this case, as shown in FIG. 8A, the angle θ1 formed between the inclined surface SP2 and the bottom surface BP of the protrusion is fixed at 54.7 ° by the characteristics of the crystalline semiconductor substrate 110. Then, as shown in (b) of FIG. 8, the corner portion EP2 of the protrusion slope SP2 is formed at an angle without a curved surface.

After the step S2, isotropic etching is further performed on one surface of the crystalline semiconductor substrate 110 on which the anisotropic etching is performed. Such isotropic etching may also be performed by wet etching, and the material and the etching time of the etching solution may be variously determined.

When such anisotropic etching is performed, as shown in FIG. 9A, the edge portion EP1 of the inclined surface SP1 of the pyramid P1 is gradually etched to form the top portion TP1 of the pyramid P1. The height is gradually lowered, and the angle between the inclined surface SP1 and the bottom surface BP of the pyramid P1 is reduced to 54.7 degrees or less. At this time, by adjusting the time of the isotropic etching can be such that the angle between the base (BP) has an angle between 45 ° and less than 54.7 °.

By this anisotropic etching, as shown in (a) and (b) of FIG. 9, the top portion TP1 of the pyramid P1 and the corner portion EP1 of the inclined surface SP1 have a curved surface.

In this case, the diameter R1 of the curved surface of the top portion TP1 of the pyramid P1 and the corner portion EP1 of the inclined surface SP1 may also be adjusted to 5 nm or more and 15 nm or less by adjusting the isotropic etching time. .

Thereafter, as in step S4, the front protection part 191 may be deposited on one surface of the crystalline semiconductor substrate 110 on which the anisotropic etching is performed, and then the anti-reflection part may be formed on the top protection part 191. will be.

Alternatively, after depositing the front protective part 191, the front electric field part 171 may be formed by depositing, and the anti-reflective part may be formed on the front electric field part 171.

As described above, the solar cell according to the present invention forms a curved surface at the corner portion EP1 and the top portion TP1 of the pyramid P1 so that the passivation effect of the front protective part 191 or the electric field effect of the front electric field part 171 are obtained. Since it can be made more uniform, there is an effect of further increasing the efficiency of the solar cell.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (12)

A crystalline semiconductor substrate of a first conductivity type;
A first amorphous silicon layer formed on the crystalline semiconductor substrate and having a second conductivity type opposite to the first conductivity type;
A first electrode formed on the first amorphous silicon layer;
A second amorphous silicon layer formed on the crystalline semiconductor substrate and having the same polarity as the first conductivity type;
And a second electrode formed on the second amorphous silicon layer.
The incident surface of the crystalline semiconductor substrate includes a plurality of protrusions having a pyramid shape,
And a corner portion of the inclined surface in the pyramid of the protrusion has a curved surface. The method of claim 1,
And wherein the top portion of the pyramid in the pyramid of the protrusion has a curved surface. The method of claim 2,
In the pyramid of the protrusion, the diameter of the corner portion of the inclined surface and the top surface of the solar cell, characterized in that 5nm or more and 15nm or less. The method of claim 1,
The width of the bottom surface of the pyramid in the pyramid of the protrusion is 5um or more, characterized in that less than 15um. The method of claim 1,
The angle between the inclined surface and the bottom surface in the pyramid of the protrusion has an angle between 45 ° or more and less than 54.7 °. The method of claim 1,
The inclined surface edge curved surface of the pyramid of the protrusion is formed by performing anisotropic etching, and then isotropic etching. The method of claim 1,
The solar cell of claim 1, wherein the plurality of protrusions is not included on an opposite surface of the incident surface of the crystalline semiconductor substrate. The method of claim 1,
The solar cell
And a front surface protection part including an amorphous silicon material is formed on the pyramid-shaped protrusions on the crystalline semiconductor substrate. The method of claim 8,
The thickness of the front protective portion is a solar cell, characterized in that uniform in the upper portion of the inclined surface edge portion or the top portion of the pyramid having the curved surface. The method of claim 8,
The solar cell
And an upper surface electric field portion of a first conductivity type doped at a higher concentration than the crystalline semiconductor substrate. The method of claim 1,
And the first amorphous silicon layer and the second amorphous silicon layer are formed on opposite surfaces of the incident surface of the crystalline semiconductor substrate. The method of claim 1,
An intrinsic silicon semiconductor layer is provided between the first amorphous silicon layer and / or the second amorphous silicon layer and the substrate, further comprising an intrinsic silicon semiconductor layer between the first amorphous silicon layer and / or the second amorphous silicon layer and the substrate. Solar cell comprising a.

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