KR20120036431A - Reapter - Google Patents
Reapter Download PDFInfo
- Publication number
- KR20120036431A KR20120036431A KR1020100098096A KR20100098096A KR20120036431A KR 20120036431 A KR20120036431 A KR 20120036431A KR 1020100098096 A KR1020100098096 A KR 1020100098096A KR 20100098096 A KR20100098096 A KR 20100098096A KR 20120036431 A KR20120036431 A KR 20120036431A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- enable signal
- address
- delay
- output
- Prior art date
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2272—Latency related aspects
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The repeater may include an enable signal delay unit configured to delay the enable signal in response to the test signal to generate a delay enable signal; And an address output unit configured to amplify an input address and output the output address in response to the delay enable signal.
Description
The present invention relates to a repeater.
The semiconductor memory device receives an address through a pad and performs an operation on a low address path and an operation on a column address path. In the operation of the low address path, a low address is generated from an address transmitted through a pad in synchronization with a low address strobe signal, and a word line connected to a memory cell is selected by the generated low address. Meanwhile, in the operation of the column address path, a column address is generated from an address transmitted through a pad in synchronization with a column address strobe signal, and data generated between the bit line and the input / output line is exchanged by the generated column address. Enable the output enable signal.
In a semiconductor memory device, in order to perform a read operation or a write operation, an operation regarding a low address path and an operation regarding a column address path should be performed. For this purpose, an address must be input through a pad. The address input through the pad is transmitted to the banks included in the semiconductor memory device. Since the signal level of the address is attenuated by the loading of the address transmission line, the address is amplified by the repeater provided in the address transmission line. Is sent.
1 is a view of a repeater according to the prior art.
As shown in FIG. 1, the repeater of the related art is driven by a read enable signal RD_EN input at a logic high level during a read operation to amplify the input address CA_IN and output it to the output address CA_OUT. .
However, in the repeater having such a configuration, when a PVT (Proess, Voltage, Temperature) characteristic change occurs in the transmission line to which the input address CA_IN is transmitted, the input address (RD_EN) is enabled in the section where the lead enable signal RD_EN is enabled. CA_IN) may not be delivered. That is, since there is no input margin between the read enable signal RD_EN and the input address CA_IN, an input operation CA_IN for a read operation is amplified and a malfunction occurs that is not output to the output address CA_OUT.
The present invention discloses a repeater capable of preventing a malfunction due to a change in the characteristics of an address line.
To this end, the present invention comprises an enable signal delay unit for generating a delay enable signal by delaying the enable signal in response to the test signal; And an address output unit configured to amplify an input address and output the output address in response to the delay enable signal.
1 is a view of a repeater according to the prior art.
2 is a block diagram showing the configuration of a repeater according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of an enable signal delay unit included in the repeater shown in FIG. 2.
FIG. 4 is a circuit diagram of an address output unit included in the repeater shown in FIG. 2.
FIG. 5 is a timing diagram for describing an operation of the repeater illustrated in FIG. 2.
Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.
2 is a block diagram showing the configuration of a repeater according to an embodiment of the present invention.
As shown in FIG. 2, the repeater according to the present exemplary embodiment delays the enable signal EN by a predetermined period in response to the first and second test signals TM <1: 2>, and thus the delay enable signal. An enable
As shown in FIG. 3, the enable
The first enable
The second enable
The enable
An
The
The
The
The operation of the repeater having such a configuration will be described below with reference to FIG. 5.
As in the first case (CASE 1), when the input address CA_IN is input in synchronization with the timing T3, the timing T6 and the timing T9, the repeater of the present embodiment has a first test signal TM <1> and a second test. Regardless of the level of the signal TM <2>, the input address CA_IN is amplified and output to the output address CA_OUT.
On the other hand, as in the second case (CASE2), the operation of the repeater in the case where the input address (CA_IN) is delayed for a predetermined period and transmitted by the change in the PVT characteristics of the transmission line to which the input address (CA_IN) is transmitted as follows. .
First, as in time T3, both the first test signal TM <1> and the second test signal TM <2> are applied at a logic low level, so that the enable signal EN is inverted and buffered, and thus the delay enable signal. If the signal is output as (END), the output signal CA_OUT is not output properly due to insufficient margin of the delay enable signal END and the input address CA_IN.
Next, as in the time point T6, when the first test signal TM <1> is at the logic high level and the second test signal TM <2> is at the logic low level, the enable signal EN is set to zero. Since the delay is delayed through the
Next, when the first test signal TM <1> and the second test signal TM <2> are at the logic high level, as in the time point T9, the enable signal EN is the
As described above, the repeater of the present exemplary embodiment is configured to delay delay signal END by the first test signal TM <1> and the second test signal TM <2> when the PVT characteristic change occurs. By checking whether the input address CA_IN is secured, malfunctions can be prevented.
1: enable signal delay unit 11: first enable signal delay unit
12: second enable signal delay unit 2: address output unit
21: precharge unit 22: drive signal generation unit
23: drive unit
Claims (6)
And an address output unit configured to amplify an input address and output the output address in response to the delay enable signal.
A delay unit delaying the enable signal by the predetermined period;
A first transfer element transferring the enable signal in response to the test signal; And
And a second transfer device configured to transfer an output signal of the delay unit in response to the test signal.
A driving signal generation unit receiving the input address and the delay enable signal and generating a pull-up signal and a pull-down signal; And
And a driving unit for driving the output address in response to the pull-up signal and the pull-down signal.
And a precharge unit for driving an input node of the input address in response to a precharge signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100098096A KR20120036431A (en) | 2010-10-08 | 2010-10-08 | Reapter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100098096A KR20120036431A (en) | 2010-10-08 | 2010-10-08 | Reapter |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20120036431A true KR20120036431A (en) | 2012-04-18 |
Family
ID=46138021
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020100098096A KR20120036431A (en) | 2010-10-08 | 2010-10-08 | Reapter |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20120036431A (en) |
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2010
- 2010-10-08 KR KR1020100098096A patent/KR20120036431A/en not_active Application Discontinuation
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