KR20010038946A - Sense amplifier output control circuit - Google Patents

Abstract

PURPOSE: A sense amp output control circuit is provided to control the output of an output data enable signal and a sense amp output signal by detecting the transition of a sense amp output pulse signal and accordingly generating a sense amp output transition detection signal(SATD) of short pulse. CONSTITUTION: The circuit includes: a sense amp circuit part(100) which outputs a sense amp output pulse signal(SAOUT_P) generated by sensing and amplifying data inputted to a data line and also outputs a sense amp output transition detection signal(SATD) by detecting the transition of the sense amp output pulse signal; and a data output part(200) which outputs a sense amp output signal(SAOUT) as an output data(DOUT) having a fixed level, being controlled by a sense amp output initialization signal(CSPRE) and an output data enable signal(ODE) and the sense amp output transition detection signal. Thus, the circuit improve the output speed of data sensed and amplified in the sense amp, by controlling the output data enable signal and a transmission gate part(140) and a latch part(210) by generating the sense amp output transition detection signal of short pulse.

Description

Sense amplifier output control circuit {SENSE AMPLIFIER OUTPUT CONTROL CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit of a memory, and in particular, detects a transition of a sense amplifier output pulse signal and accordingly generates a sense amplifier output transition detection signal, which is a short pulse, thereby outputting an output data enable signal and a sense amplifier output signal. It relates to a sense amplifier output control circuit for controlling the output of the.

FIG. 1 is a circuit diagram illustrating a conventional sense amplifier output circuit, which is controlled by a sense amplifier output enable signal SOEN, a sense amplifier enable signal SEN, and a data line equalization signal DLEQ. A sense amplifier circuit unit 10 for sensing and amplifying data input to the data lines DATA and DATAB and outputting the sensed signal as a sense amplifier output signal SAOUT; And a data output unit 20 controlled by the sense amplifier output initialization signal CSPRE and the output data enable signal ODE to output the sense amplifier output signal SAOUT as output data DOUT having a predetermined level. do.

Here, the sense amplifier circuit unit 10 is controlled by the data line equalization signal DLEQ and includes an equalization unit 11 for equalizing the data lines DATA and DATAB; A sensing and amplifying unit 12 which is controlled on / off by a sense amplifier enable signal SEN, senses and amplifies data input through the data lines DATA and DATAB and outputs them as a sense amplifier output pulse signal SAOUT_P. )Wow; And a transmission gate section 13 that is enabled by the sense amplifier output enable signal SOEN and outputs the sense amplifier output pulse signal SAOUT_P as the sense amplifier output signal SAOUT.

In addition, the data output unit 20 initializes the output data DOUT through the PMOS transistor PM controlled by the sense amplifier output initialization signal CSPRE, and the sense amplifier input to the node N1. A precharge and latch unit 21 for latching the output signal SAOUT; An output data control unit controlled by an output data enable signal ODE and outputting a pull-up signal DUTPU or a pull-down signal DUTPD according to the sense amplifier output signal SAOUT latched by the precharge and latch unit 21. (22); A pull-up PMOS transistor (PUPM) for conducting control by the pull-up signal (DUTPU) to output a power supply voltage as output data (DOUT); And a pull-down NMOS transistor PDNM which is electrically controlled by the pull-down signal DUTPD and outputs a ground voltage as output data DOUT. Referring to the timing diagram of FIG. Explain.

When an address transition is detected as shown in FIGS. 2A through 2B by the read command, an address transition detection (ATD) signal is generated, and accordingly, a sense amplifier output enable signal SOEN is generated. ), A sense amplifier enable signal SEN, a data line equalization signal DLEQ, a sense amplifier output initialization signal CSPRE, and an output data enable signal ODE are generated.

First, the equalizer 11 applies the data line equalization signal DLEQ to "low" by the ATD signal as shown in (d) of FIG. 2, wherein the data lines DATA and DATAB in the equalization state are shown in FIG. As shown in (c), data stored in a memory cell (not shown) is received.

Then, the sensing and amplifying unit 12 senses and amplifies data input through the data lines DATA and DATAB by a sense amplifier enable signal SEN that is "low" as shown in FIG. As shown in FIG. 2 (f), the signal is output as the sense amplifier output pulse signal SAOUT_P.

At this time, the sense amplifier output enable signal SOEN is shifted by the sense amplifier enable signal SEN as shown in FIG. 2G, and the sense amplifier output enable signal SOEN is transitioned. By this, the sense amplifier output pulse signal SAOUT_P is generated, and the transfer gate unit 13 is enabled by the sense amplifier output pulse signal SAOUT_P which is " low " Outputs SAOUT to the data output unit 20.

Then, the precharge and latch unit 21 turns on the PMOS transistor PM by the sense amplifier output initialization signal CSPRE that is " low " before the data output occurs, and initializes the output data DOUT thereafter. When the data output occurs, the PMOS transistor PM is turned off by the sense amplifier output initialization signal CSPRE that is "high" and the node N1 is floating. At this time, a sense amplifier generated according to the data is generated. The output signal SAOUT is input to the node N1.

At this time, the sense amplifier controller (not shown) receives an address transition detection (ATD) signal that transitions from "high" to "low" and outputs the output data enable signal ODE as shown in FIG. The output data controller 22 outputs the sense amplifier output signal SAOUT as the pull-up signal DUTPU or the pull-down signal DUTPD according to the output data enable signal ODE as shown in FIG. The pull-up PMOS and the pull-down NMOS transistors PUPM and PDNM are electrically controlled by the signals DUTPU and DUTPD to output a power supply voltage or a ground voltage as output data DOUT.

Here, the sense amplifier output enable signal SOEN is a predetermined time t1 after the sense amplifier output pulse signal SAOUT_P is outputted so that the sense amplifier output pulse signal SAOUT_P is correctly transmitted to the data output unit 20. Delay output, and the output data enable signal (ODE) is a predetermined time (t2) after the sense amplifier output signal (SAOUT) is output so that the sense amplifier output signal (SAOUT) is correctly transmitted to the output data control unit (22). The delay time (t1, t2) is affected by the internal power supply or temperature, so the proper value should be set.

As described above, in order to accurately transmit the data sensed and amplified by the sense amplifier in the related art, the sense amplifier output enable signal SOEN and the output data enable signal ODE are respectively sense amplifier output pulse signals SAOUT_P. And a delay time of a predetermined time is required after the sense amplifier output signal SAOUT is output, which causes the entire data output to be delayed.

Accordingly, the present invention has been made to solve the above-described problems, and detects the transition of the sense amplifier output pulse signal SAOUT_P and accordingly sense amplifier output transition detection signal SATD which is a short pulse. It is an object of the present invention to provide a sense amplifier output control circuit for generating an output data enable signal (ODE) and the control of the output of the sense amplifier output signal (SAOUT).

1 is a circuit diagram showing the configuration of a conventional sense amplifier output circuit.

FIG. 2 is a timing diagram showing an operation of each signal in FIG.

Figure 3 is a circuit diagram showing the configuration of the sense amplifier output control circuit of the present invention.

FIG. 4 is a circuit diagram showing the configuration of the data transition detection unit in FIG.

FIG. 5 is a timing diagram showing an operation process of each signal in FIG.

*** Description of the symbols for the main parts of the drawings ***

100: sense amplifier circuit unit 110: equalization unit

120: sensing and amplification unit 130: data transition detection unit

131: delay 140: transmission gate

200: data output section 210: latch section

220: output data control unit I1 to I6: inverter

NM: NMOS transistor PM: PMOS transistor

PUPM: PMOS transistor for pull up PDNM: Enmos transistor for pull down

TG1, TG2: Transmission Gate

In order to achieve the above object, the present invention outputs a sense amplifier output pulse signal SAOUT_P generated by sensing and amplifying data input to a data line as a sense amplifier output signal SAOUT, and the sense amplifier output pulse signal. A sense amplifier circuit unit for detecting a transition of SAOUT_P and outputting a sense amplifier output transition detection signal SSAT; It is controlled by the sense amplifier output initialization signal CSPRE and the output data enable signal ODE and the sense amplifier output transition detection signal TSAT to convert the sense amplifier output signal SAOUT into output data DOUT having a predetermined level. Characterized in that it comprises a data output unit for output.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram showing the configuration of the sense amplifier output control circuit of the present invention. As shown therein, a sense amplifier output pulse signal SAOUT_P generated by sensing and amplifying data input to the data lines DATA and DATAB is shown in FIG. A sense amplifier circuit unit 100 for outputting the sense amplifier output signal SAOUT and detecting the transition of the sense amplifier output pulse signal SAOUT_P and outputting a sense amplifier output transition detection signal TSAT; It is controlled by the sense amplifier output initialization signal CSPRE and the output data enable signal ODE and the sense amplifier output transition detection signal TSAT to convert the sense amplifier output signal SAOUT into output data DOUT having a predetermined level. It consists of a data output unit 200 for outputting.

Here, the sense amplifier circuit unit 100 is controlled by a data line equalization signal DLEQ to equalize the data lines DATA and DATAB; Sensing and amplifying on / off control by the sense amplifier enable signal SEN to sense and amplify data input through the data lines DATA and DATAB to output the sense amplifier output pulse signal SAOUT_P. Unit 120; A data transition detector 130 which detects a transition of the sense amplifier output pulse signal SAOUT_P and outputs a sense amplifier output transition detection signal SSAT according to the transition of the sense amplifier output pulse signal SAOUT_P; And a transmission gate unit 140 that is enabled by the sense amplifier output transition detection signal SSAT and outputs the sense amplifier output pulse signal SAOUT_P as a sense amplifier output signal SAOUT.

Here, the data transition detection unit 130 includes an inverter I1 for inverting and outputting the sense amplifier output pulse signal SAOUT_P as shown in FIG. 4; An inverter (I2) for buffering the output of the inverter (11); A delay unit (131) for delaying and outputting the output buffered by the inverter (I2) for a predetermined time; An inverter I3 for buffering the output of the retarder 131; An inverter I4 for inverting the output of the inverter I3; A transmission gate TG1 that is enabled by the outputs of the inverters I3 and I4 and transmits the sense amplifier output pulse signal SAOUT_P inverted by the inverter I1; A transmission gate TG2 that is enabled by the outputs of the inverters I3 and I4 and transmits a sense amplifier output pulse signal SAOUT_P; Inverters I5 and I6 sequentially invert the outputs of the transfer gates TG1 and TG2.

On the other hand, the data output unit 200 is NMOS transistor (NM) for conducting control by the sense amplifier output initialization signal (CSPRE) to initialize the output data (DOUT); A latch unit 210 which latches and outputs a sense amplifier output signal SAOUT of the sense amplifier circuit unit 100 which is electrically controlled and input by a sense amplifier output transition detection signal SSAT; An output data control unit 220 controlled by an output data enable signal ODE and outputting a pull-up signal DUTPU or a pull-down signal DUTPD according to the sense amplifier output signal SAOUT latched by the latch unit 210. Wow; A pull-up PMOS transistor (PUPM) for conducting control by the pull-up signal (DUTPU) to output a power supply voltage as output data (DOUT); A pull-down NMOS transistor (PDNM) for conducting control by the pull-down signal (DUTPD) and outputting a ground voltage as output data (DOUT), and the operation and operation of the embodiment according to the present invention configured as described above are attached. This will be described in detail with reference to FIG. 5.

An address transition detection (ATD) signal for detecting a shifted address as shown in FIGS. 5A to 5B is generated by the read command, and accordingly, a sense amplifier enable signal SEN is generated. The data line equalization signal DLEQ, the sense amplifier output initialization signal CSPRE, and the output data enable signal ODE are generated.

First, the equalizer 110 applies the data line equalization signal DLEQ to the low level by the ATD signal as shown in FIG. 5 (d). At this time, the data lines DATA and DATAB in the equalized state are shown in FIG. As shown in (c), data stored in a memory cell (not shown) is received.

Then, the sensing and amplifying unit 120 senses and amplifies data input through the data lines DATA and DATAB by a sense amplifier enable signal SEN that is "low" as shown in FIG. As shown in FIG. 5 (f), the signal is output as the sense amplifier output pulse signal SAOUT_P.

In this case, the data transition detection unit 130 detects the transition of the sense amplifier output pulse signal SAOUT_P and outputs a sense amplifier output transition detection signal TSAT according to the sense amplifier output transition detection signal SATD. If no transition occurs in the amplifier output pulse signal (SAOUT_P), it remains "high".

Thereafter, when the sense amplifier output pulse signal SAOUT_P transitions from "high" to "low", the sense amplifier output pulse signal SAOUT_P is input to the transmission gate TG1, and the sense amplifier inverted through the inverter I1. The output pulse signal SAOUT_P is input to the transmission gate TG2.

Here, the inverter I2 buffers the output of the inverter I1 and outputs it to the delay unit 131, and the delay unit 131 is configured of n (even) inverters to output the output of the inverter I2. Is delayed for a predetermined time T and output to the inverter I3.

Then, the inverter I3 buffers the output of the delayer 131 again and outputs it to the node N3, and the inverter I4 inverts the output of the inverter I3 input to the node N3. In this case, the outputs of the node N3 and the inverter I4 are applied to each of the transmission gates TG1 and TG2 to control them.

That is, the sense amplifier output pulse signal SAOUT_P that transitions from "high" to "low" is delayed by the delay time 131 by the predetermined time T, so that the node N3 becomes "high" and the inverter I4 of the inverter I4. The output is " low ", wherein only the transmission gate TG1 is enabled and the node of the inverter I1 transitioning from " low " to " high " is kept low for the predetermined time T. And the inverters I5 and I6 transmit a short pulse of outputting the output of the node N4 as a sense amplifier output transition detection signal TSAT that is " low " as shown in Fig. 5G. )

On the contrary, when the sense amplifier output pulse signal SAOUT_P transitions from "low" to "high", the sense amplifier output pulse signal SAOUT_P is input to the transmission gate TG1 and is inverted through the inverter I1. The output pulse signal SAOUT_P is input to the transmission gate TG2.

Here, the sense amplifier output pulse signal SAOUT_P is inputted to the node N3 after being delayed by a predetermined time T while sequentially passing through the inverter I2, the delay unit 131, and the inverter I3, and the inverter I4. ) Inverts the output of the inverter I3 input to the node N3, and the outputs of the node N3 and the inverter I4 are applied to each of the transmission gates TG1 and TG2 to control them.

That is, the sense amplifier output pulse signal SAOUT_P transitioning from "low" to "high" is delayed by the predetermined time T in the delay unit 131 so that the node N3 becomes "low" and the inverter I4 of the inverter I4. The output becomes “high”, in which only the transmission gate TG2 is enabled, and the input sense amplifier output pulse signal SAOUT_P is transmitted to the node N4 while maintaining the “low” state for the predetermined time T. The inverters I5 and I6 output a short pulse that sets the output of the node N4 as a sense amplifier output transition detection signal TSAT that is " low ".

At this time, the transmission gate unit 140 is controlled by the sense amplifier output transition detection signal SATD, and the data is obtained by using the sense amplifier output pulse signal SAOUT_P as the sense amplifier output signal SAOUT as shown in FIG. Output to the output unit 200.

Then, the NMOS transistor NM is turned on by the sense amplifier output initialization signal CSPRE that is "low" before the data output occurs to initialize the output data DOUT, and then "high" when the data output occurs. The node is turned off by the sense amplifier output initialization signal CSPRE to float the node N2. At this time, the sense amplifier output signal SAOUT is input to the node N2.

Then, the latch unit 210 is turned on by the sense amplifier output transition detection signal SSAT that is "low" applied to the gate of the PMOS transistor PM, and the sense amplifier output signal SAOUT input to the node N2. ) Is output to the output data controller 220.

At this time, the sense amplifier controller (not shown) receives the sense amplifier output transition detection signal (SATD) transitions from "high" to "low" and receives the output data enable signal (ODE) as shown in FIG. The output data controller 220 outputs a sense amplifier output signal SAOUT as a pull-up signal DUTPU or a pull-down signal DUTPD according to the output data enable signal ODE. The operating NMOS transistors PUPM and PDNM are electrically controlled by the signals DUTPU and DUTPD to output a power supply voltage or a ground voltage as output data DOUT as shown in FIG.

Therefore, since the transmission gate unit 140 and the latch unit 210 are controlled by the sense amplifier output transition detection signal SATD, the transmission gate unit 140 and the latch unit 210 can output the sense amplifier output pulse signal SAOUT_P as the sense amplifier output signal SAOUT at a high speed. In addition, since the output data enable signal ODE is also controlled by the sense amplifier output transition detection signal SATD, the operation speed of the output data controller 230 is improved.

As described above, the present invention detects the transition of the sense amplifier output pulse signal SAOUT_P and accordingly generates the sense amplifier output transition detection signal TSAT, which is a short pulse, to output the output data enable signal ODE. And controlling the transmission gate part and the latch part to improve the output speed of the data sensed and amplified by the sense amplifier.

Claims (4)

A sense amplifier output pulse signal SAOUT_P generated by sensing and amplifying data input to a data line is output as a sense amplifier output signal SAOUT, and a sense amplifier is detected by detecting a transition of the sense amplifier output pulse signal SAOUT_P. A sense amplifier circuit unit for outputting an output transition detection signal SSAT; It is controlled by the sense amplifier output initialization signal CSPRE and the output data enable signal ODE and the sense amplifier output transition detection signal TSAT to convert the sense amplifier output signal SAOUT into output data DOUT having a predetermined level. A sense amplifier output control circuit comprising a data output section for outputting. The sensing circuit of claim 1, wherein the sense amplifier circuit unit is controlled on / off by a sense amplifier enable signal SEN to sense and amplify data input through a data line and to output the sense amplifier output pulse signal SAOUT_P. An amplifier; A data transition detector for detecting a transition of the sense amplifier output pulse signal SAOUT_P and outputting a sense amplifier output transition detection signal TSAT according to the transition; And a transmission gate portion which is enabled by the sense amplifier output transition detection signal (SATD) and outputs the sense amplifier output pulse signal (SAOUT_P) as a sense amplifier output signal (SAOUT). 3. The apparatus of claim 2, wherein the data transition detection unit comprises: a first inverter for inverting and outputting the sense amplifier output pulse signal SAOUT_P; A second inverter for buffering the output of the first inverter; A delay unit configured to delay and output the output buffered by the second inverter by a predetermined time; A third inverter for buffering the output of said delayer; A fourth inverter for inverting the input of the inputted third inverter; A first transmission gate enabled by the outputs of the third inverter and the fourth inverter to transmit the sense amplifier output pulse signal SAOUT_P inverted by the first inverter; A second transmission gate enabled by the outputs of the third and fourth inverters to transmit a sense amplifier output pulse signal SAOUT_P; And a fifth and a sixth inverter for sequentially inverting and outputting the outputs of the respective transfer gates. 2. The semiconductor device of claim 1, wherein the data output unit comprises: an NMOS transistor configured to be electrically controlled by a sense amplifier output initialization signal CSPRE to initialize output data DOUT; A latch unit for latching and outputting the sense amplifier output signal SAOUT which is electrically controlled by the sense amplifier output transition detection signal SSAT; An output data control unit controlled by an output data enable signal ODE and outputting a pull-up signal DUTPU or a pull-down signal DUTPD according to a sense amplifier output signal SAOUT latched by the latch unit; A pull-up PMOS transistor configured to be electrically controlled by the pull-up signal DUTPU to output a power supply voltage as output data DOUT; And a pull-down NMOS transistor configured to be electrically controlled by the pull-down signal (DUTPD) to output a ground voltage as output data (DOUT).