KR20120029170A - Light emitting device and method of manufacturing the same - Google Patents

Light emitting device and method of manufacturing the same Download PDF

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Publication number
KR20120029170A
KR20120029170A KR1020100091101A KR20100091101A KR20120029170A KR 20120029170 A KR20120029170 A KR 20120029170A KR 1020100091101 A KR1020100091101 A KR 1020100091101A KR 20100091101 A KR20100091101 A KR 20100091101A KR 20120029170 A KR20120029170 A KR 20120029170A
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South Korea
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layer
light emitting
substrate
emitting device
graphene layer
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KR1020100091101A
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Korean (ko)
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고형덕
황성원
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삼성엘이디 주식회사
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Publication of KR20120029170A publication Critical patent/KR20120029170A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

A light emitting device and a method of manufacturing the same are disclosed. The disclosed light emitting device may include a graphene layer in contact with at least a portion of a substrate and a plurality of vertical light emitting structures provided on the graphene layer. The graphene layer may be formed on an upper surface of the substrate or may be formed to surround the substrate. The vertical light emitting structure may have a nanorod structure including a first conductivity type semiconductor, an active layer, and a second conductivity type semiconductor.

Description

Light emitting device and method of manufacturing the same

The present disclosure relates to a light emitting device and a method of manufacturing the same, and more particularly to a semiconductor light emitting device and a method of manufacturing the same.

A semiconductor light emitting device such as a light emitting diode (LED) or a laser diode (LD) uses an electroluminescence phenomenon, that is, a phenomenon in which light is emitted from a material (semiconductor) by application of a current or a voltage. As electrons and holes are combined in the active layer (ie, the light emitting layer) of the semiconductor light emitting device, energy corresponding to the energy band gap of the active layer may be emitted in the form of light. Therefore, the wavelength of light generated from the light emitting device may vary according to the size of the energy band gap of the active layer.

However, since commercially available semiconductor light emitting devices generally use a substrate having low thermal conductivity (typically, a sapphire substrate), there is a disadvantage in that heat dissipation characteristics are not excellent. In particular, since the amount of heat generated increases as the current injection amount increases, the heat dissipation problem may be a major obstacle in the development of a high output light emitting device. The use of a SiC substrate or a GaN substrate instead of a sapphire substrate may be somewhat advantageous in terms of heat dissipation characteristics, but the SiC substrate, GaN substrate, and the like are expensive (about 10 times or more than the sapphire substrate), thereby increasing the manufacturing cost.

Provided is a light emitting device having excellent heat dissipation characteristics and current injection / spreading characteristics.

It provides a method of manufacturing the light emitting device.

According to an aspect of the present invention, there is provided a substrate comprising: a substrate; A graphene layer provided on the substrate; A plurality of vertical nanostructures provided on the graphene layer and including a first conductivity type semiconductor, an active layer, and a second conductivity type semiconductor; And a first electrode provided on the plurality of vertical nanostructures.

The graphene layer may be formed to surround the substrate. In this case, the graphene layer may further include a second electrode spaced apart from the plurality of vertical nanostructures. The second electrode may be provided on the upper surface side of the substrate or on the lower surface side.

The graphene layer may be provided on an upper surface of the substrate. A second electrode spaced apart from the plurality of vertical nanostructures may be further provided on the graphene layer.

The graphene layer itself may be used as the second electrode.

A semiconductor layer of the same type as the first conductive semiconductor may be further provided between the graphene layer and the plurality of vertical nanostructures.

A semiconductor layer of the same type as the first conductivity type semiconductor may be further provided between the substrate and the graphene layer.

An insulating layer having a plurality of holes may be provided between the graphene layer and the plurality of vertical nanostructures, wherein the plurality of vertical nanostructures may be provided to correspond to the plurality of holes on the insulating layer. Can be.

The plurality of vertical nanostructures may have a core-shell structure.

In the plurality of vertical nanostructures, the first conductivity type semiconductor may be a core part, and the active layer and the second conductivity type semiconductor may be a shell part.

An intermediate electrode in contact with the second conductive semiconductors of the plurality of vertical nanostructures may be further provided.

The first electrode may be provided on the intermediate electrode.

According to another aspect of the invention, forming a graphene layer on the substrate; Forming a plurality of vertical nanostructures including a first conductivity type semiconductor, an active layer, and a second conductivity type semiconductor on the graphene layer; And forming a first electrode on the plurality of vertical nanostructures.

The graphene layer may be formed to surround the substrate. A second electrode spaced apart from the plurality of vertical nanostructures may be further formed on the graphene layer. The second electrode may be formed on an upper surface side or a lower surface side of the substrate.

The graphene layer may be formed on an upper surface of the substrate. A second electrode spaced apart from the plurality of vertical nanostructures may be further formed on the graphene layer.

A semiconductor layer of the same type as the first conductive semiconductor may be formed between the graphene layer and the plurality of vertical nanostructures.

A semiconductor layer of the same type as the first conductivity type semiconductor may be formed between the substrate and the graphene layer.

The forming of the plurality of vertical nanostructures may include forming an insulating layer; Forming a plurality of holes in the insulating layer; Growing the first conductivity type semiconductor in a nanopillar shape in the plurality of holes; And sequentially forming the active layer and the second conductive semiconductor to surround the first conductive semiconductor.

The plurality of vertical nanostructures may be formed in a core-shell structure.

An intermediate electrode in contact with the second conductive semiconductors of the plurality of vertical nanostructures may be formed.

The first electrode may be formed on the intermediate electrode.

A light emitting device having excellent heat dissipation characteristics and improved current injection / spreading characteristics can be implemented.

1 is a cross-sectional view showing a light emitting device according to an embodiment of the present invention.
2 is a cross-sectional view showing a light emitting device according to another embodiment of the present invention.
3 is a cross-sectional view showing a light emitting device according to another embodiment of the present invention.
4 is a cross-sectional view showing a light emitting device according to another embodiment of the present invention.
5 is a cross-sectional view showing a light emitting device according to another embodiment of the present invention.
6 is a cross-sectional view showing a light emitting device according to another embodiment of the present invention.
7A to 7G are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment of the present invention.
Description of the Related Art [0002]
100: substrate 110, 110 ': graphene layer
200, 200 ': semiconductor layer 210: first insulating layer
300: first conductive semiconductor 310: active layer
320: second conductive semiconductor 330: transparent electrode
400: second insulating layer 500: first electrode
600: second electrode H1: hole
N1: vertical nanostructure

Hereinafter, a light emitting device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of the layers or regions illustrated in the drawings are somewhat exaggerated for clarity. Like numbers refer to like elements throughout.

1 shows a light emitting device according to an embodiment of the present invention.

Referring to FIG. 1, a graphene layer 110 may be provided on the substrate 100. The graphene layer 110 may be formed to surround the substrate 100. Although not shown, another material layer may be further provided between the substrate 100 and the graphene layer 110. The substrate 100 may be any one of various substrates used in a general semiconductor device process. For example, the substrate 100 may be any one of a sapphire (Al 2 O 3 ) substrate, a Si substrate, a SiC substrate, an amorphous AlN substrate, and a Si-Al substrate. However, this is exemplary and other substrates may be used. The graphene layer 110 may be a layer including one or several graphenes. Graphene will be described in more detail later.

The first conductive semiconductor layer (hereinafter, referred to as a first semiconductor layer) 200 may be provided on the graphene layer 110. The first semiconductor layer 200 may be, for example, an n-type semiconductor layer, but in some cases, may also be a p-type semiconductor layer. The first semiconductor layer 200 may have a single layer or a multilayer structure. Although not shown, a predetermined buffer layer may be provided between the first semiconductor layer 200 and the graphene layer 110. The first insulating layer 210 may be provided on the first semiconductor layer 200. A plurality of holes H1 exposing the first semiconductor layer 200 may be formed in the first insulating layer 210.

A plurality of vertical nanostructures N1 may be provided on the first insulating layer 210. The nanostructure N1 may also be called a nanorod. The plurality of vertical nanostructures N1 may be formed to correspond to the plurality of holes H1. In this case, the plurality of vertical nanostructures N1 may be connected to the first semiconductor layer 200 through holes H1 corresponding thereto. In more detail with respect to the nanostructure (N1), the nanostructure (N1) is a nano-conducting first conductive semiconductor 300, and the active layer 310 and the second conductive semiconductor 320 surrounding the periphery It may include. The first conductivity type semiconductor 300 may be referred to as a core portion, and the active layer 310 and the second conductivity type semiconductor 320 may be referred to as shells. Therefore, the nanostructure (N1) can be said to have a core-shell (core-shell) structure.

In the nanostructure N1, the first conductivity-type semiconductor 300 may be n-type, and the second conductivity-type semiconductor 320 may be p-type or vice versa. The active layer 310 may be a light emitting layer that emits light while combining electrons and holes. The first conductivity type semiconductor 300, the active layer 310, and the second conductivity type semiconductor 320 may have various modified structures. For example, the first conductivity type semiconductor 300 and the second conductivity type semiconductor 320 may have a multilayer structure. The active layer 310 may have a structure in which a quantum well layer and a barrier layer are alternately stacked one or more times. In this case, the quantum well layer may have a single quantum well structure or a multi-quantum well structure. Also, although not shown, the nanostructure N1 may further include a superlattice structure layer. In addition, although the active layer 310 and the second conductive semiconductor 320 are illustrated as having a continuous structure as a whole, the active layer 310 and the second conductive semiconductor 320 may be formed of adjacent nanostructures ( It may have a structure broken between N1) (ie discontinuous structure). In addition, various modification structures may be possible.

The nanostructure N1 may further include a transparent electrode 330 at the outermost portion. In other words, the transparent electrode 330 may be further provided to cover the second conductivity-type semiconductor 320 as a whole. The transparent electrode 330 may be referred to as a kind of intermediate electrode. The transparent electrode 330 may be viewed as a part of the nanostructure N1, but may be regarded as a separate component. A second insulating layer 400 may be provided to fill a space between the plurality of nanostructures N1. Whether or not to form the second insulating layer 400 may be optional. That is, in some cases, the second insulating layer 400 may not be provided.

The first electrode 500 may be provided on the transparent electrode 330. The first electrode 500 may be connected to the second conductive semiconductor 320 through the transparent electrode 330. When the second conductive semiconductor 320 is a p-type semiconductor, the first electrode 500 may be referred to as a p-type electrode. The second electrode 600 may be further provided on the graphene layer 110. The second electrode 600 may be formed on the top surface of the graphene layer 110 spaced apart from the first semiconductor layer 200. The second electrode 600 may be connected to the first semiconductor layer 200 through the graphene layer 110. When the first semiconductor layer 200 is an n-type semiconductor layer, the second electrode 600 may be referred to as an n-type electrode.

Hereinafter, graphene constituting the graphene layer 110 will be described in more detail.

Graphene is a monolayer structure made of carbon. Graphene is electrically two-dimensional ballistic transport. The transfer of charge in a material by two-dimensional ballistics means that it moves in a state where there is little resistance from scattering. Therefore, graphene can have very small electrical resistance even at small sizes of sub-microns. Thus, graphene may have high charge mobility (about 100 times Si) and high current density (about 100 times Cu). Graphene also has very good thermal conductivity and thermal stability. Specifically, the graphene may have a thermal conductivity of 5 × 10 3 W / mk or more, and may stably maintain characteristics even at a high temperature of 1000 ° C. or more.

Therefore, when the substrate 100 is wrapped with the graphene layer 110 or at least applied between the substrate 100 and the plurality of nanostructures N1, heat dissipation characteristics of the light emitting device may be improved. In addition, since the current injection and current spreading characteristics are improved by the graphene layer 110, current injection may be uniformly performed on the plurality of nanostructures N1, and as a result, the plurality of nanostructures N1. ) May exhibit uniform light emission characteristics. Therefore, according to the embodiment of the present invention, it is possible to implement a high output light emitting device having excellent heat dissipation characteristics and uniform light emitting characteristics. In particular, in the exemplary embodiment of the present invention, since the vertical nanostructure N1 is used, a large number of light emitting structures (ie, nanostructures) can be easily formed in a narrow region. Therefore, the amount of light emitted per unit area can be greatly increased as compared with the conventional light emitting device using a horizontal film structure.

The structure of FIG. 1 can be variously modified. Examples are shown in FIGS. 2 to 4.

As shown in FIG. 2, the second electrode 600 may be formed under the substrate 100. In this case, since the first electrode 500 and the second electrode 600 exist above and below the substrate 100, respectively, the light emitting device may be referred to as a vertical device in this respect.

In the structure of FIG. 2, the first semiconductor layer 200, the first insulating layer 210, and the plurality of nanostructures N1 may be extended to cover the entire upper surface of the substrate 100. An example is shown in FIG. 3.

In addition, as illustrated in FIG. 4, the second electrode 600 may not be provided. In this case, the graphene layer 110 itself may be used as the second electrode. In the structure of FIG. 4, the first semiconductor layer 200, the first insulating layer 210, and the plurality of nanostructures N1 may be extended to cover the entire upper surface of the substrate 100.

1 to 4, the graphene layer 110 is formed to surround the substrate 100, but the formation range / region of the graphene layer 110 may vary. For example, as shown in FIG. 5, the graphene layer 110 ′ may be formed only on the top surface of the substrate 100.

In addition, the formation position of the graphene layer 110 ′ in FIG. 5 may vary. One example is shown in FIG. 6.

Referring to FIG. 6, a first semiconductor layer 200 ′ may be provided on the substrate 100, and a graphene layer 110 ′ may be provided on the first semiconductor layer 200 ′. In this case, the first semiconductor layer 200 ′ may be provided to cover the entire upper surface of the substrate 100. The configuration of FIG. 6 may be the same as that of FIG. 5 except that the formation positions of the first semiconductor layer 200 ′ and the graphene layer 110 ′ are reversed and the size of the first semiconductor layer 200 ′ is changed. have.

1 to 6, the first semiconductor layers 200 and 200 ′ may not be provided. For example, even if the first semiconductor layer 200 is not provided in FIG. 1, injection of current into the first conductive semiconductor 300 through the graphene layer 110 may be easily performed. In this regard, the provision of the first semiconductor layers 200 and 200 ′ may be optional.

Hereinafter, a method of manufacturing a light emitting device according to an embodiment of the present invention will be described with reference to FIGS. 7A to 7G.

Referring to FIG. 7A, a graphene layer 110 may be formed to surround the substrate 100. Before forming the graphene layer 110, a predetermined material layer (not shown) is first formed on the surface of the substrate 100, and then the graphene layer is formed by using the material layer as a buffer layer or a seed layer. 110 may be formed. For example, after forming a buffer layer (ex, Ni layer) on the Si substrate, the graphene may be grown on the buffer layer. Alternatively, graphene may be grown on the SiC substrate. Thermal chemical vapor deposition may be used for the growth of graphene, but other methods may be used. In addition, as shown in FIG. 5, when the graphene layer 110 ′ is formed only on the upper surface of the substrate 100, an exfoliation method may be used in addition to the thermal CVD method.

Referring to FIG. 7B, a stacked pattern of the first semiconductor layer 200 and the first insulating layer 210 may be formed on the graphene layer 110. It is known that epitaxial growth of a semiconductor material is possible on the graphene layer 110. In addition, since the graphene layer 110 has excellent thermal stability, epitaxial growth of a semiconductor may be possible on the graphene layer 110 even at a high temperature of 1000 ° C. or more. Therefore, the first semiconductor layer 200 may be easily formed on the graphene layer 110. The first semiconductor layer 200 may be an n-type semiconductor layer, but in some cases, may be a p-type semiconductor layer. The stacked pattern of the first semiconductor layer 200 and the first insulating layer 210 may be formed to partially expose the graphene layer 110 on the upper surface of the substrate 100. Although the first semiconductor layer 200 and the first insulating layer 210 are shown to have the same size (horizontal direction size), the sizes of the two layers 200 and 210 may be different from each other.

Referring to FIG. 7C, a plurality of holes H1 exposing the first semiconductor layer 200 may be formed by patterning the first insulating layer 210.

Referring to FIG. 7D, the first conductive semiconductor 300 having the nanopillar shape may be formed on the first semiconductor layer 200 exposed by the plurality of holes H1. The first conductivity type semiconductor 300 can be formed by, for example, an epitaxial growth method.

Referring to FIG. 7E, an active layer 310 and a second conductive semiconductor 320 surrounding the plurality of first conductive semiconductors 300 may be sequentially formed. The first conductive semiconductor 300, the active layer 310, and the second conductive semiconductor 320 may form a vertical nanostructure N1 having a core-shell structure. In some cases, the active layer 310 and the second conductive semiconductor 320 present between the vertical nanostructures N1 may be removed.

Next, a transparent electrode 330 may be formed to cover the top surface of the second conductivity type semiconductor 320. The transparent electrode 330 may be formed conformally to the second conductivity type semiconductor 320. The transparent electrode 330 may be considered as part of the nanostructure N1, but may not be.

Referring to FIG. 7F, a second insulating layer 400 filling the space between the plurality of nanostructures N1 may be formed. The height of the second insulating layer 400 may be somewhat lower than that of the transparent electrode 330. The height of the second insulating layer 400 may be the same as the height of the transparent electrode 330. In some cases, the second insulating layer 400 may not be formed. When the plurality of nanostructures N1 are formed densely, the subsequent process may be performed without the second insulating layer 400.

Referring to FIG. 7G, the first electrode 500 in contact with the plurality of nanostructures N1 may be formed. In addition, the second electrode 600 spaced apart from the first semiconductor layer 210 may be formed on the graphene layer 110. The second electrode 600 may be formed on the bottom surface of the substrate 100. The graphene layer 110 itself may be used as the second electrode without providing the second electrode 600.

7A to 7G are directed to the method of manufacturing the light emitting device of FIG. 1, the modifications may be made to the light emitting device of FIGS. 2 to 6. Since this is a level of technical modifications well known to those skilled in the art, a detailed description thereof will be omitted.

As such, the substrate 100 may be coated with the graphene layer 110, or the graphene layer 110 may be applied between the substrate 100 and the first semiconductor layer 200 (or the plurality of nanostructures N1). In a simple manner, a light emitting device having improved heat dissipation characteristics and current injection / spreading characteristics can be implemented. In particular, in the exemplary embodiment of the present invention, since the vertical nanostructure N1 is used, a large number of light emitting structures (ie, nanostructures) may be formed in a narrow region. Therefore, the amount of light emitted per unit area can be greatly increased as compared with the conventional light emitting device using a horizontal film structure.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those of ordinary skill in the art will appreciate that the light emitting device and the method of manufacturing the same according to the embodiment of the present invention can be modified in various ways. As a specific example, those skilled in the art will appreciate that the structure of the vertical nanostructure N1 may be variously modified in FIGS. 1 to 6. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

Claims (25)

Board;
A graphene layer provided on the substrate;
A plurality of vertical nanostructures provided on the graphene layer and including a first conductivity type semiconductor, an active layer, and a second conductivity type semiconductor; And
And a first electrode provided on the plurality of vertical nanostructures. The method of claim 1,
The graphene layer is a light emitting device formed to surround the substrate. The method of claim 2,
The light emitting device provided on the graphene layer further comprises a second electrode spaced apart from the plurality of vertical nanostructures. The method of claim 3, wherein
The second electrode is a light emitting device provided on the upper side of the substrate. The method of claim 3, wherein
The second electrode is a light emitting device provided on the lower side of the substrate. The method of claim 1,
The graphene layer is a light emitting device provided on the upper surface of the substrate. The method according to claim 6,
The light emitting device provided on the graphene layer further comprises a second electrode spaced apart from the plurality of vertical nanostructures. The method of claim 1,
The graphene layer is a light emitting device used as a second electrode. The method of claim 1,
A light emitting device further comprising a semiconductor layer of the same type as the first conductive semiconductor between the graphene layer and the plurality of vertical nanostructures. The method of claim 1,
A light emitting device further comprising a semiconductor layer of the same type as the first conductivity type semiconductor between the substrate and the graphene layer. The method of claim 1,
An insulating layer having a plurality of holes is provided between the graphene layer and the plurality of vertical nanostructures,
The plurality of vertical nanostructures are provided on the insulating layer to correspond to the plurality of holes. The method of claim 1,
The plurality of vertical nanostructures have a core-shell structure. The method of claim 12,
In the plurality of vertical nanostructures, the first conductive semiconductor is a core portion, and the active layer and the second conductive semiconductor are light emitting elements. The method of claim 1,
An intermediate electrode in contact with the second conductive semiconductor of the plurality of vertical nanostructures is further provided,
The first electrode is a light emitting device provided on the intermediate electrode. Forming a graphene layer on the substrate;
Forming a plurality of vertical nanostructures including a first conductivity type semiconductor, an active layer, and a second conductivity type semiconductor on the graphene layer; And
Forming a first electrode on the plurality of vertical nanostructures; manufacturing method of a light emitting device comprising a. The method of claim 15,
The graphene layer is a manufacturing method of a light emitting device formed to surround the substrate. 17. The method of claim 16,
And forming a second electrode spaced apart from the plurality of vertical nanostructures on the graphene layer. The method of claim 17,
The second electrode is a manufacturing method of the light emitting element is formed on the upper surface side or the lower surface side of the substrate. The method of claim 15,
The graphene layer is a manufacturing method of the light emitting device formed on the upper surface of the substrate. The method of claim 19,
And forming a second electrode spaced apart from the plurality of vertical nanostructures on the graphene layer. The method of claim 15,
And forming a semiconductor layer of the same type as the first conductive semiconductor between the graphene layer and the plurality of vertical nanostructures. The method of claim 15,
And forming a semiconductor layer of the same type as the first conductive semiconductor between the substrate and the graphene layer. The method of claim 15, wherein the forming of the plurality of vertical nanostructures comprises:
Forming an insulating layer;
Forming a plurality of holes in the insulating layer;
Growing the first conductivity type semiconductor in a nanopillar shape in the plurality of holes; And
And sequentially forming the active layer and the second conductive semiconductor so as to surround the first conductive semiconductor. The method of claim 15,
The plurality of vertical nanostructures are a method of manufacturing a light emitting device to form a core-shell (core-shell) structure. The method of claim 15,
Forming an intermediate electrode in contact with the second conductive semiconductors of the plurality of vertical nanostructures,
The first electrode is formed on the intermediate electrode.
KR1020100091101A 2010-09-16 2010-09-16 Light emitting device and method of manufacturing the same KR20120029170A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101338148B1 (en) * 2012-05-01 2014-01-06 주식회사 칩테크놀러지 Semiconductor Light Emitting Chip and Method for Manufacturing thereof
US20150129834A1 (en) * 2013-11-12 2015-05-14 Samsung Electronics Co., Ltd. Semiconductor light emitting device
KR20160046186A (en) * 2014-10-20 2016-04-28 엘지이노텍 주식회사 Light emitting device and lighting system
US9461205B2 (en) 2013-10-14 2016-10-04 Samsung Electronics Co., Ltd. Nanostructure semiconductor light emitting device
CN111326610A (en) * 2018-12-14 2020-06-23 中国科学院半导体研究所 Nano-column LED chip based on insulating substrate and preparation method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101338148B1 (en) * 2012-05-01 2014-01-06 주식회사 칩테크놀러지 Semiconductor Light Emitting Chip and Method for Manufacturing thereof
US9461205B2 (en) 2013-10-14 2016-10-04 Samsung Electronics Co., Ltd. Nanostructure semiconductor light emitting device
US20150129834A1 (en) * 2013-11-12 2015-05-14 Samsung Electronics Co., Ltd. Semiconductor light emitting device
KR20160046186A (en) * 2014-10-20 2016-04-28 엘지이노텍 주식회사 Light emitting device and lighting system
CN111326610A (en) * 2018-12-14 2020-06-23 中国科学院半导体研究所 Nano-column LED chip based on insulating substrate and preparation method thereof

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