KR20120028147A - Method for manufacturing three dimensional semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a three dimensional semiconductor memory device is provided to adjust stress of first and second material films, thereby reducing bending of a plate. CONSTITUTION: First material films(10) and second material films(20) are alternatively laminated on a substrate. The numbers of the first and second material films are 2n wherein n is an integer. Semiconductor patterns penetrate a thin film structure. A trench exposing a substrate between the semiconductor patterns is formed by patterning the thin film structure. Recess areas are formed between second material films by eliminating the first material films exposed to the trench. Conductive patterns are locally formed on the recess areas.

Description

Method for manufacturing three dimensional semiconductor memory device

The present invention relates to a method for manufacturing a three-dimensional semiconductor device, and more particularly, to a method for manufacturing a three-dimensional semiconductor device in which a plurality of thin films are continuously stacked.

There is a demand for increasing the density of semiconductor memory devices in order to meet the high performance and low price demanded by consumers. In the case of semiconductor memory devices, since the degree of integration is an important factor in determining the price of a product, an increased degree of integration is particularly required. In the case of the conventional two-dimensional or planar semiconductor memory device, since the degree of integration is mainly determined by the area occupied by the unit memory cell, it is greatly influenced by the level of the fine pattern formation technique. However, since expensive equipment is required for pattern miniaturization, the degree of integration of a two-dimensional semiconductor memory device is increasing but is still limited.

In order to overcome this limitation, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, for mass production of 3D semiconductor memory devices, a process technology capable of realizing reliable product characteristics while reducing manufacturing cost per bit than that of 2D semiconductor memory devices is required.

The problem to be solved by the present invention is to provide a method for manufacturing a three-dimensional semiconductor device that can further improve the reliability and productivity.

The problem to be solved by the present invention is not limited to the above-mentioned problem, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, at least 2n (n is an integer of 2 or more) first and second material layers are alternately repeatedly stacked on a substrate. To form a thin film structure, wherein the first material film may have a stress of 0.1-10 × 10 ⁹ dyne / cm 2, and the second material film may have a stress of −0.1 to 10 × 10 ⁹ dyne / cm 2.

Specific details of other embodiments are included in the detailed description and the drawings.

According to embodiments of the present invention, the stress applied to the substrate may be alleviated by controlling the stresses of the first and second material layers constituting the thin film structure. As a result, cracking of the first and second material layers may be prevented, and a phenomenon of bending the substrate may be reduced. Therefore, the process error in the manufacturing process of the three-dimensional semiconductor device can be reduced, and further, the productivity of the manufacturing process of the semiconductor device can be improved.

1 is a simplified circuit diagram of a three-dimensional semiconductor device according to an embodiment of the present invention.
2 is a perspective view showing a three-dimensional semiconductor device according to an embodiment of the present invention.
4 and 5 are diagrams for conceptually describing a method of manufacturing a 3D semiconductor device according to an embodiment of the present invention.
6 and 7 illustrate a method of forming a thin film structure in a method of manufacturing a 3D semiconductor device according to other exemplary embodiments of the present inventive concept.
7 to 14 are perspective views illustrating a method of manufacturing a 3D semiconductor device according to an embodiment of the present invention.
15A to 15D are views illustrating part A of FIG. 14.
16 and 17 are perspective views illustrating a 3D semiconductor device according to other example embodiments of the inventive concept.
18 is a schematic block diagram illustrating an example of a memory system including a 3D semiconductor device according to example embodiments.
19 is a schematic block diagram illustrating an example of a memory card including a 3D semiconductor device according to example embodiments.
20 is a schematic block diagram illustrating an example of an information processing system equipped with a three-dimensional semiconductor device according to the present invention.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in this specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional and / or plan views, which are ideal exemplary views of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Accordingly, shapes of the exemplary views may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. For example, the etched regions shown at right angles may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device and not to limit the scope of the invention.

Hereinafter, a three-dimensional semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described in detail with reference to the drawings.

The 3D semiconductor device according to example embodiments may include a cell array region, a peripheral circuit region, and a connection region. In the cell array region, a plurality of memory cells and bit lines and word lines for electrical connection to the memory cells are disposed. Peripheral circuits may be formed in the peripheral circuit area to drive memory cells and read data stored in the memory cells. Specifically, a word line driver, a sense amplifier, row and column decoders and control circuits may be disposed in the peripheral circuit area C / P. The connection area may be disposed between the cell array area and the peripheral circuit circuit area, and a wiring structure for electrically connecting word lines and peripheral circuits may be disposed therein.

1 is a simplified circuit diagram illustrating a cell array of a 3D semiconductor device according to an embodiment of the present invention. 2 is a perspective view illustrating a cell array of a 3D semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a cell array of a 3D semiconductor memory device according to an embodiment may include a common source line CSL, a plurality of bit lines BL, and a common source line CSL and bit lines BL. It may include a plurality of cell strings (CSTR) disposed in.

The bit lines are arranged two-dimensionally, and a plurality of cell strings CSTR are connected in parallel to each other. The cell strings CSTR may be commonly connected to the common source line CSL. That is, the plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. According to an embodiment, a plurality of common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the common source lines CSL, or each of the common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground select transistor GST connected to a common source line CSL, a string select transistor SST connected to a bit line BL, and ground and string select transistors GST and SST. ) May be formed of a plurality of memory cell transistors MCT. In addition, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be connected in common to the sources of the ground select transistors GST. In addition, the ground select line GSL, the plurality of word lines WL0-WL3 and the plurality of string select lines SSL, which are disposed between the common source line CSL and the bit lines BL, are grounded. The gate transistors of the select transistor GST, the memory cell transistors MCT, and the string select transistors SST may be used, respectively. In addition, each of the memory cell transistors MCT includes a data storage element.

Referring to FIG. 2, the common source line CSL may be a conductive thin film disposed on the substrate 100 or an impurity region formed in the substrate 100. The bit lines BL may be conductive patterns (eg, metal lines) spaced apart from the substrate 100 and disposed on the bit lines BL. The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each other. Accordingly, the cell strings CSTR are two-dimensionally arranged on the common source line CSL or the substrate 100.

Each of the cell strings CSTR includes a plurality of ground select lines GSL1 and GSL2, a plurality of word lines WL0-WL3, and a plurality of disposed between the common source line CSL and the bit lines BL. String select lines SSL1 and SSL2. In one embodiment, the plurality of string select lines SSL1 and SSL2 may constitute the string select lines SSL of FIG. 2, and the plurality of ground select lines GSL1 and GSL2 may select the ground select of FIG. 2. Lines GSL may be configured. The ground select lines GSL1 and GSL2, the word lines WL0-WL3, and the string select lines SSL1 and SSL2 may be conductive patterns stacked on the substrate 100.

In addition, each of the cell strings CSTR may include a semiconductor pillar (or a vertical semiconductor pattern PL) extending vertically from the common source line CSL and connected to the bit line BL. The semiconductor pillars PL may be formed to penetrate the ground select lines GSL1 and GSL2, the word lines WL0-WL3, and the string select lines SSL1 and SSL2. In other words, the semiconductor pillars PL may pass through a plurality of conductive patterns stacked on the substrate 100. In addition, the semiconductor pillar PL may include a body portion B and impurity regions D formed at one or both ends of the body portion B. For example, the drain region D may be formed at an upper end of the semiconductor pillar PL (that is, between the body portion B and the bit line BL).

The data storage layer DS may be disposed between the word lines WL0-WL3 and the semiconductor pillars PL. In example embodiments, the data storage layer DS may be a charge storage layer. For example, the data storage layer DS may be one of an insulating layer including a trap insulating layer, a floating gate electrode, or conductive nano dots.

A dielectric film may be disposed between the ground select lines GSL1 and GSL2 and the semiconductor pillars PL or between the string select lines SSL1 and SSL2 and the semiconductor pillar PL. Here, the dielectric film may be formed of the same material as the data storage film DS, or may be a gate insulating film (for example, a silicon oxide film) for a conventional MOSFET.

In this structure, the semiconductor pillars PL may be formed together with the ground select lines GSL1 and GSL2, the word lines WL0-WL3, and the string select lines SSL1 and SSL2. A MOS field effect transistor (MOSFET) used as a channel region can be configured. In contrast, the semiconductor pillars PL together with the ground select lines GSL1 and GSL2, the word lines WL0-WL3, and the string select lines SSL1 and SSL2 form a MOS capacitor. can do.

In this case, the ground select lines GSL1 and GSL2, the plurality of word lines WL0-WL3, and the string select lines SSL1 and SSL2 may be used as gate electrodes of the select transistor and the cell transistor, respectively. The semiconductor pillars PL may be formed by parasitic fields from voltages applied to the ground select lines GSL1 and GSL2, the word lines WL0-WL3, and the string select lines SSL1 and SSL2. Inversion regions may be formed. Here, the maximum distance (or width) of the inversion area may be greater than the thickness of the word lines or the selection lines for generating the inversion area. Accordingly, the inversion regions formed in the semiconductor pillars vertically overlap each other to form a current path electrically connecting the bit lines selected from the common source line CSL.

That is, the cell string CSTR includes ground and string transistors constituted by the lower and upper select lines GSL1, GSL2, SSL1, and SSL2, and cell transistors constituted by the word lines WL0-WL3 (FIG. MCT of 2) may have a structure connected in series.

The operation of the 3D semiconductor memory device described with reference to FIGS. 1 and 2 will be briefly described as follows. The operation method of the 3D semiconductor memory device according to example embodiments is not limited thereto and may be variously modified.

First, a program operation of writing data into memory cells will be described. The same voltage may be applied to the word lines WL0-WL3 positioned on the same layer, and different voltages may be applied to the word lines WL0-WL3 positioned on different layers. The program voltage V _{- PGM} is applied to the word lines WL0-WL3 of the layer including the selected memory cell, and the pass voltage V _PASS is applied to the word lines WL0-WL3 of the unselected layer. Is approved. Here, the program voltage V _PGM is a high voltage of about 10 to 20 V, and the pass voltage V _PASS is a voltage that can turn on the memory cell transistors. In addition, 0 V is applied to the bit line BL connected to the selected memory cell transistor, and a Vcc voltage (ie, a power supply voltage) is applied to the other bit lines BL. In addition, 0 V (ie, a ground voltage) is applied to the ground select lines GSL, so that the ground select transistors are all turned off. Furthermore, a Vcc voltage is applied to the selected string select line SSL, and 0 V is applied to the unselected string select line SSL. Under such a voltage condition, the selected string select transistor SST and the memory cell transistors MCT included in the selected cell string CSTR may be turned on. Therefore, the channel of the memory cell transistors MCT included in the selected cell string CSTR has an equipotential (ie, 0V) with the selected bit line BL. In this case, since the high voltage program voltage V _PGM is applied to the word lines WL0-WL3 of the selected memory cell transistor MCT, an FN tunneling phenomenon may occur and data may be written to the selected memory cell transistor.

Next, a read operation for reading data written to the memory cells will be described. The same voltage may be applied to the word lines WL0-WL3 positioned on the same layer, and different voltages may be applied to the word lines WL0-WL3 positioned on different layers. Specifically, for the read operation, 0V is applied to the word line WL0-WL3 connected to the selected memory cell transistor MCT, and word lines WL0 of the unselected memory cell transistors MCT positioned in another layer. Read voltage Vread is applied to -WL3). The read voltage Vread is a voltage capable of turning on unselected memory cell transistors. In addition, a bit line voltage of about 0.4 to 0.9 V may be applied to the selected bit line BL, and 0 V may be applied to the other bit lines BL. In addition, 0V is applied to the common source line CSL, and a read voltage Vread is applied to the ground select lines GSL so that the channel of the selected memory cell transistor MCT is connected to the common source line CSL. have. In addition, a read voltage Vread is applied to the selected string select line SSL, and 0 V is applied to the unselected string select line SSL. Under such a voltage condition, the memory cell transistor MCT may be turned on or turned off according to data 0 or 1 in the selected memory cell. When the selected memory cell transistor MCT is turned on, current flow may occur in the cell string CSTR, and a change in current flowing through the cell string CSTR may be detected through the selected bit line BL.

For example, when electrons are stored in the selected memory cell transistor MCT, the selected memory cell transistor MCT is turned off, and the voltage of the selected bit line BL is not transferred to the common source region CSL. . In contrast, when electrons are not stored in the selected memory cell transistor MCT, the selected memory cell may be turned on by a read voltage, and the voltage of the bit line BL may be transferred to the common source line CSL. .

Next, the erase operation of the three-dimensional semiconductor device will be described. In example embodiments, the charge stored in the memory cell transistor MCT may be emitted to the semiconductor pillar PL to be erased. According to another exemplary embodiment, charges of a type opposite to those stored in the data storage layer may be injected into the data storage layer to be erased. According to another exemplary embodiment, one of the memory cell transistors may be selected and erased, or the memory cell transistors MCT in a block unit may be simultaneously erased.

According to one embodiment of the present invention, in order to form three-dimensionally arranged word lines, a plurality of first and second material layers 10 and 20 are alternately repeatedly stacked on the substrate 100. Thin film structure ST may be formed. Here, the first and second material films may be sequentially stacked on at least 2n (n is an integer of 2 or more) layers.

 The thin film structure ST may provide stress to the substrate 100 (that is, a wafer), and as a result, the thin film structure ST may be bent upward or downward, as shown in FIG. 3. In addition, as the stress applied to the substrate 100 increases, warpage of the substrate 100 becomes severe, and cracks may occur between the first and second material layers 10 and 20. Can be. In addition, as the substrate 100 is bent, a process margin may be changed in a subsequent process or a process error may occur in a semiconductor facility.

Meanwhile, according to embodiments of the present invention, the stress of the first and second material films 10 and 20 constituting the thin film structure ST is controlled and applied to the substrate 100 by the thin film structure ST. Losing stress can be alleviated. Accordingly, cracking of the first and second material layers 10 and 20 may be prevented, and warpage of the substrate 100 may be suppressed. Therefore, the process error in the manufacturing process of the three-dimensional semiconductor device can be reduced, and further, the productivity of the manufacturing process of the semiconductor device can be improved.

Hereinafter, a method of forming a thin film structure in a method of manufacturing a 3D semiconductor device according to embodiments of the present invention will be described in detail with reference to FIGS. 4 to 6.

Referring to FIG. 4, the first material layers 10 and the second material layers 20 may be alternately repeatedly stacked on the substrate 100 to form a thin film structure (ST of FIG. 3).

The first material layers 10 and the second material layers 20 may be films having tensile stress and / or compressive stress. According to an embodiment, the first material layers 10 and the second material layers 20 may have opposite types of stresses. For example, the first material films 10 may be a film having a tensile stress, and the second material films 20 may be a film having a compressive stress. That is, in one embodiment, the thin film structure may include a tensile stress film and a compressive stress film that are alternately repeatedly stacked. According to an embodiment, the first material layers 10 and the second material layers 20 have a high etching selectivity in a wet etching process using a chemical solution and a low etching rate in a dry etching process using an etching gas. Can have a selectivity ratio. In addition, the first material layers 10 and the second material layers 20 may have the same thickness, and the thicknesses of the first material layer 10 and the second material layer 20 may be different from each other.

The first and second material films 10 and 20 may be formed by thermal CVD, plasma enhanced CVD, physical CVD, or atomic layer deposition (ALD). ) May be deposited using the technique.

In one embodiment, the first and second material films 10 and 20 may be deposited in a plasma atmosphere by generating a plasma in the reaction gas. For example, the first and second material layers 10 and 20 may be remote plasma CVD, microwave plasma CVD, inductively coupled plasma, dual frequency CCP. The plasma deposition apparatus may be performed using a frequency capacitively coupled plasma method, a helicon plasma CVD, or a high density plasma method.

The first material layers 10 may be at least one of a silicon layer, a silicon oxide layer, silicon carbide, a silicon oxynitride layer, and a silicon nitride layer. The second material layers 20 may be at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film, and may be made of a material different from that of the first material film 10.

The first material layers 10 may be formed of a silicon nitride layer, and the second material layers 20 may be formed of a silicon oxide layer. The silicon oxide film constituting the second material film 20 may be, for example, a high density plasma (HDP) oxide film, TEE (TetraEthylOrthoSilicate), PE-TEOS (Plasma Enhanced TetraEthylOrthoSilicate), or O ₃ -TEOS (O ₃ -Tetra Ethyl). Ortho Silicate (USG), Undoped Silicate Glass (USG), PhosphoSilicate Glass (PSG), Borosilicate Glass (BSG), BoroPhosphoSilicate Glass (BPSG), Fluoride Silicate Glass (FSG), Spin On Glass (SOG), Tonen SilaZene (TOSZ) or these Can be used in combination.

In the thin film structure, when the first material films 10 are formed by the LP-CVD or thermal-CVD method, the tensile stress applied to the substrate 100 may be increased. As a result, warpage of the substrate 100 may be severe, and cracks may occur between the first and second material layers 10 and 20.

In addition, when the silicon nitride film is formed using the LP-CVD method, since the silicon nitride film is formed in a batch type chamber, the silicon nitride film may be deposited on the front and rear surfaces of the substrate 100. Accordingly, a process of removing the silicon nitride film deposited on the rear surface of the substrate 100 is required to proceed with the subsequent process.

Meanwhile, according to an embodiment, the first and second material films 10 and 20 may be formed using plasma enhanced chemical vapor deposition (PE-CVD) technology. When the first and second material films 10 and 20 are formed by using plasma enhanced chemical vapor deposition (PE-CVD) technology, the stress of the first and second material films 10 and 20 may be reduced. It may vary depending on the composition and / or thickness of the. In addition, the stresses of the first and second material films 10 and 20 may be affected by changes in deposition parameters such as deposition temperature, RF power, pressure, reaction gas mixing rate, carrier gas concentration, and reaction type in the PE-CVD process. It may vary.

In addition, the thin film structure formed on the rear surface of the substrate 100 is removed by forming the thin film structure in a batch type chamber by performing a PE-CVD process in a single type chamber. The process of making it can be skipped.

According to an embodiment, the silicon nitride film, which is the first material film 10, may have a tensile stress, and the silicon oxide film, which is the second material film 20, may have a compressive stress. That is, the thin film structure may be formed by alternately stacking a tensile stress film and a compressive stress film.

According to one embodiment, alternately stacking the silicon nitride film and the silicon oxide film alternately may proceed in-situ in a closed chamber that performs a PE-CVD process. In detail, forming the thin film structure may include forming a silicon nitride film using a silicon source gas and a nitrogen source gas, forming a silicon oxide film using a first purge step, a silicon source gas, and an oxygen source gas, and 2 Iteratively repeating the secondary purge steps.

In more detail, when the silicon nitride film is formed using the PE-CVD method, the silicon nitride film may be deposited using a silicon source gas and a nitrogen source gas. Here, at least one selected from the group consisting of SiH ₄ , Si ₂ H ₆ SiH ₃ Cl, and SiH ₂ Cl ₂ may be used as the silicon source gas, and NH ₃ and / or N ₂ may be used as the nitrogen source gas. Can be. In addition, N ₂ and / or He gas may be used as the carrier gas.

 The silicon nitride film formed by the deposition process as described above may contain hydrogen, and may include Si-N bonding, N-H bonding, Si-H bonding, and Si-O bonding. In addition, the stress of the silicon nitride film may vary depending on the hydrogen content and the ratio of N—H bonding / Si—H bonding. In detail, the tensile stress increases as the ratio of N-H bonding / Si-H bonding decreases, and the compressive stress may increase as the ratio of N-H bonding / Si-H bonding increases. Further, in the silicon nitride film, the content of hydrogen and the ratio of N-H bonding / Si-H bonding may vary depending on the deposition temperature of the silicon nitride film. Specifically, as the deposition temperature increases when the silicon nitride film is formed, the content of hydrogen and the ratio of N—H bonding / Si—H bonding in the silicon nitride film may be reduced.

When forming a silicon oxide film using the PE-CVD method, the silicon oxide film may be deposited using a silicon source gas and an oxygen source gas. Here, at least one selected from the group consisting of SiH ₄ , Si ₂ H ₆ SiH ₃ Cl, SiH ₂ Cl _2, and TEOS may be used as the silicon source gas, and N ₂ O, O ₂ may be used as the oxygen source gas. And / or O ₃ (ozone) may be used. The silicon oxide film formed by such a deposition process may include Si-O and Si-OH bonding, and compressive stress may increase as the Si-OH bonding decreases.

According to one embodiment, the silicon nitride film may be formed at a deposition temperature of about 250 ℃ to 650 ℃. In addition, the silicon nitride film provides about 10 to 100 sccm of SiH ₄ gas, about 10 to 100 sccm of NH ₃ gas, and about 1 to 5 slm of N ₂ gas, and about 50 to 10,000 W in an airtight chamber. Can be formed. The silicon nitride film thus formed may have a ratio of NH bonding / Si—H bonding of about 1 to 5, and may have a stress of about 0.1 to 10 × 10 ⁹ dyne / cm 2.

According to an embodiment, the silicon oxide film may be formed at a deposition temperature of about 250 ° C. to 650 ° C., and the SiH ₄ gas is about 10-100 sccm, the N ₂ O gas, or the O ₂ gas is about 10-100 sccm in a sealed chamber. It may be formed by providing an RF power to about 50 ~ 10,000W. The silicon oxide film formed as described above may have a stress of about −0.1 to −10 × 10 ⁹ dyne / cm 2.

As such, the tensile stress film and the compressive stress film may be alternately repeatedly stacked to form a thin film structure, thereby controlling the stress applied to the substrate 100 by the thin film structure. That is, in the embodiment shown in FIG. 4, the stress applied to the substrate 100 may be canceled by the tensile stress of the first material films 10 and the compressive stress of the second material films 20. have. Accordingly, the stress applied to the substrate 100 by the thin film structure is reduced, and thus the bending of the substrate 100 can be suppressed as shown in FIG. 3. According to one embodiment, after the thin film structure is formed on the substrate 100, the degree of warpage of the substrate 100 (that is, the height difference between the center of the substrate 100 and the edge of the substrate 100) warpage height (WH) of FIG. 3 may be reduced to about ± 200 μm or less.

Meanwhile, according to another embodiment, the first material film 10 made of the silicon nitride film may have a compressive stress, and the second material film 20 made of the silicon oxide film may have a tensile stress. For example, when forming a silicon nitride film using PE-CVD technology, NH bonding / Si- is changed by changing deposition parameters such as temperature, RF power, pressure, reaction gas mixing rate and reaction type in the PE-CVD process. A silicon nitride film having a ratio of H bonding of about 5 to 20 can be formed. As the bonding ratio is increased, the silicon nitride film may have a compressive stress.

Meanwhile, in another embodiment, in order to reduce the tensile stress of the silicon nitride film, a hydrogenation process may be performed to increase the hydrogen content in the silicon nitride film. On the contrary, in order to increase the tensile stress applied to the substrate 100 by the silicon nitride film, a plasma treatment process using nitrogen radicals may be performed. Accordingly, Si-N bonding can be denser in the silicon nitride film.

In addition, in one embodiment, after forming the silicon oxide film having a compressive stress as the second material layer 20, a dehydrogenation process may be performed to reduce the compressive stress of the silicon oxide film. The dehydrogenation process includes, for example, plasma treatment, UV treatment or heat treatment in a dehydrogenation gas atmosphere, and N ₂ , O ₂ , O ₃ , N ₂ O or a combination thereof may be used as the dehydrogenation gas. As such, when the dehydrogenation process is performed on the silicon oxide film, Si-OH bonding in the silicon oxide film may be reduced to reduce hydrogen ions, and tensile stress may be increased by voids formed in the dehydrogenated silicon oxide film.

According to another embodiment, a thin film structure in which the first and second material films 10 and 20 are alternately stacked repeatedly is formed, and the first material films 10 are formed of a silicon nitride film having a compressive stress. The second material layers 20 may be formed of a silicon oxide layer such as PSG (PhosphoSilicate Glass), BSG (Borosilicate Glass), or BPSG (BoroPhosphoSilicate Glass). Here, an impurity such as Ge ions may be injected into the silicon nitride film having a compressive stress, or a UV treatment process may be performed. Accordingly, the compressive stress of the silicon nitride film can be alleviated. Accordingly, after the silicon nitride film having the compressive stress is formed, the stresses of the thin film structure in which the first and second material layers are repeatedly formed alternately may be alleviated by performing processes to alleviate the compressive stress.

According to the embodiment illustrated in FIG. 5, a thin film structure in which the first material films 10a and 10b and the second material films 110 are alternately stacked is formed, and the first material films 10a and 10b are formed. ) May have tensile or compressive stress. For example, the first material films 10a and 10b are stacked on the substrate 100 via the second material film 110, wherein the first material films 10a and 10b are tensile stressed. The silicon nitride film having and the silicon nitride film having a compressive stress may be alternately stacked. The second material layers 110 may be formed of a silicon oxide layer such as PSG (PhosphoSilicate Glass), BSG (Borosilicate Glass), or BPSG (BoroPhosphoSilicate Glass). That is, a silicon nitride film having a tensile stress, a silicon oxide film, a silicon nitride film having a compressive stress, and a silicon oxide film may be sequentially and repeatedly formed on the substrate 100. Accordingly, the stress applied to the substrate 100 may be alleviated by the thin film structure including the plurality of first and second material layers 10a, 10b, and 110.

According to the embodiment shown in FIG. 6, a thin film structure in which the first and second material films 10a, 10b and 110 are alternately stacked is formed, and the first material films 10a and 10b are tensile or It can be a compressive stress. Here, the first material layers 10a and 10b constituting the lower portion of the thin film structure may have a tensile stress on the substrate 100, and the first material layers 10a and 10b constituting the upper portion of the thin film structure may be The substrate 100 may have a compressive stress. To this end, the first material films 10a and 10b may be formed of a silicon nitride film formed using a PE-CVD technique, and the first material films 10a and 10b constituting the lower part of the thin film structure may be NH bonded. The ratio of / Si-H bonding may be about 1 to 5, and the ratio of NH bonding / Si-H bonding may be about 5 to 110 in the first material layers 10a and 10b constituting the upper portion of the thin film structure. have. Furthermore, the first material films 10a and 10b constituting the lower part of the thin film structure may be formed at a first deposition temperature, and the first material films 10a and 10b constituting the upper part of the thin film structure may be formed of a first material. It may be formed at a second deposition temperature lower than the deposition temperature.

As in the embodiments of the present invention, while repeatedly stacking the first and second material layers 10 and 20, deposition conditions may be changed according to the degree of warpage of the substrate 100. For example, when depositing the first and second material films 10 and 20 using PE-CVD technology, deposition parameters such as temperature, RF power, pressure, reactant gas mixing rate and reaction type may be adjusted. have. Hereinafter, a method of manufacturing a 3D semiconductor memory device using the method of forming the thin film structure according to the exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 14.

7 to 14 are perspective views illustrating a method of manufacturing a 3D semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 7, the sacrificial layers SC1 ˜ SC8 and the insulating layers 111 ˜ 118 are alternately stacked on the substrate 100.

The substrate 100 may be formed of a material having semiconductor characteristics (for example, a silicon wafer, a silicon film, a germanium film, a silicon germanium film), an insulating material (for example, an insulating film (oxide, nitride, etc.), glass), and an insulating material. It may be one of the semiconductors covered by.

The sacrificial layers SC1 to SC8 and the insulating layers 111 to 118 may be alternately and repeatedly stacked as illustrated. The sacrificial layers SC1 to SC8 and the insulating layers 111 to 118 may be formed of materials selected to have an etch selectivity. For example, the insulating layers 111 to 118 may be at least one of a silicon film, a silicon oxide film, a silicon carbide, and a silicon nitride film, and the sacrificial films SC1 to SC8 may be a silicon film, a silicon oxide film, a silicon carbide film, and a silicon nitride film. It may be a material different from the insulating film selected from among. According to this embodiment, the sacrificial layers Sc1 to SC8 may be the first material layer described with reference to FIGS. 3 to 6, and the insulating layers 111 to 118 may be second material layers. Further, in this embodiment, the sacrificial films SC1 to SC8 and the insulating films 111 to 118 may be stacked at least 2n (n is an integer of 2 or more).

In example embodiments, the sacrificial layers SC1 ˜ SC8 may have the same thickness. In contrast, the upper sacrificial layer SC1 at the lowermost layer and the upper sacrificial layer SC8 at the uppermost layer of the sacrificial layers SC1 to SC8 may be formed thicker than the sacrificial layers SC2 to SC7 disposed therebetween. In this case, the sacrificial layers SC2 to SC7 between the lowermost and uppermost sacrificial layers SC1 and SC8 may have the same thickness.

According to an embodiment, the uppermost insulating layer 118 of the insulating layers 111 to 118 may be thicker than the insulating layers 111 to 117 below. In addition, the insulating layers 111 to 117 below the upper insulating layer 118 may have the same thickness. In addition, the insulating layers 112 and 116 formed on a predetermined layer among the insulating layers 111 to 118 may be formed thicker than the other insulating layers 111, 113, 114, 115, and 117, as shown in the drawing. .

In addition, a buffer insulating layer 101 may be formed between the lowermost sacrificial layer SC1 and the substrate 100. The buffer insulating film 101 may be formed thinner than the other insulating films 111 ˜ 118 and may be a silicon oxide film formed through a thermal oxidation process.

Referring to FIG. 8, the thin film structure ST is patterned to form openings 131 exposing the substrate 100.

Specifically, the forming of the openings 131 may include forming a mask pattern (not shown) defining a planar position of the openings 131 on the thin film structure ST, and using the mask pattern as an etching mask. And anisotropically etching the thin film structure ST.

The openings 131 may be formed to expose sidewalls of the sacrificial layers SC1 to SC8 and the insulating layers 111 to 118. In addition, according to an embodiment, the openings 131 may be formed to penetrate the buffer insulating film 101 to expose the top surface of the substrate 100. In addition, an upper surface of the substrate 100 exposed to the opening 131 by over etching may be recessed to a predetermined depth while the openings 131 are formed. The openings 131 may have different widths according to distances from the substrate 100 by an anisotropic etching process.

According to one embodiment, each of the openings 131 may be formed in the shape of a cylindrical or cuboid hole, as shown in FIG. 2, and may be formed two-dimensionally and regularly on the xy plane. That is, the openings 131 are spaced apart from each other on the x and y axes, respectively. According to another embodiment, in the horizontal shape, the openings 131 may be trenches in the form of lines extending in the y-axis direction. The openings 131 having a line shape may be formed to be parallel to each other. According to another embodiment, the openings 131 may be arranged in a zig zag in the y-axis direction, as shown in FIG. 17. In addition, the separation distance between the openings 131 adjacent in one direction may be less than or equal to the width of the opening. As such, when the openings 131 are arranged in a zigzag shape, a larger number of openings 131 may be disposed within a predetermined area.

9, a semiconductor pattern 132 is formed in the openings 131.

In detail, the semiconductor pattern 132 may be formed in the opening to be in direct contact with the substrate 100 and may be substantially perpendicular to the substrate 100. The semiconductor pattern 132 may include, for example, silicon (Si), germanium (Ge), or a mixture thereof, and the semiconductor pattern 132 may be a semiconductor doped with impurities, or may be in an undoped state. May be an intrinsic semiconductor. In addition, the horizontal semiconductor film may have a crystal structure including at least one selected from single crystal, amorphous, and polycrystalline.

The semiconductor pattern 132 may be formed in the openings 131 using chemical vapor deposition or atomic layer deposition. In addition, when the semiconductor pattern 132 is formed using a deposition technique, a discontinuous interface due to a difference in crystal structure may be formed between the semiconductor pattern 132 and the substrate 100. In addition, according to an exemplary embodiment, the semiconductor pattern 132 may be formed of single crystal silicon by depositing amorphous silicon or polycrystalline silicon and then phase-transforming the amorphous silicon or polycrystalline silicon through a heat treatment process such as laser annealing. In addition, according to another exemplary embodiment, the semiconductor pattern 132 may be formed in the openings 131 by performing an epitaxial process using the substrate 100 exposed by the openings 131 as a seed layer. It may be formed.

In addition, the semiconductor pattern 132 may be deposited to a thickness less than half the width of the opening 131. In this case, the semiconductor pattern 132 may fill a portion of the opening 131 and define an empty area in the center portion of the opening. In addition, the thickness of the semiconductor pattern 132 (that is, the thickness of the shell) may be thinner than the width of the depletion region to be generated in the semiconductor film during operation of the semiconductor memory device or smaller than the average length of the silicon grains constituting the polycrystalline silicon. That is, the semiconductor pattern 132 may be formed in a pipe-shaped, hollow cylindrical shape, or cup shape in the openings 131. The buried insulating pattern 134 may be filled in the empty area defined by the semiconductor pattern 132. The buried insulating pattern 134 may be formed of an insulating material having excellent gap fill characteristics. For example, the buried insulation pattern 134 may be formed of a high density plasma oxide film, a spin on glass layer, and / or a CVD oxide film.

In addition, the semiconductor pattern 132 may be completely filled in the cylindrical opening 131 by a deposition process to have a cylindrical shape. In this case, after the semiconductor pattern 132 is deposited, the planarization process for the semiconductor pattern 132 may be performed.

Meanwhile, when the openings 131 are formed in a line shape, as illustrated in FIG. 16, semiconductor patterns 132 are formed in the openings 131 with insulating patterns 111 ˜ 118 therebetween. Can be. As described above, the semiconductor patterns 132 may be formed by sequentially forming a semiconductor film and a buried insulating film in the openings 131, and patterning the semiconductor film and the buried insulating film to have a rectangular plane in the opening 131. 132 may be formed. The semiconductor pattern 132 may have a U-shaped shape.

Referring to FIG. 10, after the semiconductor patterns 132 are formed, the trenches 140 exposing the substrate 100 are formed between the adjacent semiconductor patterns 132.

Specifically, forming the trenches 140 may include forming a mask pattern (not shown) defining a planar position of the trenches 140 on the thin film structure ST, and using the mask pattern as an etch mask. And anisotropically etching the thin film structure ST.

The trench 140 may be spaced apart from the semiconductor patterns 132 to expose sidewalls of the sacrificial layers SC1 to SC8 and the insulating layers 111 to 118. In the horizontal shape, the trench 140 may be formed in a line shape or a rectangle, and in the vertical depth, the trench 140 may be formed to expose the top surface of the substrate 100. 140 may have a different width depending on the distance from the substrate 100 by an anisotropic etching process. In addition, an upper surface of the substrate 100 exposed to the trench 140 by over etching may be recessed to a predetermined depth while the trenches 140 are formed.

As the trenches 140 are formed, the thin film structure may have a line shape extending in the y-axis direction. In addition, the plurality of semiconductor patterns 132 arranged in the y-axis direction may pass through the thin film structure having one line shape. As described above, the thin film structure having a line shape by the trenches 140 may have an inner wall adjacent to the semiconductor pattern 132 and an outer wall exposed to the trench 140. That is, sacrificial patterns SC1 to SC8 and insulating patterns 111 to 118 that are alternately and repeatedly stacked may be formed on the substrate 100.

Meanwhile, after forming the trenches 140, an impurity region 105 may be formed in the substrate 100. The impurity region 105 may be formed through an ion implantation process using the thin film structure having the trench 140 as an ion mask. The impurity region 105 may overlap a portion of the lower region of the thin film structure by diffusion of impurities. In addition, the impurity region 105 may have a conductivity type opposite to that of the substrate 100.

Referring to FIG. 11, the sacrificial patterns SC1 ˜ SC8 exposed to the trenches 140 may be removed to form recess regions 142 between the insulating patterns 111 ˜ 118.

The recess regions 142 may be formed by removing the sacrificial patterns SC1 to SC8 between the insulating patterns 111 to 118. That is, the recess regions 142 may extend horizontally from the trench 140 between the insulating patterns 111 to 118, and may expose portions of sidewalls of the semiconductor pattern 132. The lowermost recessed region 142 may be defined by the buffer insulating layer 101. The vertical thickness (length in the z-axis direction) of the recess region 142 formed as described above is defined by the deposition thickness of the sacrificial films SC1 to SC8 when the sacrificial films SC1 to SC8 are deposited in FIG. 2. Can be defined.

In detail, the forming of the recess regions 142 may be performed by isotropically etching the sacrificial patterns SC1 ˜ SC8 using an etch recipe having etch selectivity with respect to the insulating patterns 111 ˜ 118. It may include. Here, the sacrificial patterns SC1 ˜ SC8 may be completely removed by an isotropic etching process. For example, when the sacrificial patterns SC1 to SC8 are silicon nitride layers and the insulating patterns 111 to 118 are silicon oxide layers, the etching step may be performed using an etchant including phosphoric acid.

Referring to FIG. 12, the information storage layer 150 is formed in the recess regions 142.

The information storage layer 150 may be formed to substantially conformally cover the thin film structure in which the recess regions 142 are formed. The information storage film 150 may be formed using a deposition technique (eg, chemical vapor deposition or atomic layer deposition technique) that may provide excellent step coverage. The information storage layer 150 may be formed to have a thickness thinner than half of the thickness of the recess regions 142. That is, the information storage layer 150 may be formed on sidewalls of the semiconductor pattern 132 exposed to the recess region 142, and the information storage layer 150 may have an insulating pattern defining the recess region 142. It may extend to the lower surface and the upper surface of the field (111 ~ 118). In addition, the information storage layer 150 formed by the deposition process may be formed on the surface of the substrate 100 and the upper surface of the uppermost insulating pattern 118 exposed between the thin film structures in the form of lines, and the insulating patterns 111. May cover sidewalls of 118). The information storage layer 150 may cover the upper surface of the substrate 100 or the buffer insulating layer 101 exposed by the recessed region 142 of the lowermost layer. That is, as shown in FIGS. 15A to 15C, the information storage layer 152 may be conformally formed on the surface of the thin film structure in which the recess regions 142 are formed.

According to another embodiment, as shown in FIG. 15B, the information storage pattern 154 is locally formed between the vertically adjacent insulating patterns 111 to 118 so that the other information storage patterns 154 are vertically adjacent to each other. ) Can be separated. As such, when the information storage patterns 154 are vertically separated from each other, the charges trapped in the information storage pattern 154 may be prevented from being spread to other adjacent information storage patterns 154. Even when the information storage pattern 154 is locally formed between the vertically adjacent insulating patterns 111 to 118, the lowermost information storage pattern 154 is formed on the upper surface of the buffer insulating film 101 or the substrate 100. It may also be in direct contact with.

According to an embodiment, the information storage layer 150 may be a charge storage layer. For example, the charge storage layer may be one of a charge trap insulating layer, a floating gate electrode, or an insulating layer including conductive nano dots. In addition, when the information storage layer 150 is a charge storage layer, the information stored in the information storage layer 150 is a Fowler caused by the voltage difference between the semiconductor pattern 132 and the gate electrodes WL of FIG. 10. Can be changed using Northernheim tunneling Meanwhile, the information storage film 150 may be a thin film (for example, a thin film for the phase change memory or a thin film for the variable resistance memory) capable of storing information based on other operating principles.

According to an embodiment, as shown in FIGS. 15A and 15C, the information storage layer 150 may include a blocking insulating layer 152a, a charge trap layer 152b, and a tunnel insulating layer 152c that are sequentially stacked. . The blocking insulating layer 152a may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high dielectric film, and may include a plurality of films. In this case, the high dielectric film refers to insulating materials having a dielectric constant higher than that of silicon oxide film, and include tantalum oxide film, titanium oxide film, hafnium oxide film, zirconium oxide film, aluminum oxide film, yttrium oxide film, niobium oxide film, cesium oxide film, indium oxide film, iridium oxide film, and BST. Film and PZT film. The tunnel insulating layer 152c may be formed of a material having a lower dielectric constant than the blocking insulating layer 152a and may include, for example, at least one selected from an oxide, a nitride, an oxynitride, and the like. The charge trap film 152b may be an insulating thin film rich in charge trap sites (eg, silicon nitride film) or an insulating thin film including conductive grains. According to an embodiment, the tunnel insulating film 152c may be a silicon oxide film, the charge trap film 152b may be a silicon nitride film, and the blocking insulating film 152a may be an insulating film including an aluminum oxide film.

Meanwhile, according to another exemplary embodiment, the blocking insulating layer 152a may be formed of a first blocking insulating layer and a second blocking insulating layer. Here, the first and second blocking insulating layers may be formed of different materials, and one of the first and second blocking insulating layers may be one of materials having a band gap smaller than that of the tunnel insulating layer and larger than the charge trap layer. . For example, the first blocking insulating layer may be one of high dielectric layers such as an aluminum oxide layer and a hafnium oxide layer, and the second blocking insulating layer may be a material having a dielectric constant smaller than that of the first blocking insulating layer. In example embodiments, the second blocking insulating layer may be one of the high dielectric layers, and the first blocking insulating layer may be a material having a dielectric constant smaller than that of the second blocking insulating layer.

According to another embodiment, in the information storage film 150 composed of the blocking insulating film 152a, the charge trap film 152b, and the tunnel insulating film 152c, which are sequentially stacked, the tunnel insulating film 152c and the charge trap film 152b. 15 may be formed across the inner wall of the thin film structure adjacent to the semiconductor pattern 132. That is, the tunnel insulating film 152c and the charge trap film 152b may be formed first on the inner wall of the opening before forming the semiconductor pattern 132. The blocking insulating layer 152a may be conformally formed in the recess region 142 after the recess regions 142 are formed. Accordingly, the blocking insulating layer 152a may directly contact the upper and lower surfaces of the insulating pattern. Meanwhile, after the recess regions 142 are formed, the charge trap layer 152b and the blocking insulating layer 152a may be conformally formed in the recess region 142.

Next, referring to FIGS. 12 and 13, gate electrodes WL are formed in each of the recess regions 142 in which the information storage layer 150 is formed. In addition, when forming the gate electrodes WL, the common source conductive line CSL is formed together in the substrate 100.

As the gate electrode WL is formed in the recess region 142 in which the information storage layer 150 is conformally formed, the vertical thickness of the gate electrode WL may be reduced than the vertical thickness of the recess region 142. have. As such, the thickness reduction of the gate electrodes WL may increase the resistance of the gate electrode WL. Therefore, in order to improve the integration and electrical characteristics of the three-dimensional semiconductor memory device, it is necessary to reduce the resistivity of the material constituting the gate electrode WL.

In an embodiment, the gate electrodes WL and the common source conductive lines CSL may be formed of a metal material having low resistivity (eg, tungsten). The common source line CSL may be an impurity region 105 formed in the substrate 100. However, when the common source line CSL is an impurity region formed in the substrate 100, it may be difficult to keep the resistance constant and the resistance of the common source line CSL may be high.

In another embodiment, the common source line CSL may be formed of the impurity region 105 in the substrate 100 and the common source silicide layer 184. The common source conductive line CSL including the metal silicide may have a lower resistance than the common source conductive line including the impurity region 105. Further, in embodiments, the common source silicide film 184 constituting the common source conductive line CSL is formed simultaneously with the gate silicide film 182 constituting the gate electrode WL stacked on the substrate 100. Can be.

Hereinafter, a method of forming the gate electrodes WL and the common source line CSL will be described in detail with reference to FIGS. 12 and 13.

The gate electrodes WL may be formed by forming the gate conductive layer 170 in the recesses and the trenches in which the data storage layer 150 is formed, and by removing the gate conductive layer 170 in the trench. Forming gate electrodes WL separated from each other.

The gate conductive layer 170 may be formed using a deposition technique (eg, chemical vapor deposition or atomic layer deposition technique) that may provide excellent step coverage. Accordingly, the gate conductive layer 170 may be conformally formed in the trench while filling the recess regions. In detail, the gate conductive layer 170 may be deposited to a thickness greater than or equal to half the thickness of the recess region. When the planar width of the trench is greater than the thickness of the recess region, the gate conductive layer 170 may fill a portion of the trench and define an empty region in the center portion of the trench. At this time, the empty area may be opened upward.

The gate conductive layer 170 may include at least one of doped polysilicon, tungsten, metal nitride layers, and metal silicides. According to one embodiment, forming the gate conductive layer 170 includes sequentially forming a barrier metal layer (eg, metal nitride) and a metal layer (eg, tungsten). On the other hand, since the technical idea of the present invention is not limited to the flash memory device, the gate conductive layer 170 may be modified in various materials and structures.

Subsequently, the gate conductive layer 170 filled in the trench is anisotropically etched to form vertically separated gate electrodes WL.

Specifically, removing the gate conductive layer 170 from the trench may be performed by using a hard mask pattern (not shown) formed on the uppermost insulating layer or the upper portion of the thin film structure ST as an etching mask. And anisotropically etch the film 170. When anisotropically etching the gate conductive layer 170, the data storage layer 150 in contact with the top surface of the substrate 100 may be used as an etch stop layer.

In example embodiments, a trench for exposing the data storage layer 150 covering the top surface of the substrate 100 may be formed to form the vertically separated gate electrodes WL. Alternatively, the anisotropic etching of the gate conductive layer 170 may expose the upper surface of the substrate 100 to the trench, and as shown in the figure, the upper surface of the substrate 100 may be recessed.

According to another embodiment, the gate electrodes WL may be formed by performing an isotropic etching process on the gate conductive layer 170 having the empty area. The isotropic etching process may be performed until the gate electrodes WL are separated from each other. That is, the sidewalls of the insulating layers and the data storage layer 150 on the upper surface of the substrate 100 may be exposed by an isotropic etching process. Here, as the isotropic etching process is performed through the empty region, the gate conductive layer 170 of the sidewall and the bottom portion of the empty region may be etched substantially simultaneously. As the isotropic etching process is performed through the empty region, the gate conductive layer 170 may be uniformly etched on the thin film structure ST and the substrate 100. Accordingly, horizontal thicknesses of the gate electrodes WL may be uniform. In addition, the horizontal thicknesses of the gate electrodes WL may vary according to a process time during the isotropic etching process. For example, the gate electrodes WL may be formed to fill a portion of the recess region. Each of the gate electrodes WL formed as described above may include the metal pattern 163a and the barrier metal pattern 162 interposed between the metal pattern 163 and the data storage layer 152 as shown in FIGS. 15A through 15C. It may include.

In example embodiments, gate electrodes WL locally formed in each of the recess regions may form a gate structure. That is, the gate structure may be formed between trenches adjacent to each other. As such, as the trenches are formed, in one embodiment, the gate structure may have a line shape extending in one direction. In addition, a plurality of semiconductor patterns 132 arranged in one direction may pass through one gate structure. The gate electrodes WL have outer walls adjacent to the trench and inner walls adjacent to the semiconductor pattern 132. Inner walls of the gate electrodes WL may surround the semiconductor pattern 132 or may cross one side wall of the semiconductor pattern 132. Alternatively, the gate electrodes WL included in one block may be connected to each other in the word line contact region WCTR and may be formed in a comb-shape or a finger-shape.

According to this embodiment, the stacked gate electrodes WL may be used as the string select line SSL, the ground select line GSL, and the word lines WL described with reference to FIG. 2. For example, the top and bottom layers of the gate electrodes WL are used as the string selection line SSL and the ground selection line GSL, respectively, and the gate electrodes WL therebetween are word lines WL. Can be used as

Alternatively, as described with reference to FIG. 3, two layers of gate electrodes WL disposed at the top may be used as a string select line (SSL in FIG. 2), and two layers of gate electrodes WL disposed at the bottom thereof. ) May be used as the ground select line (GSL in FIG. 2). The gate electrodes WL used as the string select line (SSL in FIG. 2) or the ground select line (GSL in FIG. 2) may be horizontally separated, in which case a plurality of strings are electrically separated at the same height. Select lines (SSL in FIG. 2) or ground select lines (GSL in FIG. 2) may be disposed.

Meanwhile, after the gate structure is formed, a process of selectively removing sidewalls of the insulating patterns 111 to 118 and the data storage layer 150 formed on the surface of the substrate 100 is further performed as shown in FIG. 15A. Can be. In the process of removing the data storage layer 150, an etching gas or an etching solution having an etching selectivity with respect to the gate conductive layer 170 may be used. For example, when the data storage layer 150 on the sidewalls of the insulating layers is removed through an isotropic etching process, an etching solution such as HF, O ₃ / HF, phosphoric acid, sulfuric acid, and LAL may be used. In addition, in order to remove the data storage layer 150, a fluoride-based etching solution and a phosphoric acid or sulfuric acid solution may be sequentially used.

Referring to FIG. 14, after the gate electrodes WL are formed, impurity regions 105 used as a common source line may be formed by implanting impurities into the substrate 100 between the gate electrodes WL. Can be.

In detail, the impurity regions 105 may be formed through an ion implantation process using gate structures on the substrate 100 as an ion implantation mask. Accordingly, the impurity region 105 may be in the form of a line extending in one direction, such as a horizontal shape of the trench. The impurity region 105 may overlap a portion of the lower region of the gate structure by diffusion of impurities. In addition, the impurity region may have a conductivity type opposite to that of the substrate 100.

When the impurity region 105 is formed, the information storage film 150 located on the bottom surface of the trench 140 or the information storage film on the bottom surface of the trench 140 may be used as an ion implantation buffer film. According to another embodiment, the impurity region 105 may be formed in the substrate 100 under the trench 140 after the trench 140 is formed, as described with reference to FIG. 10.

In addition, according to an embodiment, a silicide process may be performed to react the impurity region 105 in the substrate 100 with the metal film 180 to form a metal silicide.

14, a gate isolation insulating pattern 190 is formed in the trenches 140.

Forming the gate isolation insulating pattern 190 may include filling the trenches 140 in which the unreacted metal film is removed with at least one of insulating materials. In an embodiment, the gate isolation insulating pattern 190 may be at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. According to another exemplary embodiment, before forming the gate isolation insulating pattern 190 in the trenches 140, a capping layer may be formed to prevent oxidation of the gate and the common source silicide layers 182 and 184. . The capping film may be formed of an insulating nitride, for example, a silicon nitride film.

After the gate isolation insulating pattern 190 is formed, the drain region D may be formed by implanting a conductive type impurity opposite to the semiconductor pattern 132 into the upper portion of the semiconductor pattern 132. Alternatively, the drain region D may be formed on the semiconductor pattern 132 before forming the trenches 140 described with reference to FIG. 4.

Subsequently, bit lines BL may be formed on the gate electrodes WL to electrically connect the semiconductor patterns 132. The bit lines BL may be formed along a direction crossing the gate electrodes WL formed in a line shape as shown. In addition, the bit lines BL may be connected to the drain regions D on the semiconductor patterns 132 by contact plugs.

18 is a schematic block diagram illustrating an example of a memory system including a semiconductor memory device manufactured according to a method of manufacturing embodiments of the present invention.

Referring to FIG. 18, the memory system 1100 may include a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, It can be applied to a memory card or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes an input / output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions performed by the controller. The input / output device 1120 may receive data or a signal from the outside of the system 1100 or output data or a signal to the outside of the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

The memory 1130 includes a nonvolatile memory device according to embodiments of the present invention. The memory 1130 may also further include other types of memory, volatile memory that can be accessed at any time, and various other types of memory.

The interface 1140 serves to transmit data to and receive data from the communication network.

19 is a schematic block diagram illustrating an example of a memory card including a semiconductor memory device manufactured according to a method of manufacturing embodiments of the present invention.

Referring to FIG. 19, a memory card 1200 for supporting a high capacity of data storage capability includes a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 includes a data exchange protocol of a host that is connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs various control operations for exchanging data of the memory controller 1220. Although it is not shown in the drawing, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned.

20 is a schematic block diagram illustrating an example of an information processing system equipped with a semiconductor memory device manufactured according to the manufacturing method of the embodiments of the present invention.

20, the flash memory system 1310 of the present invention is mounted in an information processing system such as a mobile device or a desktop computer. The information processing system 1300 according to the present invention includes a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350 electrically connected to a flash memory system 1310 and a system bus 760, respectively. It includes. The flash memory system 1310 may be configured substantially the same as the above-described memory system or flash memory system. The flash memory system 1310 stores data processed by the CPU 1330 or data externally input. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention may be further provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. Self-explanatory to those who have learned.

In addition, the flash memory device or the memory system according to the present invention may be mounted in various types of packages. For example, a flash memory device or a memory system according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline ( SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer- It can be packaged and mounted in the same manner as Level Processed Stack Package (WSP).

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

Claims (9)

On the substrate (at least) 2n (n is an integer of 2 or more) to form a thin film structure in which the first and second material films are alternately stacked,
Fabrication of a three-dimensional semiconductor device in which the first material film applies a stress of 0.1 ~ 10 × 10 ⁹ dyne / ㎠ to the substrate, the second material film applies a stress of -0.1 ~-10 × 10 ⁹ dyne / ㎠ Way. The method of claim 1,
Forming semiconductor patterns penetrating the thin film structure,
Patterning the thin film structure to form a trench that exposes the substrate between the semiconductor patterns,
Removing the first material layers exposed to the trench to form recess regions between the second material layers,
And forming conductive patterns locally in the recess regions. The method of claim 2,
Before forming the conductive patterns,
And forming a data storage layer in contact with the semiconductor pattern in each of the recess regions. The method of claim 1,
The first material films are silicon nitride films deposited using plasma enhanced chemical vapor deposition technology.
And the second material films are silicon oxide films deposited using a plasma enhanced chemical vapor deposition technique. The method of claim 4, wherein
The first and second material films are formed at a deposition temperature of 250 ° C to 650 ° C. The method of claim 1,
Forming the thin film structure,
And forming the first material films and the second material films in one chamber. The method of claim 1,
Forming the thin film structure,
And forming first and second material films on the substrate by alternating the chamber for forming the first material films and the chamber for forming the second material films. The method of claim 1,
Forming the thin film structure is a method of manufacturing a three-dimensional semiconductor device to adjust the height difference between the center of the substrate and the edge of the substrate to ± 200㎛. The method of claim 1,
The stress applied to the substrate by the thin film structure is canceled by the first material films having tensile stress and the second material films having compressive stress.

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