KR20120027640A - Slop compensation circuit for boost converter - Google Patents

Abstract

PURPOSE: A slope compensation circuit of a boost converter is provided to maximize space efficiency by using only the minimum number of MOS transistors. CONSTITUTION: A first PMOS(P-Channel Metal-Oxide Semiconductor) transistor and a second PMOS transistor composes a current mirror. A capacitor is connected between a source terminal of the first PMOS transistor and a power terminal. A current source is connected between a common connection point of the drain terminal and the gate terminal at the first PMOS transistor and a ground terminal. Source resistance is connected between the source terminal of s second PMOS transistor and the power terminal. A slope compensation circuit is connected to both ends of the capacitor. The slope compensation circuit controls the charging operation of the capacitor in a turn-on/ turn-off action. The slope compensation circuit is composed of a third PMOS transistor for outputting the target slope compensation current through the drain terminal of the second PMOS transistor.

Description

SLOPE COMPENSATION CIRCUIT FOR BOOST CONVERTER}

TECHNICAL FIELD The present invention relates to a current slope compensation technique of a DC / DC converter, and more particularly, to a slope converter circuit of a boost converter, which can simplify the configuration of a circuit for current slope compensation in a boost converter and reduce an error occurrence.

FIG. 1 is a circuit diagram of a boost converter according to the prior art and includes an inductor L11, a MOS transistor M11, a smoothing capacitor C11, and a control IC 10 as shown therein.

The inductor L11 charges electrical energy from the input voltage VIN when turned on by the MOS transistor M11 to be described later, and the charged electrical energy is outputted when turned off. The MOS transistor M11 is a power transistor and is switched (on, off) by a gate pulse GP output from the controller 10. The inductor L11 is driven according to the on / off operation of the MOS transistor M11. The Schottky diode D11 rectifies and outputs an AC voltage output from the inductor L11. The capacitor C11 outputs the voltage VOUT of the DC component by smoothing the pulse flow component included in the voltage output through the Schottky diode D11.

The controller 10 controls the driving of the power transistor M11 to output the output voltage VOUT as a target output voltage, which will be described in detail below.

The current detector 11 detects an output current of the inductor L11 and outputs a sensing current according thereto. The slope compensation circuit 12 outputs a slope compensated current so that the current of the inductor L11 can maintain a constant duty over time. The summer 13 adds and outputs the current output from the slope compensator 12 to the current output from the current sensing unit 11. The error amplifier 14 compares the feedback voltage distributed by the resistors R11 and R12 with a reference voltage and amplifies and outputs the error voltage. The error comparator 15 compares the voltage corresponding to the current output from the summer 13 with the error voltage output from the error amplifier 14 and outputs a high or low level signal according to the comparison result. . The control logic unit 17 synchronizes the gate driving signal in the form of a pulse width modulation signal PWM output from the error comparator 15 with the clock signal CLK output from the clock signal generator 16. ) The gate driver 18 drives the MOS transistor M11 as described above according to the gate pulse GP supplied from the control logic unit 17.

In other words, the current at both ends of the inductor L11 increases and decreases according to the switching operation of the MOS transistor M11. At this time, the inductor L11 has an input terminal voltage higher than the output terminal voltage when the current is increased, and the input terminal voltage is lower than the output terminal voltage when the current is decreased. That is, when the MOS transistor M11 is turned on, the input terminal voltage of the inductor L11 is in a positive polarity state higher than the output terminal voltage, and thus is not immediately transferred to the terminal side of the output voltage VOUT, thereby charging electrical energy. The voltage becomes a negative state lower than the output terminal voltage and transfers electrical energy to the output terminal. At this time, when viewed from the terminal side of the output voltage (VOUT), the voltage between the input voltage (VIN) and the both ends of the inductor (L11) appears to be summed, the output voltage (VOUT) is increased than the input voltage (VIN).

However, when the on-time (duty ratio) of the inductor L11 exceeds 50% by the magnitude of the input voltage and the output voltage, sub-harmonic oscillation occurs, so that the slope compensation is prevented. The circuit 12 is used. The slope compensation in the slope compensation circuit 12 is required to be 1/2 or more of the down slope of the inductor L11 current. In addition, the slope compensation current may use a nonlinear or linear current.

2 is a slope compensation circuit diagram of a conventional boost converter, as shown here, a current source I _C and a capacitor C21 connected in series between a power supply terminal VDD and a ground terminal; An NMOS transistor NM21 for controlling a charging operation of the capacitor C21 according to a gate pulse GP connected to a drain terminal and a source terminal respectively at both ends of the capacitor C21; An amplifier AMP21 for amplifying the charging voltage of the capacitor C21; An NMOS transistor NM22 operating on and off according to the output voltage of the amplifier AMP21, and a source resistor RS21 connected between the source terminal and the ground terminal of the NMOS transistor NM22; It is composed of a PMOS transistor (PM21) (PM22), which is configured in a mirror form and is driven by the NMOS transistor (NM22) to output a current compensated for the slope (hereinafter referred to as "slope compensation current"), The operation thereof is as follows.

A current source I _C and a capacitor C21 are connected in series between the power supply terminal VDD and the ground terminal, and the drain terminal and the source terminal of the NMOS transistor NM21 are connected to both ends of the capacitor C21, respectively. do. The gate of the NMOS transistor NM21 is supplied with a series of positive gate pulses GP for controlling slope compensation, which is a turn-on period of the MOS transistor M, which is a switching element of the inductor L. Supplied in synchronization with

Therefore, the charging voltage of the capacitor C21 is controlled by the gate pulse GP supplied as described above. The charging voltage of the capacitor C21 adjusted as described above is amplified by the amplifier AMP21 and then output to the gate of the NMOS transistor NM22.

Accordingly, the operation of the NMOS transistor NM22 is controlled by the output voltage of the amplifier AMP21, and the operation of the PMOS transistors PM21 and PM22 is controlled by the NMOS transistor NM22 operated in this manner. Controlled.

As a result, the slope compensation current I _slope is output from the drain terminal of the PMOS transistor PM22 by the series of control operations as described above.

The slope compensation current of the slope compensation circuit of FIG. 2 is expressed as follows.

As shown in Equation 1, the slope compensation current I _slope is determined by the source resistance RS21, the capacitor C21, and the charging current I _C of the capacitor C21, and thus linearly changed according to time. Increase by enemy.

As shown in Equation 1, the slope compensation current I _slope is determined by the source resistance RS21, the capacitor C21, and the charging current I _C of the capacitor C21 and is linear with time. It shows the characteristic of increasing by the end.

However, in the conventional boost converter, since the slope compensation circuit not only includes an amplifier but also includes a large number of MOS transistors, there is a defect that takes up a lot of installation space. In addition, when the circuit design does not properly consider the characteristics of the amplifier, there is a problem such as an error occurs.

Accordingly, an object of the present invention relates to a slope compensating circuit of a boost converter which can simplify the configuration of a circuit for current slope compensation in a boost converter and reduce the occurrence of errors.

The objects of the present invention are not limited to the above-mentioned objects. Other objects and advantages of the invention will be more clearly understood by the following description.

The present invention for achieving the above object,

A first PMOS transistor and a second PMOS transistor constituting the current mirror;

A capacitor connected between a power supply terminal and a source terminal of the first PMOS transistor;

A current source connected between the common terminal of the drain terminal and the gate terminal of the first PMOS transistor and the ground terminal;

A source resistor connected between a power supply terminal and a source terminal of the second PMOS transistor;

A source terminal and a drain terminal are connected to both ends of the capacitor, and the charging operation of the capacitor C31 is controlled by a turn-on / turn-off operation by a gate pulse, and the target terminal is controlled through the drain terminal of the second PMOS transistor. And a third PMOS transistor configured to output the slope compensation current.

Another invention for achieving the above object is,

A first NMOS transistor and a second NMOS transistor constituting the first current mirror;

A capacitor connected between the source terminal and the ground terminal of the first NMOS transistor;

A current source connected between a power supply terminal and a common connection point of the drain terminal and the gate terminal of the first NMOS transistor;

A source resistor connected between the source terminal and the ground terminal of the second NMOS transistor;

A third NMOS transistor having a drain terminal and a source terminal connected to both ends of the capacitor and controlling a charging operation of the capacitor by a turn-on / turn-off operation by a gate pulse to control the operation of the first mirror;

Forming a second current mirror between a power supply terminal and a drain of the second NMOS transistor to output a slope compensation current corresponding to a driving current of the second NMOS transistor; It is characterized by including the configuration.

In the present invention, when the current slope compensation circuit is implemented in the boost converter, a simple configuration using only a small number of MOS transistors without using an amplifier has an effect of maximizing space efficiency.

In addition, there is no need to consider the characteristics of the amplifier, there is an effect that does not occur errors that can occur when designing the amplifier circuit.

1 is a circuit diagram of a boost converter according to the prior art.
2 is a slope compensation circuit diagram of a boost converter according to the prior art.
3 is a slope compensation circuit diagram of a first embodiment of a boost converter according to the present invention;
4 is a slope compensation circuit diagram of a second embodiment of a boost converter according to the present invention;

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a slope compensation circuit diagram of a first embodiment of a boost converter according to the present invention, as shown therein, the first PMOS transistor MP31 and the second PMOS transistor MP32 constituting a current mirror; A capacitor C31 connected between a power supply terminal VDD and a source terminal of the first PMOS transistor MP31; A current source I _C connected between the common terminal of the drain terminal and the gate terminal of the first PMOS transistor MP31 and the ground terminal; A source resistor RS31 connected between a power supply terminal VDD and a source terminal of the second PMOS transistor MP32 for source degeneration; A source terminal and a drain terminal are connected to both ends of the capacitor C31, and the charging operation of the capacitor C31 is controlled by the turn-on / turn-off operation by the gate pulse GP to control the second PMOS transistor MP32. And a third PMOS transistor MP33 for outputting a target slope compensation current I _slope through the drain terminal of the N-th transistor.

 The operation of the slope compensation circuit according to the first embodiment of the present invention configured as described above is as follows.

A current mirror is configured by the first PMOS transistor MP31 and the second PMOS transistor MP32, and the slope compensation current I _slope is output through the drain terminal of the second PMOS transistor MP32. The capacitor C31 is connected between the power supply terminal VDD and the source terminal of the first PMOS transistor MP31, and the current source I _C is connected between the common terminal of the drain terminal and the gate terminal and the ground terminal. . The source resistor RS31 is connected between the power supply terminal VDD and the source terminal of the second PMOS transistor MP32.

A source terminal and a drain terminal of the third PMOS transistor MP33 are connected to both ends of the capacitor C31, and a gate pulse GP is supplied to the gate terminal thereof. The gate pulse GP is a pulse having the same phase as the gate pulse GP supplied to the gate of the MOS transistor M11 in FIG. 1.

Accordingly, when the gate pulse GP is supplied to the gate of the MOS transistor M11 as 'high' in FIG. 1 and the MOS transistor M11 is turned on, the gate of the third PMOS transistor MP33 is also gated. The pulse GP is supplied 'high' so that the third PMOS transistor MP33 is turned off.

As a result, the charging voltage of the capacitor C31 is increased. In addition, the common gate voltage V _G is lowered due to an increase in the charging voltage of the capacitor C31. As a result, the second PMOS transistor MP32 is turned on, and current flows through the source resistor RS31 and the second PMOS transistor MP32.

However, as the common gate voltage V _G decreases, the voltage across the source resistor RS31 increases so that the slope compensation current I _slope output through the drain terminal of the second PMOS transistor MP32 is timed. Is increased accordingly. That is, the slope compensation current I _slope is a current compensated in FIG. 1 so that the current of the inductor L11 can maintain a constant duty over time.

However, when the gate pulse GP is supplied 'low' to the gate of the MOS transistor M11 and the MOS transistor M11 is turned off, the gate pulse of the gate of the third PMOS transistor MP33 is also applied. GP is supplied 'low' so that the third PMOS transistor M33 is turned on.

Accordingly, the charging voltage of the capacitor C31 is discharged to the current source I _C through the third PMOS transistor M33 and the first PMOS transistor MP31. In addition, the voltage supplied to the source terminal of the second PMOS transistor MP32 is lowered through the source resistor RS31 due to the discharge operation of the capacitor C31. Therefore, the slope compensation current I _slope output through the drain terminal of the second PMOS transistor MP32 is blocked.

As a result, the slope compensation current I _slope output through the drain terminal of the second PMOS transistor MP32 becomes a linear current having a slope compensated type that increases with time.

The slope compensation current of the slope compensation circuit of FIG. 3 is expressed as follows.

Here, 'V _GS1 ' is a case-source voltage of the first PMOS transistor MP31, which is a fixed value regardless of time. Accordingly, the gate voltages V _G of the first and second PMOS transistors MP31 and MP32 may be expressed by Equation 3 below.

Here, the transconductance Gm of the second PMOS transistor MP32 having the source resistance may be expressed by Equation 4 below.

The slope compensation current I _slope of Equation 4 may be expressed by Equation 5 below based on a time function.

However, if the value of the source resistance RS31 in [Equation 5] is much larger than the value of the internal resistance re of the second PMOS transistor MP32 (RS31 >> re), the value of Equation 5 It can be expressed by the following [Equation 6].

As a result, when the values of the source resistors RS21 and RS31 and the capacitance values of the capacitors C21 and C31 are equal to each other in FIGS. 2 and 3, the equations (1) and (6) As can be seen, the same slope compensation current can be obtained. In other words, even when the slope compensation circuit is simply configured as in FIG. 3, the same slope compensation current as in FIG. 2 can be obtained.

4 is a slope compensation circuit diagram according to a second embodiment of the boost converter according to the present invention. As shown in FIG. ; A capacitor C41 connected between the source terminal of the first NMOS transistor MN41 and the ground terminal; A current source I _C connected between the power supply terminal VDD and the common connection point of the drain terminal and the gate terminal of the first NMOS transistor MN41; A source resistor (RS41) connected between a source terminal of the second NMOS transistor (MN42) and a ground terminal for source degeneration; A drain terminal and a source terminal are connected to both ends of the capacitor C41, and the charging operation of the capacitor C41 is controlled by the turn-on / turn-off operation by the gate pulse GP to control the operation of the first mirror. A third NMOS transistor MN43 to be used; A second current mirror is formed between the power supply terminal VDD and the drain of the second NMOS transistor MN42 to output a slope compensation current I _slope corresponding to the driving current of the second NMOS transistor MN42. And a first PMOS transistor MP41 and a second PMOS transistor MP42.

NMOS transistors NM41-NM43 are used in the second embodiment, whereas PMOS transistors MP31-MP33 are used in the first embodiment. The operation of the second embodiment will be described below. .

The first current mirror is formed of the first NMOS transistor MN41 and the second NMOS transistor MN42, and the current source I is connected between the drain terminal of the first NMOS transistor MN41 and the power supply terminal VDD. _C ) is connected and a capacitor C41 is connected between the source terminal and the ground terminal. The first PMOS transistor MP41 and the second PMOS transistor MP42 are configured to output a slope compensation current I _slope between the drain terminal of the second NMOS transistor MN42 and the power supply terminal VDD. The second current mirror is connected, and a source resistor RS41 is connected between the source terminal and the ground terminal.

A drain terminal and a source terminal of the third NMOS transistor MN43 are connected to both ends of the capacitor C41, and the charging operation of the capacitor C41 is controlled by the turn-on / turn-off operation by the gate pulse GP. . The phase of the gate pulse GP is opposite to the phase of the gate pulse GP supplied to the gate of the MOS transistor M11 in FIG. 1.

Accordingly, when the gate pulse GP is supplied 'high' to the gate of the MOS transistor M11 in FIG. 1, the gate of the third NMOS transistor MP43 is also gated when the MOS transistor M11 is turned on. The pulse GP is supplied 'low' so that the third NMOS transistor MN43 is turned off.

As a result, the charging voltage of the capacitor C41 is increased. As the charging voltage of the capacitor C41 increases, the gate voltage V _G of the first NMOS transistor MN41 and the second NMOS transistor MN42 constituting the first mirror is increased. Therefore, the amount of current flowing through the first PMOS transistor MP41, the second NMOS transistor MN42, and the source resistor RS41 is increased. As a result, the slope compensation current I _slope output through the drain terminal of the second PMOS transistor MP42 constituting the first PMOS transistor MP41 and the second current mirror increases. Here, the slope compensation current I _slope means a current compensated such that the output current of the inductor L11 linearly changes with respect to the change of the input current in FIG. 1.

However, when the gate pulse GP is supplied 'low' to the gate of the MOS transistor M11 and the MOS transistor M11 is turned off, the gate pulse of the gate of the third PMOS transistor MP33 is also applied. GP) is supplied 'high' so that the third NMOS transistor MN43 is turned on.

Accordingly, the charging voltage of the capacitor C41 is discharged to the ground terminal through the third NMOS transistor MN43. As a result, the gate voltage V _G of the first NMOS transistor MN41 and the second NMOS transistor MN42 is lowered, and the second NMOS transistor MN42 is turned off. Therefore, the current flowing through the first PMOS transistor MP41, the second NMOS transistor MN42, and the source resistor RS41 is blocked. As a result, the slope compensation current I _slope output through the drain terminal of the second PMOS transistor MP42 is blocked.

Also for the slope compensation circuit of the second embodiment of the present invention as shown in FIG. 4, Equations 2 to 6 are expressed in the same manner as in the first embodiment. Therefore, even if the slope compensation circuit is simply configured as shown in FIG. 4, the same slope compensation current as in FIG. 2 can be obtained.

Although the preferred embodiment of the present invention has been described in detail above, the scope of the present invention is not limited thereto, and may be implemented in various embodiments based on the basic concept of the present invention defined in the following claims. Such embodiments are also within the scope of the present invention.

10:
11: current sensing unit
12: slope compensation circuit
13: summer
14: error amplifier
15: error comparator
16: clock signal generator
17: control logic section
18: gate driver

Claims (5)

An inductor for charging electrical energy from an input voltage;
A MOS transistor for controlling charging of the inductor by a switching operation;
In the slope compensation circuit of the boost converter comprising a control unit for controlling the driving of the MOS transistor to output a DC voltage as a target, and to compensate the slope of the output current,
The control unit,
A first PMOS transistor and a second PMOS transistor constituting the current mirror;
A capacitor connected between a power supply terminal and a source terminal of the first PMOS transistor;
A current source connected between the common terminal of the drain terminal and the gate terminal of the first PMOS transistor and the ground terminal;
A source resistor connected between a power supply terminal and a source terminal of the second PMOS transistor;
A source terminal and a drain terminal are connected to both ends of the capacitor, and the charging operation of the capacitor is controlled by a turn-on / turn-off operation by a gate pulse, and a target slope compensation current is passed through the drain terminal of the second PMOS transistor. And a slope compensating circuit comprising a third PMOS transistor for outputting the slope compensation circuit.
The slope compensation circuit of claim 1, wherein the phase of the gate pulse supplied to the gate of the third PMOS transistor is the same as the phase of the gate pulse supplied to the gate of the MOS transistor.
The slope compensating circuit of claim 1, wherein the slope compensating current is a current compensated such that an output current of the inductor changes linearly with a change in an input current.
An inductor for charging electrical energy from an input voltage;
A MOS transistor for controlling charging of the inductor by a switching operation;
In the slope compensation circuit of the boost converter comprising a control unit for controlling the driving of the MOS transistor to output a DC voltage as a target, and to compensate the slope of the output current,
The control unit,
A first NMOS transistor and a second NMOS transistor constituting the first current mirror;
A capacitor connected between the source terminal and the ground terminal of the first NMOS transistor;
A current source connected between a power supply terminal and a common connection point of the drain terminal and the gate terminal of the first NMOS transistor;
A source resistor connected between the source terminal and the ground terminal of the second NMOS transistor;
A third NMOS transistor having a drain terminal and a source terminal connected to both ends of the capacitor and controlling a charging operation of the capacitor by a turn-on / turn-off operation by a gate pulse to control the operation of the first mirror;
A first PMOS transistor and a second PMOS transistor configured to output a slope compensation current corresponding to a driving current of the second NMOS transistor by forming a second current mirror between a power supply terminal and a drain of the second NMOS transistor. A slope compensation circuit of a boost converter, comprising a configured slope compensation circuit.
The slope compensation circuit of claim 4, wherein the phase of the gate pulse supplied to the gate of the third NMOS transistor is the same as the phase of the gate pulse supplied to the gate of the MOS transistor.

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