KR20120025358A - Method and apparatus for transmitting and receiving data in a communication system using linear block code - Google Patents

Abstract

PURPOSE: A method and an apparatus for transmitting and receiving data in a communication system using a linear block code are provided to improve the performance of an LDPC code by improving the reliability of bits having low error correcting capability among bits constituting LDPC codes. CONSTITUTION: A transmitter(500) comprises a coder(511), an interleaver(513), and a signal constellation bit mapping unit(515), and a modulator(517). A receiver(550) comprises a demodulator(557), a signal constellation bit demapping unit(555), a deinterleaver(553), and a decoder(551). The interleaver outputs the interleaved code to the signal constellation bit mapping unit. The modulator modulates the signal outputted from the bit mapping unit into a predetermined mode.

Description

TECHNICAL AND APPARATUS FOR TRANSMITTING AND RECEIVING DATA IN A COMMUNICATION SYSTEM USING LINEAR BLOCK CODE

The present invention relates to an apparatus and method for transmitting and receiving data in a communication system, and more particularly, to an apparatus and method for transmitting and receiving data in a communication system using a linear block code.

In general, the general process of data transmission and reception in a communication system is as follows. That is, data generated from an information source of a transmitter is wirelessly transmitted through a channel through source coding, channel coding, interleaving, and modulation. In addition, the receiving side receives the radio-transmitted signal to perform demodulation, deinterleaving, channel decoding, and source decoding.

However, in a communication system, signal distortion occurs due to various noise, fading, and inter-symbol interference (ISI) of a channel. In particular, high-speed digital communication systems that require high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and the portable Internet, are essential to overcome noise, fading, and signal distortion caused by ISI. The channel coding and interleaving correspond to the representative techniques.

Interleaving means that damaged parts of bits to be transmitted are distributed to several places instead of being concentrated in one place, thereby minimizing data errors caused by passing through fading channels, minimizing data transmission loss, and It is used to increase the effect.

In addition, channel coding is widely used as a method for improving communication reliability by allowing a receiver to identify and efficiently restore noise, fading, and signal distortion caused by ISI. Codes used for channel coding are called error-correcting codes (ECCs) in the sense of error correction, and various types of error correction codes have been actively studied.

A generally known linear block code is a low density parity check code (LDPC code). The present invention to be described later will be described later based on the LDPC code of the linear block code and a brief description of the LDPC code will be described below.

The LDPC code is generally defined as a parity-check matrix and can be expressed by using a bipartite graph collectively referred to as a Tanner graph. Here, the bipartite graph means that the vertices constituting the graph are divided into two different types. In the case of the LDPC code, the bipartite graph is composed of vertices called variable nodes and check nodes. Is expressed. Here, the variable node corresponds one-to-one with the coded bits.

의 예시도이다. 도 1에서는 4개의 행(row)과 8개의 열(column)로 구성된 LDPC 부호의 패리티 검사 행렬을 가정한 것이다. 도 1의 행렬은 8개의 열을 가짐으로써 길이가 8인 부호어(codeword)를 생성하는 LDPC 부호를 나타낸다. 상기 패리티 검사 행렬 H₁과 8개의 비트들로 구성된 부호어

은 아래와 같은 수학식 1의 관계를 가지고 있다.Hereinafter, a graph representation method of the LDPC code will be described with reference to FIGS. 1 and 2. 1 is a parity check matrix of an LDPC code.

An illustration of the. In FIG. 1, a parity check matrix of an LDPC code composed of four rows and eight columns is assumed. The matrix of FIG. 1 shows an LDPC code having 8 columns to generate a codeword of length 8. A codeword consisting of the parity check matrix H ₁ and eight bits

Has the relationship of Equation 1 below.

는 패리티 검사 행렬 H의 열을 의미한다. 그러므로 패리티 검사 행렬의 각각의 열은 각각의 부호어 비트와 관계가 있다고 할 수 있다. 즉, 패리티 검사 행렬의

번째 열

은 부호어의

번째 비트

와 관계가 있다. 그러므로 각각의 열

의 0이 아닌 원소의 개수 및 위치는 부호 비트

의 성능과 관계가 있다. remind

Denotes a column of the parity check matrix H. Therefore, it can be said that each column of the parity check matrix is related to each codeword bit. That is, the parity check matrix

Th column

Is a codeword

Bit

Has a relationship with Therefore each column

The number and position of the nonzero elements of the sign bit

Is related to performance.

2 is a graphical representation of the parity check matrix H of the LDPC code. That is, it is a figure which shows the Tanner graph corresponding to H of FIG. Referring to FIG. 2, the Tanner graph of the LDPC code includes eight variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), x ₈ (216) and four check nodes (218, 220, 222, 224). Here, the i th column and the j th row of the parity check matrix H of the LDPC code correspond to the variable nodes x _i and j th check nodes, respectively. In addition, a value of 1, i.e., a non-zero value of a point where the i-th column and the j-th row of the parity check matrix H of the LDPC code intersect, means that the variable nodes x _i and j on the Tanner graph as shown in FIG. An edge exists between the first test node.

In the Tanner graph of the LDPC code, the degree of the variable node and the check node means the number of line segments connected to each node, which is determined in the column or row corresponding to the node in the parity check matrix of the LDPC code. It is equal to the number of nonzero entries. For example, the variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), and x ₇ (214 in FIG. 2 above. ), the order of x ₈ (216) is 4, 3, 3, 3, 2, 2, 2, 2, respectively, in order, and the order of test nodes 218, 220, 222, and 224 is 6 in order, respectively. , 5, 5, 5. In addition, the number of non-zero elements in each column of the parity check matrix H1 of FIG. 1 corresponding to the variable nodes of FIG. 2 is equal to the above-described orders 4, 3, 3, 3, 2, 2, 2, 2, and 2. And the number of non-zero elements in each row of the parity check matrix H1 of FIG. 1 corresponding to the check nodes of FIG. 2 in the order of the above orders 6, 5, 5, and 5 Matches.

As described above, each coded bit has a relation with a column of a parity check matrix, and has a one-to-one correspondence with a variable node on a Tanner graph. In addition, the order of the variable node that has a one-to-one correspondence with the coded bit is referred to as the order of the coded bit.

In addition, LDPC codes are known to have better decoding performance than codeword bits having higher orders than codeword bits having lower orders. This is because the decoding performance can be improved as the higher order variable node acquires more information through iterative decoding than the low order variable node. However, this alone cannot accurately determine the performance of codeword bits. We need to look at other properties such as the cycle of the variable node on the Tanner graph that maps one-to-one with each codeword bit.

3 shows an example of a parity check matrix of an LDPC code having the specific structure. The LDPC code hereinafter is code d used in DVB-S2, DVB-T2, and DVB-NGH which are European broadcasting systems. It is a systematic structure in which a codeword includes an information word. Hereinafter, for convenience of description, the present invention will be described based on the parity check matrix of FIG. 3, but the present invention is not limited to the parity check matrix of FIG. 3. It is also not limited to DVB-S2, DVB-T2, and DVB-NGH.

개의 column으로 구성되며, 패리티 파트는

개의 column으로 구성된다. 상기 패리티 검사 행렬의 row의 개수는 패리티 파트의 column의 개수와 동일한

로 구성된다. Referring to FIG. 3, the parity check matrix includes an information word part and a parity part, and the information word part is

Consists of two columns, the parity part

It consists of two columns. The number of rows of the parity check matrix is equal to the number of columns of the parity part.

It consists of.

은 LDPC 부호어의 길이,

은 정보어의 길이,

은 패리티 파트의 길이를 의미한다. 상기 부호어의 길이라 함은 부호어를 구성하는 비트들의 개수를 의미한다. 또한 정보어의 길이라 함은 정보어를 구성하는 비트들의 길이를 의미한다. 그리고

이 성립하도록 정수

과

를 결정한다. 이때,

도 정수가 되도록 한다.

Is the length of the LDPC codeword,

Is the length of the information word,

Means the length of the parity part. The length of the codeword means the number of bits constituting the codeword. In addition, the length of the information word means the length of the bits constituting the information word. And

Integer to make

and

. At this time,

Is also an integer.

번째 열(column)부터

번째 열까지의 무게 1의 위치는 이중 대각(dual diagonal) 구조를 가진다. 따라서, 상기 패리티 비트에 대응되는 열의 차수(degree)는 상기

번째 열을 제외하고 모두 2이며, 상기

번째 열의 차수는 1 임을 알 수 있다. The part corresponding to the parity bit in the parity check matrix of FIG.

From the first column

The position of weight 1 up to the first row has a dual diagonal structure. Therefore, the degree of the column corresponding to the parity bit is

2 except for the 1st column, and above

It can be seen that the order of the first column is 1.

번째 열까지의 구조를 이루는 규칙은 다음과 같다. Referring to FIG. 3, a part corresponding to the information word part in the parity check matrix, that is, from the 0th column

The rules forming the structure up to the first column are as follows.

개의 열을

개씩 그룹화(grouping)하여, 총

개의 열 그룹(column group)을 생성한다. 각 열 그룹에 속해있는 각각의 열을 구성하는 방법은 하기 규칙 2를 따른다. <Rule 1>: Corresponds to the information word in the parity check matrix

Columns

Grouped one by one,

Create two column groups. How to configure each column belonging to each column group follows the rule 2.

번째

열 그룹의 각 0 번째 열에서의 1의 위치를 결정한다. 여기서, 각

번째 열 그룹의 0 번째 열의 차수를

라 할 때, 1이 있는 각 행의 위치를

이라 가정하면,

번째 열 그룹 내의

번째 열에서 1이 있는 행의 위치

는 하기 수학식 2과 같이 정의된다. <Rule 2>: First

th

Determine the position of 1 in each 0th column of the row group. Where

Order of the 0th column of the 1st column group

Is the position of each row

Assuming that

Within the first column group

Position of row with 1 in the first column

Is defined as in Equation 2 below.

번째

열 그룹 내에 속하는 열들의 차수는 모두

로 일정함을 알 수 있다. 이하에서는 상기 규칙에 따라 패리티 검사 행렬에 대한 정보를 저장하고 있는 LDPC 부호의 구조를 쉽게 이해하기 위하여 구체적인 예를 살펴본다. According to rule 1 and rule 2 above

th

The orders of the columns within a column group are all

It can be seen that the constant. Hereinafter, a specific example will be described to easily understand the structure of the LDPC code that stores information about the parity check matrix according to the above rule.

이며, 3개의 열 그룹의 0 번째 열에 대한 1이 있는 행의 위치 정보는 다음과 같은 수열들로 나타낼 수 있다. 여기서 이 수열들을 "무게-1 위치 수열(weight-1 position sequence)"이라 부른다. As a specific example

The positional information of a row having 1 for the 0th column of the 3 column group may be represented by the following sequences. These sequences are referred to herein as "weight-1 position sequences."

The weight-1 position sequence for the position of the row 1 with respect to the 0th column of each column group may be expressed only as a sequence for each column group as follows for convenience.

1 2 8 10

0 9 13

0 14

번째 무게-1 위치 수열은

번째 열 그룹에 대한 1이 있는 행의 위치 정보를 순차적으로 나타낸 것이다.
That is

First weight-1 position sequence

Positional information of a row with 1 for the first column group is sequentially displayed.

So far, we have discussed the LDPC code. Hereinafter, a signal constellation in the case of applying a quadrature amplitude modulation (QAM) method, which is a higher order modulation method commonly used in a communication system, will be described. The modulated symbol in QAM is composed of a real part and an imaginary part, and various modulation symbols may be configured by different sizes and codes of the real part and the imaginary part. In order to examine the characteristics of the QAM, it will be described together with the QPSK modulation scheme.

4A is a schematic diagram of a signal constellation of a general Quadrature Phase Shift Keying (QPSK) modulation scheme.

y ₀ determines the sign of the real part and y ₁ determines the sign of the imaginary part. That is, if y ₀ is 0, the real part sign is positive (plus: +), and if y ₀ is 1, the real part sign is negative (minus:-). In addition, if y ₁ is 0, the sign of the imaginary part is positive (plus: +), and if y ₁ is 1, the sign of the imaginary part is negative (minus:-). Since y ₀ and y ₁ are the sign bits representing the sign of the real part and the imaginary part, the probability of error occurrence of y ₀ and y ₁ is the same. Therefore, in the QPSK modulation method, (y ₀ , y corresponding to one modulation signal) ₁ ) The reliability of each bit is the same. Here, when y _{0, q and} y _{1, q} , the subscript second index q means the qth output of the modulation signal configuration bit.

4B is a schematic diagram of a signal constellation of a typical 16-QAM modulation scheme. The meaning of (y ₀ , y ₁ , y ₂ , y ₃ ) corresponding to one modulation signal bit is as follows. Bits y ₀ and y ₂ determine the sign and magnitude of the real part, respectively, and bits y ₁ and y ₃ each determine the sign and size of the imaginary part. In other words, y ₀ and y ₁ determine the sign of the real and imaginary parts of the signal, and y ₂ and y ₃ determine the magnitudes of the real and imaginary parts of the signal. Since it is easier to determine the sign than to determine the magnitude of the modulated signal, the probability of error for y ₂ and y ₃ is higher than y ₀ and y ₁ . Thus, the probability or reliability that the error of the bits will not occur is in the order of R (y ₀ ) = R (y ₁ )> R (y ₂ ) = R (y ₃ ). Where R (y) represents the reliability for bit y. Unlike QPSK, the modulation signal configuration bits (y ₀ , y ₁ , y ₂ , y ₃ ) of the QAM have different characteristics of reliability of each bit.

In the 16-QAM modulation method, two bits of the four bits constituting the signal determine the sign of the real part and the imaginary part of the signal, and two bits need to represent the magnitudes of the real part and the imaginary part of the signal (y ₀ , y ₁ , y ₂ , y ₃ ) and the role of each bit may vary.

4C is a schematic diagram of a signal constellation of a general 64-QAM modulation scheme. Here, bits y ₀ , y ₂ and y ₄ of (y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ ) corresponding to one modulation signal bit determine the sign and magnitude of the real part, and y ₁ , y ₃ and y ₅ determine the sign and magnitude of the imaginary part. At this time, y ₀ and y ₁ determine the sign of the real part and the imaginary part, respectively, and y _2, y ₃ , y _4, y ₅ determine the size of the real part and the imaginary part, respectively. The reliability of y ₀ and y ₁ is higher than the reliability of y _2, y ₃ , y _4, y ₅ because it is easier to determine the sign than to determine the magnitude of the modulated symbol. y _2, y ₃ is determined depending on whether the size of the modulated symbol is greater than or less than _4, y _4, y ₅ is determined whether the size of the modulated symbol is close to 4 and 0 based on 2, or It depends on whether it is close to 4 or 8 based on 6. Therefore _, the size of the crystal range of y _2, y ₃ is 4, and the crystal range of y _4, y ₅ is 2. Therefore _, the reliability of y _2, y ₃ is higher than that of y _4, y ₅ . To sum it up, the probability that each bit of error does not occur, that is, the reliability is R (y ₀ ) = R (y ₁ )> R (y ₂ ) = R (y ₃ )> R (y ₄ ) = R (y ₅ ).

In the 64-QAM modulation scheme, two bits of the six bits constituting the signal determine the sign of the real part and the imaginary part of the signal, and four bits need only indicate the magnitude of the real part and the imaginary part of the signal. Thus, the order of (y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ ) and the role of each bit can change. In addition, in the case of signal constellations of 256-QAM or more, the role and reliability of the modulation signal configuration bits are changed in the same manner as described above. That is, if one modulation signal bit is (y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ ), R (y ₀ ) = R (y ₁ )> R ( y ₂ ) = R (y ₃ )> R (y ₄ ) = R (y ₅ )> R (y ₆ ) = R (y ₇ )

However, conventionally, when performing interleaving / deinterleaving in a communication system using an LDPC code, an arbitrary interleaving / deinterleaving scheme is used or a variable of an LDPC code regardless of a reliability characteristic of an LDPC code or a modulation code component bit of a higher order modulation. By using the interleaving / deinterleaving and signal constellation bit mapping schemes considering only the order of nodes or check nodes, there is a problem in that distortion of a signal transmitted through a channel cannot be minimized.

Also, in one system, multiple parity check matrices are used to support multiple code rates. At this time, the degree distribution characteristic varies for each code rate, and the signal constellation bit mapping method must be changed according to the distribution characteristic. However, if too many bit mapping methods are used, the complexity of the system is increased. Therefore, there is a need for a method that can use the same bit mapping method as much as possible.

Accordingly, the present invention provides a transmission and reception apparatus and method for reducing signal distortion in a communication system using an LDPC codeword.

The present invention also provides an interleaving apparatus and method for improving the performance of the LDPC codeword in a communication system using the LDPC codeword.

The present invention also provides a signal constellation bit mapping apparatus and method for improving the performance of an LDPC codeword in a communication system using the LDPC codeword.

The present invention for solving the above problems is a data transmission method of a communication system using a low density parity check (LDPC) matrix, when the information data bits are input, by encoding the information data bits to LDPC codeword An LDPC encoding process for generating a signal, an interleaving process for the LDPC codeword, a signal constellation bit mapping process for outputting a mapping signal by mapping the interleaved LDPC codeword with signal constellation bit mapping, and a high order And a modulating process of modulating and outputting a modulated signal, and an RF process of RF processing the modulated signal and transmitting the RF through a transmitting antenna.

Effects according to the present invention are as follows.

The present invention can maximize the performance of the LDPC codeword in a communication system using the LDPC codeword.

In addition, the present invention improves the decoding performance of the LDPC code. In addition, the present invention improves reliability of bits having low error correction capability among the bits constituting the LDPC code.

In addition, the present invention can improve the reliability of data transmission and reception by increasing the performance of the link, especially in a wireless channel environment where the link performance is likely to be degraded due to noise, fading, and inter-symbol interference (ISI). In addition, the present invention enables the high-speed communication by transmitting and receiving a reliable LDPC code by reducing the error probability of the signal in the entire communication system.

1 is an exemplary diagram of a parity check matrix H ₁ of an LDPC code;
2 is a graph representation of a parity check matrix H ₁ of an LDPC code;
3 is an exemplary diagram of a parity check matrix of an LDPC code having a specific structure;
4A is a schematic diagram of a signal constellation of a typical QPSK modulation scheme;
4b is a schematic diagram of a signal constellation of a typical 16-QAM modulation scheme;
4C is a schematic diagram of a signal constellation of a general 64-QAM modulation scheme;
5 is a configuration diagram of a communication system using an LDPC code according to an embodiment of the present invention;
6A through 6D are diagrams illustrating an interleaver and a signal constellation bit mapper according to an embodiment of the present invention;
7A and 7B are exemplary views illustrating an operation of an interleaver according to an embodiment of the present invention.
8A and 8B are exemplary diagrams illustrating an interleaver and a bit mapping method according to an embodiment of the present invention;
9 is a block diagram of a transceiver according to an embodiment of the present invention;
10 is a block diagram of a transceiver according to another embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the preferred embodiment of the present invention. In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

5 is a configuration diagram of a communication system using an LDPC code according to an embodiment of the present invention. Hereinafter, a configuration of a communication system using an LDPC code according to an embodiment of the present invention will be described with reference to FIG. 5.

The transmitter 500 of the present invention includes an encoder 511, an interleaver 513, and a bitmap into constellation or signal constellation bit mapping 515 (hereinafter referred to as "bit mapping"). Group ”, a modulator 517. The receiver 550 also includes a demodulator 557 and a signal constellation bit demapping 555 (hereinafter abbreviated as " bit demapping "). An interleaver 553 and a decoder 551 are included.

First, the operation of the transmitter and the receiver of the present invention will be briefly described with reference to FIG. 5, and the configuration and operation of the interleaver and bit mapper proposed by the present invention will be described in detail with reference to FIG. 6.

가 입력되면

는 부호기(511)로 전달되고, 부호기(511)는 상기 정보 데이터 비트들을 소정의 방식으로 부호화하여 부호어(codeword)

를 생성하고 이를 인터리버(513)로 출력한다. 상기 부호의 부호율은

이다.First, an information data bit stream is transmitted to the transmitter 500.

Is entered

Is passed to the encoder 511, and the encoder 511 encodes the information data bits in a predetermined manner.

Generates and outputs it to the interleaver 513. The code rate of the code is

to be.

The interleaver 513 interleaves the codeword output from the encoder 511 in a predetermined manner and outputs the codeword to the signal constellation bit mapper 515. The interleaving operation of the interleaver 513 is performed according to the interleaving scheme proposed by the present invention. A detailed description of the interleaving scheme will be given later.

를 소정의 방식으로 신호 성좌 비트 매핑하여 변조기(517)로 출력한다. 상기 비트 매핑기(515)는 본 발명에서 제안하는 매핑 방식에 따라 매핑된다. 상기 매핑 방식은 상기

의 차수들의 분포 특성에 따라 변조 심볼을 구성하는 비트들에 매핑하는 것으로서 그 상세한 설명은 후술하기로 한다.The bit mapper 515 is a bit output from the interleaver 513, that is, the interleaved LDPC codeword.

The signal constellation bit mapping is performed in a predetermined manner and output to the modulator 517. The bit mapper 515 is mapped according to the mapping scheme proposed by the present invention. The mapping method is

Mapping to bits constituting the modulation symbol according to the distribution characteristics of the order of the will be described later.

를 변조할 때 비트 오류율(bit error rate : BER) 또는 부호어 오류율(Frame error rate : FER)을 최소화할 수 있도록 인터리빙과 비트 매핑을 수행하여 성능을 높이게 된다.The modulator 517 modulates the signal output from the bit mapper 515 in a predetermined manner and transmits the modulated signal through a transmission antenna Tx. In the interleaver 513 and the bit mapper 515 of the present invention, the modulator 517

In order to minimize the bit error rate (BER) or the code error rate (FER), the interleaving and bit mapping are performed to improve the performance.

Hereinafter, the interleaver 513 and the bit mapper 515 are designed such that a relationship between a codeword bit, which is an input signal of the interleaver, and a modulation signal component bit, which is an output signal of the bit mapper, satisfies the following rules. The number of bits of the codeword is n, and it is assumed that 2 ^2m -QAM modulation scheme is used.

Rule 3) Different bit mapping methods should be used depending on the ratio of low order bits.

Rule 4) When the ratio of low order bits is large, the highest order bits are composed of low reliability modulation signal bits.

Rule 5) Ensure that the cycle between the codeword bits constituting the same modulated signal is as large as possible.

Rule 6) When using multiple parity check matrices, consider bit mapping or changing the position of the columns of the parity check matrix so that the same bit mapping method can be used as much as possible.

In case of Rule 3), there is a disadvantage that an optimal mapping method should be used according to each code rate. Therefore, as in Rule 6, the minimum bit mapping method should be used considering the method of optimizing the mapping method while changing the position of the information word part of the parity check matrix. Detailed description will be made later.

In case of rule 5), in determining the DEMUX of FIGS. 6A to 6D, the input bits of the DEMUX are first determined whether to be mapped to the MSB or the LSB of which the modulation signal has high reliability, and a plurality of modulation signals constituting the MSB. When selecting among the bits of, consider the cycle between the codeword bits.

By configuring the relationship between the LDPC codeword bits and the modulation signal configuration bits as described above, the decoding performance of the LDPC codeword can be improved. The main feature of the rule is that unlike the conventional method, the degree distribution of the parity check matrix is considered, and the position of the columns of the parity check matrix is changed in order to use the mapping method using the minimum number while considering the optimal performance. Consider the mapping method at the same time. The distribution of the parity check matrix can be changed according to the code rate and the length of the code.

The reason why the mapping method to which the above rule is applied can obtain excellent performance is described in detail as follows.

The low order bits in the LDPC codeword can be improved by mapping them to a small but reliable modulation signal component bit in the decoding process. However, if all low order bits are mapped to high reliability modulated signal component bits, the relatively high order bits may be mapped to low reliability modulated signal component bits, which may increase the influence of low reliability. Therefore, it is possible to improve performance by mapping only a part of the configuration bits having high reliability to mapping the modulation signal component bits having high reliability in all the lower orders. However, only mapping modulation signal component bits having low reliability to low order bits may cause serious degradation in the error correction capability of the low order bits, resulting in an error floor. do. Therefore, the ratio of mapping to the low reliability component bits among the lower order bits should be carefully selected, which may vary depending on the order distribution of the parity check matrix.

Meanwhile, the receiver 550 receives the signal transmitted from the transmitter 500 and outputs the signal through the reverse process of the transmitter 500. That is, the signal input to the receiver 550 through the receiving antenna (Rx. Ant) is transmitted to the demodulator 557. The demodulator 557 demodulates the received signal in a demodulation scheme corresponding to the modulation scheme of the modulator 517 of the transmitter 500 and outputs the demodulated signal to the bit demapper 555. The bit demapper 555 demaps the signal output from the demodulator 557 according to the mapping scheme performed by the bit mapper 515 of the transmitter 500 and then outputs the demultiplexer 553 to the deinterleaver 553. . The deinterleaver 553 deinterleaves the signal output from the bit demapper 555 to correspond to the interleaving method applied by the interleaver 513 of the transmitter 500 and then outputs the deinterleaver to the decoder 551. The decoder 551 decodes the deinterleaved signal by a decoding method corresponding to the method applied by the encoder 511 of the transmitter 500 to restore the final information data bit.

Meanwhile, in FIG. 5, the signal output from the modulator 517 is RF-processed by an RF transmitter (not shown in FIG. 5) for a separate radio frequency (“RF”) signal transmission process. A signal transmitted through the transmission antenna and similarly received at the receiving antenna is RF processed by an RF receiver (not shown in FIG. 5) for RF signal reception processing and input to the demodulator 557.

The transmitter of the present invention is characterized by an interleaver 513 and a bit mapper 515 using an unequal reliability characteristic of a higher-order modulation scheme, and the receiver of the present invention has an unequal reliability characteristic of a higher-order modulation scheme. A deinterleaver 553 and a bit demapper 555 are used. Hereinafter, operations of the interleaver and the signal constellation bit mapper proposed by the present invention will be described in detail with reference to FIG. 5.

6A to 6D are diagrams illustrating an interleaver and a signal constellation bit mapper according to an embodiment of the present invention.

6A through 6D, the bit mapper 415 of FIG. 5 may be configured as a demultiplexer DEMUX. FIG. 6A illustrates a method using a QPSK modulated signal, FIG. 6B illustrates a method using a 16-QAM modulated signal, FIG. 6C illustrates a method using a 64-QAM modulated signal, and FIG. 6D illustrates using an arbitrary modulation scheme. Each method is shown. Hereinafter, the four methods will be described together.

를 출력한다. 그리고 인터리빙된 신호

는 각각 대응하는 역다중화부(621, 641, 661, 682)로 입력되어 다수의 스트림으로 분리된다. 즉, 도 6a는 QPSK의 경우이므로 4개의 스트림으로 분리되고, 도 6b는 16-QAM의 경우이므로 8개의 스트림으로 분리되고, 도 6c는 64-QAM의 경우이므로 12개의 스트림으로 분리된다. 즉, 상기 도 6의 구성을 통해 각각 입력된 신호들은 해당하는 방식에 따라 인터리빙된 후 변조 신호를 구성하는 비트의 두 배수의 스트림으로 분리되어 출력된다. 이는 변조 신호를 구성하는 비트의 수 만큼 스트림을 구성하는 방법에 비하여, 상기 방법이 부호어 비트들을 변조 신호를 구성 하는 비트들에 매핑 하는 방법을 다양하게 할 수 있으므로 성능의 향상을 가져 올 수 있다.When the coded signal x is input to the corresponding bit interleavers 611, 631, 651, and 681 (hereinafter referred to as "interleaver") according to each modulation scheme, the interleaved signal is interleaved to interleave the coded signal.

. And interleaved signals

Are respectively input to the corresponding demultiplexers 621, 641, 661, and 682 to be divided into a plurality of streams. That is, FIG. 6A is divided into four streams because of the case of QPSK, and FIG. 6B is divided into eight streams because of the case of 16-QAM, and FIG. 6C is divided into 12 streams because of the case of 64-QAM. That is, the signals input through the configuration of FIG. 6 are interleaved according to a corresponding scheme, and are separated into two streams of bits constituting a modulated signal. This method can improve performance because the method can vary the method of mapping the codeword bits to the bits constituting the modulated signal, as compared to the method of constructing the stream by the number of bits constituting the modulated signal. .

Each of the demultiplexers 621, 641, 661, and 682 receives one stream and divides the stream into a plurality of streams to form bits of a modulated signal. In the present invention, interleaved codewords are used among the bits of the modulated signal. It is important which bits make up what. Hereinafter, a case in which a 16QAM modulated signal is used as shown in FIG. 6B during the operations of the demultiplexers 621, 641, 661, and 682 will be described in detail. In addition, the case of using the 64QAM modulated signal as shown in Figure 6c will be described in detail. When other modulation signals are used, the description can be omitted in the same manner as the 16QAM modulation signal.

이 인터리버(631)에 입력된다. 인터리빙 방식은 각각의 변조 신호의 비트 매핑 방식과, LDPC 부호의 비트별 차수 분포 및 신호 성좌의 비트별 신뢰도를 동시에 고려하여 결정된다. 그러면 이에 대하여 좀 더 상세히 살펴보기로 한다.LDPC codeword bits first

This is input to the interleaver 631. The interleaving method is determined in consideration of the bit mapping method of each modulation signal, the bit-order order distribution of the LDPC code, and the bit-by-bit reliability of the signal constellation. Let's take a closer look at this.

은 역다중화부(641)로 입력되어 변조 신호를 구성하는 비트 수로 역다중화되어 출력된다. 즉, 16-QAM의 경우 변조 신호는 4개의 비트로 구성되므로 역다중화부(641)의 입력 비트들은 4*2=8개의 비트로 역다중화되어 출력된다. 이때 연속적으로 입력되는 8개의 비트들

과 신호를 구성하는

와의 매핑 관계에 따라 상기 비트 매핑 방법이 결정된다. 이하에서 본 발명에 따른 인터리빙 방식과 비트 매핑 방법을 상세한 설명한다. 또한 본 발명이 제안하는 인터리버와 비트 매핑기는 앞에서 언급한 규칙에 의하여 설계된 것이다. Output Bits of Interleaver 631

The demultiplexer is input to the demultiplexer 641 and demultiplexed to the number of bits constituting the modulated signal. That is, in the case of 16-QAM, since the modulation signal is composed of four bits, the input bits of the demultiplexer 641 are demultiplexed into 4 * 2 = 8 bits and output. 8 bits that are input continuously

And make up the signal

The bit mapping method is determined according to the mapping relationship with. Hereinafter, the interleaving method and the bit mapping method according to the present invention will be described in detail. In addition, the interleaver and the bit mapper proposed by the present invention are designed according to the aforementioned rules.

에 대하여

는 도 4b의 16-QAM 변조 방식의 (

)에 매핑 된다. 즉,

가 하나의 16-QAM 변조 신호를 구성하며 각각 (

) = (

) 매핑 되며,

가 하나의 16-QAM 변조 신호를 구성하며 각각 (

) = (

) 매핑 된다. 즉, 역다중화부(641)의 출력 비트

중

가

번째 변조 신호의 실수부를 구성하며

가

번째 변조 신호의 허수부를 구성함을 알 수 있다. 또한

중

가

번째 변조 신호의 실수부를 구성하며

가

번째 변조 신호의 허수부를 구성함을 알 수 있다. In Figure 6, the number of LDPC codeword bits

about

Is the 16-QAM modulation scheme of FIG.

). In other words,

Constitute one 16-QAM modulated signal, each (

) = (

), And

Constitute one 16-QAM modulated signal, each (

) = (

). That is, the output bit of the demultiplexer 641

medium

end

The real part of the first modulated signal

end

It can be seen that the imaginary part of the first modulated signal is configured. Also

medium

end

The real part of the first modulated signal

end

It can be seen that the imaginary part of the first modulated signal is configured.

과 신호를 구성하는

와의 매핑 관계에 따라 상기 비트 매핑 방법이 결정된다. 이하에서 본 발명에 따른 인터리빙 방식과 비트 매핑 방법을 상세한 설명한다. 또한 본 발명이 제안하는 인터리버와 비트 매핑기는 앞에서 언급한 규칙에 의하여 설계된 것이다.In the case of 64-QAM, since the modulation signal is composed of 6 bits, the input bits of the demultiplexer 661 are demultiplexed into 6 * 2 = 12 bits and output. 12 bits that are continuously input at this time

And make up the signal

The bit mapping method is determined according to the mapping relationship with. Hereinafter, the interleaving method and the bit mapping method according to the present invention will be described in detail. In addition, the interleaver and the bit mapper proposed by the present invention are designed according to the aforementioned rules.

,

는 도 4c의 64-QAM 변조 방식의 (

)에 매핑 된다. 즉,

가 하나의 64-QAM 변조 신호를 구성하며 각각 (

) = (

) 매핑 되며,

가 하나의 64-QAM 변조 신호를 구성하며 각각 (

) = (

) 매핑 된다.

가

번째 변조 신호의 실수부를 구성하며

가

번째 변조 신호의 허수부를 구성함을 알 수 있다. 또한

가

번째 변조 신호의 실수부를 구성하며

가

번째 변조 신호의 허수부를 구성함을 알 수 있다.
In Figure 6, the output bit of the demultiplexer 661

,

Is the 64-QAM modulation scheme of FIG.

). In other words,

Constitute one 64-QAM modulated signal, each (

) = (

), And

Constitute one 64-QAM modulated signal, each (

) = (

).

end

The real part of the first modulated signal

end

It can be seen that the imaginary part of the first modulated signal is configured. Also

end

The real part of the first modulated signal

end

It can be seen that the imaginary part of the first modulated signal is configured.

Next, a design process of the interleaver according to an embodiment of the present invention will be described. The design process of the interleaver according to the present invention follows the following steps.

First step : The number of columns of the interleaver is determined to be equal to the number of bits used in the modulation symbol, that is, two times the number of modulation signal configuration bits.

Second step : The value obtained by dividing the length of the codeword by the number of columns determined in the first step is determined as the number of interleave rows.

Third step : LDPC codeword bits are written to the interleaver having the size determined in the order of the columns.

Step 4: Read one bit in each column in which codeword bits are written.

When inputting one bit at the third step, the position of the starting column may change depending on the row.

In Table 1 below, the lengths of the codewords are 16200 and 4320, for example, and the sizes of the rows and columns of the interleaver according to each modulation scheme are shown.

Modulation method  The number of rows The number of columns n = 16200 n = 4320 QPSK 4050 1080 4 16 QAM 2025 540 8 64 QAM 1350 360 12

Next, the design and operation of the interleaver will be described below with reference to FIGS. 7A and 7B.

7A and 7B are exemplary views illustrating an operation of an interleaver according to an embodiment of the present invention. It is assumed that the interleaver of FIGS. 7A and 7B uses 16-QAM modulation and has a length of 4320 for the LDPC codeword. The four steps of the design and operation of the interleaver described above will be described.

In the first step, eight columns, which are the number of bits used in the 16-QAM, are configured, and in the second step, the number of bits in the row is determined as 4320/8 = 540. In the third step, LDPC codeword bits are sequentially input to each column. In addition, when the input of each column is completed, an input is made to the next column as shown, wherein the number of bits input to each column is 540, which is the number of rows calculated above. Then, according to the fourth step, one bit in each column is sequentially output. In this case, in FIG. 7A, the first bit of column 0 is sequentially output from the first bit of column 7, and the second bit of column 0 is sequentially output from the second bit of column 7. The above process is repeated by the number of rows 540.

Twelve columns are configured for the 64-QAM modulation scheme, and the number of bits of the row in the second stage is determined as 4320/12 = 360. In the case of using the 64-QAM modulation method, since the same method may be used as the method using the 16QAM modulation signal, a detailed description thereof will be omitted.

Through the above process, the LDPC codeword is interleaved. In addition, in order to further increase the performance of interleaving, any interleaving may be performed even inside each column. If there is an association between adjacent codeword bits, interleaving may be performed to be stronger in burst errors. In the simplest case, any interleaving may be a cyclic shift. In this case, rather than performing each cyclic shift, a value to be shifted can be input as a starting point. This is represented in Figure 7b.

So far, the interleaving method has been described. Hereinafter, the bit mapping scheme proposed by the present invention will be described.

The bit mapping scheme described below maps the highest order bits to one of the least reliable bits of the modulation signal configuration bits constituting the modulation signal based on the output of one row of the interleaving outputs of the LDPC codeword, Some of the lowest order bits are mapped to one of the most reliable bits of the modulation signal component bits, with the ratio of mapping the highest bits to the highest bits according to the ratio of the lowest order bits. However, when using multiple DEMUXs, the complexity of the system increases, so that the same DEMUX can be used as much as possible without varying all depending on the ratio of the lowest bits. To do this, change the position of the columns of the parity check matrix. Or use the interleaver only for information word parts. Detailed description will be made with reference to FIGS. 9 to 10.

Hereinafter, the DEMUX of FIG. 6 will be described in detail. The number of output streams of DEMUX depends on the modulation method and is shown in Table 2.

Modulation method

Number of sub-streams,

QPSK 4 16 QAM 8 64 QAM 12 256 QAM 16

를 입력 받아

를 출력 하도록 한다. The DEMUX of FIG. 6D is bit interleaved as follows.

Take input

To output

de-multiplexed된 값의 substream 값으로 이하 표 3 내지 표 10와 같이 정의 할 수 있다.

The substream value of the de-multiplexed value may be defined as shown in Tables 3 to 10 below.

DEMUX(de-muliplxer)의 입력

Input of DEMUX (de-muliplxer)

입력 비트 number (

) (n은 부호어 길이)

Input bit number (

(n is the codeword length)

DEMUX의 출력

Output of DEMUX

DEMUX의 출력 bit number (

)

Output bit number of DEMUX (

)

이다.Hereinafter, the DEMUX of FIG. 6B for the 16-QAM modulation scheme will be described in detail. Codeword length is

to be.

는 Demux에 입력되어

(

) 값이 출력 된다. 이하의 표 3 내지 표 6의 input bit number,

mod

는 입력 비트

의 인덱스값

에 대하여

값을 의미하며, output bit number,

는 출력 비트

의 인덱스

에서

값을 의미한다.The output bits of the bit interleaver

Is entered in Demux

(

) Value is printed. Input bit numbers of Tables 3 to 6 below;

mod

Input bits

Index value of

about

Value, output bit number,

Output bit

Index of

in

It means the value.

Assuming that the interleaver sequentially outputs the bits of the column 0 to the bits of the column 7, as shown in Figure 7a, the embodiment of the Demux of Figure 6b in which the output bits of the interleaver is allocated to the modulation signal configuration bits according to the 16QAM modulation scheme It is illustrated by the following <Table 3> to <Table 6>.

는

와 매핑,

는

와 매핑,

는

와 매핑,

는

와 매핑,

는

와 매핑,

는

와 매핑,

는

와 매핑,

는

와 매핑하다. 상기 매핑 된다는 의미는

(

,

)임을 의미한다. According to Table 3,

Is

And mapping,

Is

And mapping,

Is

And mapping,

Is

And mapping,

Is

And mapping,

Is

And mapping,

Is

And mapping,

Is

Map with Means that the mapping

(

,

).

16 QAM

mod

Input bit number

mod

0 One 2 3 4 5 6 7 Output bit number,

One 7 0 5 4 2 6 3

16 QAM

mod

Input bit number

mod

0 One 2 3 4 5 6 7 Output bit number

7 One 2 5 4 0 6 3

16 QAM

mod

Input bit number

mod

0 One 2 3 4 5 6 7 Output bit number

7 2 One 6 3 0 5 4

16 QAM

mod

Input bit number

mod

0 One 2 3 4 5 6 7 Output bit number

One 4 0 5 7 2 6 3

과

와

와

는 하나의 동일 변조 신호를 구성하며,

와

비트들은 상기 도 4b의 y0와 y1을 각각 구성하며, 변조 신호 구성 비트들 중 신뢰도가 가장 높은 비트에 할당되며,

와

비트들은 상기 도 4b의 y₂와 y₃을 각각 구성하며, 변조 신호 구성 비트들 중에서 신뢰도가 가장 낮은 비트에 할당된다. 또한, 도 6에서 설명된 Demux 출력 값들 중에

과

와

와

는 동일 변조 신호를 구성하며,

과

비트들은 상기 도 4b의 y₀와 y₁을 각각 구성하며, 변조 신호 구성 비트들 중 신뢰도가 가장 높은 비트에 할당되며,

와

는 비트들은 상기 도 4b의 y₂와 y₃을 각각 구성하며, 변조 신호 구성 비트들 중에서 신뢰도가 가장 낮은 비트에 할당된다. Among the output values of Demux described in FIG. 6

and

Wow

Wow

Constitute one identical modulated signal,

Wow

Bits constitute y0 and y1 of FIG. 4B, respectively, and are assigned to the bits having the highest reliability among the modulation signal configuration bits.

Wow

The bits constitute y ₂ and y ₃ of FIG. 4B, respectively, and are assigned to the bits having the lowest reliability among the modulation signal configuration bits. Also, among the Demux output values described in FIG.

and

Wow

Wow

Constitute the same modulated signal,

and

Bits constitute y ₀ and y ₁ of FIG. 4B, respectively, and are assigned to bits having the highest reliability among modulated signal configuration bits.

Wow

Bits constitute y ₂ and y ₃ of FIG. 4B, respectively, and are assigned to bits having the lowest reliability among modulated signal component bits.

Referring to Tables 2 to 5, it can be seen that the interleaver output signals satisfy all of the rules 1), 2), and 3).

Hereinafter, the DEMUX of FIG. 6C for the 64-QAM modulation scheme will be described in detail.

는 Demux에 입력되어

(

) 값이 출력 된다. 이하의 표 7 내지 표 10의 input bit number,

mod

는 입력 비트

의 인덱스값

에 대하여

값을 의미하며, output bit number,

는 출력 비트

의 인덱스

에서

값을 의미한다. The output bits of the bit interleaver

Is entered in Demux

(

) Value is printed. Input bit numbers of Tables 7 to 10 below,

mod

Input bits

Index value of

about

Value, output bit number,

Output bit

Index of

in

It means the value.

An embodiment of Demux of FIG. 6 in which an output bit of an interleaver is allocated to a modulation signal component bit according to a 64-QAM modulation scheme is illustrated in Tables 7 to 10 below.

는

에 매핑,

는

에 매핑,

는

에 매핑,

는

에 매핑,

는

에 매핑,

는

에 매핑,

는

에 매핑,

는

에 매핑,

는

에 매핑,

는

에 매핑,

는

에 매핑,

는

에 매핑된다. 상기 매핑 된다는 의미는

임을 의미한다. (

,

)According to Table 6,

Is

Mapping to,

Is

Mapping to,

Is

Mapping to,

Is

Mapping to,

Is

Mapping to,

Is

Mapping to,

Is

Mapping to,

Is

Mapping to,

Is

Mapping to,

Is

Mapping to,

Is

Mapping to,

Is

Is mapped to. Means that the mapping

Means. (

,

)

64 QAM

mod

Input bit number

mod

0 One 2 3 4 5 6 7 8 9 10 11 Output bit number

11 One 9 7 0 6 3 8 2 5 10 4

64 QAM

mod

Input bit number

mod

0 One 2 3 4 5 6 7 8 9 10 11 Output bit number

9 11 One 6 0 7 2 8 3 5 10 4

64 QAM

mod

Input bit number

mod

0 One 2 3 4 5 6 7 8 9 10 11 Output bit number

11 4 10 5 2 9 3 8 7 0 6 One

64 QAM

mod

Input bit number

mod

0 One 2 3 4 5 6 7 8 9 10 11 Output bit number

11 4 10 0 5 9 One 6 7 2 8 3

Example 1

For better understanding, the input / output of a signal according to the interleaving and bit mapping scheme proposed by the present invention will be described with reference to FIG. 8A.

Assuming that the modulation scheme is 16-QAM and the codeword length is 24, the interleaver has a size of 8 columns and a size of 3 rows. Assume that the bit mapping method applies <16 QAM-Method 1> in Table 3 above.

The codewords output from the LDPC encoder are X = [x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ , x ₇ , x ₈ , x ₉ , x ₁₀ , x ₁₁ , x ₁₂ , x ₁₃ , x ₁₄ , x ₁₅ , x ₁₆ , x ₁₇ , x ₁₈ , x ₁₉ , x ₂₀ , x ₂₁ , x ₂₂ , x ₂₃ ]. When the codeword bits are written in the order of the columns in the interleaver 551, {x ₀ , x ₁ , x ₂ } in column 1 of the interleaver 551, {x ₃ , x ₄ , x ₅ }, and column 3 in column 2 Contains {x ₆ , x ₇ , x ₈ }, column 4 contains {x ₉ , x ₁₀ , x ₁₁ }, column 5 contains {x ₁₂ , x ₁₃ , x ₁₄ }, and column 6 contains {x ₁₅ , x ₁₆ , x ₁₇ }, {x ₁₈ , x ₁₉ , x ₂₀ } in column 7 and {x ₂₁ , x ₂₂ , x ₂₃ } in column 8 respectively. In each of the input columns, bits output in the order of the rows, that is, signals interleaved and output, v = [v ₀ , v ₁ , v ₂ , v ₃ , v ₄ , v ₅ , v ₆ , v ₇ ] = [ x ₀ , x ₃ , x ₆ , x ₉ , x ₁₂ , x ₁₅ , x ₁₈ , x ₂₁ ].

If v is input to the demultiplexer 551, it is mapped according to the above mapping rule, so y = {b _0,0 , b _1,0 , b _2,0 , b _3,0 , b _4,0 , b _{5, 0} , b _6,0 , b _7,0 } = {v ₂ , v ₀ , v ₅ , v ₇ , v ₄ , v ₃ , v ₆ , v ₁ } = {x ₆ , x ₀ , x ₁₅ , x ₂₁ , x ₁₂ , x ₉ , x ₁₈ , x ₃ }. That is, the first modulated signal to the configuration b _0,0 and b _1,0 and b _2,0, and b Looking at the bit that is mapped to _3.0, with the highest confidence code bit-b _0,0 and b The codewords mapped to _1,0 are x ₆ and x ₀ . In addition, codewords mapped to b _2,0 and b _3,0 , which are low reliability bits, are x ₁₅ and x ₂₁ . In addition, that is, two b _4,0 and b _5,0 and b _6,0, and b Looking at the bit that is mapped to the _7,0, the reliability is highest sign determination bit b _4,0 constituting the second modulation signal And codewords mapped to b _5,0 are x ₁₂ , x ₉ . Also, codewords mapped to b _6,0 and b _37,0 , which are low reliability bits, are x ₁₈ and x ₃ .

Example 2)

For better understanding, the input / output of a signal according to the interleaving and bit mapping scheme proposed by the present invention will be described with reference to FIG. 8B below.

Assuming that the modulation scheme is 16-QAM and the codeword length is 24, the interleaver has a size of 8 columns and a size of 3 rows. Assume that the bit mapping method applies <16 QAM-Method 2> of Table 4 above.

The codewords output from the LDPC encoder are X = [x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ , x ₇ , x ₈ , x ₉ , x ₁₀ , x ₁₁ , x ₁₂ , x ₁₃ , x ₁₄ , x ₁₅ , x ₁₆ , x ₁₇ , x ₁₈ , x ₁₉ , x ₂₀ , x ₂₁ , x ₂₂ , x ₂₃ ]. When the codeword bits are written in the order of the columns in the interleaver 551, {x ₀ , x ₁ , x ₂ } in column 1 of the interleaver 551, {x ₃ , x ₄ , x ₅ }, and column 3 in column 2 Contains {x ₆ , x ₇ , x ₈ }, column 4 contains {x ₉ , x ₁₀ , x ₁₁ }, column 5 contains {x ₁₂ , x ₁₃ , x ₁₄ }, and column 6 contains {x ₁₅ , x ₁₆ , x ₁₇ }, {x ₁₈ , x ₁₉ , x ₂₀ } in column 7 and {x ₂₁ , x ₂₂ , x ₂₃ } in column 8 respectively. In each of the input columns, bits output in the order of the rows, that is, signals interleaved and output, v = [v ₀ , v ₁ , v ₂ , v ₃ , v ₄ , v ₅ , v ₆ , v ₇ ] = [ x ₀ , x ₃ , x ₆ , x ₉ , x ₁₂ , x ₁₅ , x ₁₈ , x ₂₁ ].

If v is input to the demultiplexer 551, it is mapped according to the above mapping rule, so y = {b _0,0 , b _1,0 , b _2,0 , b _3,0 , b _4,0 , b _{5, 0} , b _6,0 , b _7,0 } = {v ₅ , v ₁ , v ₂ , v ₇ , v ₄ , v ₃ , v ₆ , v ₀ } = {x ₁₅ , x ₃ , x ₆ , x ₂₁ , x ₁₂ , x ₉ , x ₁₈ , x ₀ }. That is, the first modulated signal to the configuration b _0,0 and b _1,0 and b _2,0, and b Looking at the bit that is mapped to _3.0, with the highest confidence code bit-b _0,0 and b The codewords mapped to _1,0 are x ₁₅ and x ₃ . In addition, codewords mapped to b _2,0 and b _3,0 , which are low reliability bits, are x ₆ and x ₂₁ . In addition, that is, two b _4,0 and b _5,0 and b _6,0, and b Looking at the bit that is mapped to the _7,0, the reliability is highest sign determination bit b _4,0 constituting the second modulation signal And codewords mapped to b _5,0 are x ₁₂ , x ₉ . In addition, codewords mapped to b _6,0 and b _37,0 , which are low reliability bits, are x ₁₈ and x ₀ .

Example 3

,

,

,

,

이며, 20개의 열 그룹의 0 번째 열에 대한 1이 있는 행의 위치 정보는 다음과 같은 수열들로 나타낼 수 있다. 즉, 상기

번째 무게-1 위치 수열은

번째 열 그룹에 대한 1이 있는 행의 위치 정보를 순차적으로 나타낸 것이다. As an example of the LDPC code, an LDPC code having the structure of the parity check matrix of FIG.

,

,

,

,

The position information of a row having 1 for the 0th column of the 20 column group may be represented by the following series. That is

First weight-1 position sequence

Positional information of a row with 1 for the first column group is sequentially displayed.

In this case, when the Demux method of Table 3 is used for the 16-QAM modulation method and Table 7 is used for the 64-QAM modulation method, excellent performance can be obtained.

22 451 529 665 1424 1566 1843 1897 1940 2069 2334 2760 2833

287 303 321 644 874 1110 1132 1175 1266 1377 1610 1819 2517

58 183 247 821 965 1315 1558 1802 1969 2013 2095 2271 2627

181 285 1171 1208 1239 1468 1956 1992 2083 2253 2456 2664 2859

209 1067 1240 2698

970 1201 2099 2388

211 1820 2602 2630

471 1101 1972 2244

254 793 2546 2680

147 761 1495 2794

75 1108 2256 2842

178 796 1309 1763

1820 2157 2470 2686

998 1502 1728 2431

1385 1432 1919 2730

244 972 1673 1902

583 1333 1645 2675

316 664 1086 2854

776 997 2287 2825

537 1719 1746 2728

Example 4

,

,

,

,

이며, 25개의 열 그룹의 0 번째 열에 대한 1이 있는 행의 위치 정보는 다음과 같은 수열들로 나타낼 수 있다. 즉, 상기

번째 무게-1 위치 수열은

번째 열 그룹에 대한 1이 있는 행의 위치 정보를 순차적으로 나타낸 것이다. As an example of the LDPC code, an LDPC code having the structure of the parity check matrix of FIG.

,

,

,

,

The positional information of a row having 1 for the 0th column of the 25 column group may be represented by the following sequences. That is

First weight-1 position sequence

Positional information of a row with 1 for the first column group is sequentially displayed.

In this case, excellent performance can be obtained by using the Demux method of Table 3 for the 16-QAM modulation method and using Table 7 for the 64-QAM modulation method.

103 134 272 282 763 1086 1107 1599 1797 1904 2047 2281 2398

8 232 419 579 676 1333 1486 1710 1777 2079 2193 2377 2415

147 268 335 726 1260 1536 1654 1879 1975 2086 2187 2314 2378

5 450 726 833 860 1200 1425 1507 1512 1588 1921 2029 2504

841 1428 1909 2157

1173 1467 1744 2137

253 618 2173 2309

1163 1518 1836 2425

1276 1563 1646 2320

140 799 847 1306

49 1249 1364 1663

38 509 517 1816

677 761 1544 1842

798 1021 1728 1911

160 772 1325 2465

146 1214 1241 1700

608 672 2082 2506

648 1514 1777 2489

82 415 1755 2196

1096 2140 2149 2475

278 1030 1051 2285

66 1439 2345 2391

251 1683 2252 2494

130 260 428 1328

767 1335 1374 2152

Example 5

,

,

,

,

이며, 12개의 열 그룹의 0 번째 열에 대한 1이 있는 행의 위치 정보는 다음과 같은 수열들로 나타낼 수 있다. 즉, 상기

번째 무게-1 위치 수열은

번째 열 그룹에 대한 1이 있는 행의 위치 정보를 순차적으로 나타낸 것이다. As an example of the LDPC code, an LDPC code having the structure of the parity check matrix of FIG.

,

,

,

,

The positional information of a row having 1 for the 0th column of the 12 column group may be represented by the following sequences. That is

First weight-1 position sequence

Positional information of a row with 1 for the first column group is sequentially displayed.

In this case, excellent performance can be obtained by using the Demux method of Table 4 for the 16-QAM modulation method and using Tables 8 to 10 for the 64-QAM modulation method.

384 944 1269 2266

407 1907 2268 2594

1047 1176 1742 1779

304 890 1817 2645

102 316 353 2250

488 811 1662 2323

31 2397 2468 3321

102 514 828 1010 1024 1663 1737 1870 2154 2390 2523 2759 3380

216 383 679 938 970 975 1668 2212 2300 2381 2413 2754 2997

536 889 993 1395 1603 1691 2078 2344 2545 2741 3157 3334 3377

694 1115 1167 2548

1266 1993 3229 3415

Example 6

,

,

,

,

이며, 15개의 열 그룹의 0 번째 열에 대한 1이 있는 행의 위치 정보는 다음과 같은 수열들로 나타낼 수 있다. 즉, 상기

번째 무게-1 위치 수열은

번째 열 그룹에 대한 1이 있는 행의 위치 정보를 순차적으로 나타낸 것이다.
As an example of the LDPC code, an LDPC code having the structure of the parity check matrix of FIG.

,

,

,

,

The position information of a row having 1 for the 0th column of the 15 column group may be represented by the following series. That is

First weight-1 position sequence

Positional information of a row with 1 for the first column group is sequentially displayed.

In this case, excellent performance can be obtained by using the Demux method of Table 4 for the 16-QAM modulation method and using Tables 9 to 10 for the 64-QAM modulation method.

1343 1563 2745 3039

1020 1147 1792 2609

2273 2320 2774 2976

665 2539 2669 3010

581 1178 1922 2998

633 2559 2869 2907

876 1213 2191 2261

916 1217 1632 2798

500 992 1230 2630

1842 2038 2169 2312

595 679 1206 1486

1087 2681 2894 3123

73 185 355 1381 1672 1998 2406 2577 2600 2834 3084 3115 3150

22 65 390 1022 1046 1465 1498 1682 1879 2108 2164 2203 3106

127 213 714 816 1031 1456 1815 2097 2183 2404 2934 2999 3153

In the case of the LDPC code based on the parity check matrices of the embodiments 5) and 6), the same DEMUX may be used by adjusting the position of the column having the maximum degree despite having a different degree distribution. Detailed description thereof will be made with reference to FIGS. 9 to 10.

Hereinafter, to describe in detail the interleaving and bit mapping scheme proposed by the present invention, it will be described based on the DVB-T2 system and the DVB-NGH system. However, it is not limited to such a system.

9 is a block diagram of a transceiver according to an embodiment of the present invention.

The transmitter 932 of FIG. 9 includes a parity interleaver 902, a demux 904, and a Mapping Cell to Constellation (Encoder 900, a parity interleaver 908, an information word interleaver 910, and a block interleaver 912). 906).

In the encoder 900, the LDPC coded and encoded bits are input to the bit interleaver 902. The bit interleaver 902 includes a parity interleaver 908, an information word interleaver 910, and a block interleaver 912. The parity interleaver 908 is used in the DVB-T2 system using only parity bits among LDPC codewords. The detailed description will be omitted because it may obscure the subject matter of the present invention. The information word interleaver 910 interleaves only information word bits among LDPC code words. As described above, in order not to use different Demux for each code rate in order to obtain optimal performance, only the information word bits are interleaved so that the same demux can be used. Of course, the parity interleaver 908 and the information word interleaver 910 may have the same effect even if the order is changed. Output data of the information word interleaver 910 is input to the block interleaver 912. The block interleaver 912 performs the same operation as described with reference to FIG. 6. Output data of the block interleaver 912 is input to the demux 904. The demux 904 is configured based on the above Tables 3 to 10, and performs the operation of the demux described in detail with reference to FIGS. 6 to 8. Output bits of the demux 904 are input to a mapping cell to constellation 906. Naturally, the demux 904 plays the same role as the signal constellation bit mapper 915 of FIG. 4. In addition, the parity interleaver 908 in the transmitter 932 is not necessarily a block.

The interleaving scheme and the bit mapping scheme in the transmitter 932 have been described. Hereinafter, a deinterleaving and bit demapping scheme used in the receiver 934 will be described. Since the receiver 934 is configured to correspond to the transmitter 932, it will be apparent to those skilled in the art. That is, the Demapping Cell to Constellation 916 of the receiver 934 high-order demodulates the demodulated signal and outputs the modulated signal component bits, and the Mux 918 bit demaps the output modulated signal component bits to demap the demapping signal. Output The demapping method used here corresponds to the bit mapping scheme of the transmitter 904. The bit deinterleaver 920 bit deinterleaves and outputs the output demapping signal. At this time, the size of the deinterleaver 920 is the same as the size of the interleaver 922 of the above-described transmitter. The deinterleaver 920 includes a block deinterleaver 924, an information word deinterleaver 926, and a parity deinterleaver 928. The block deinterleaver 924 sequentially inputs the parity deinterleaved signals in rows, and outputs the deinterleaved signals in the order of columns. The output deinterleaved signals are input to the information word deinterleaver 926. The information word deinterleaver 926 corresponds to the interleaving method of the information word interleaver 910. The output information deinterleaving signals are input to the parity deinterleaver 928. The parity deinterleaver 928 corresponds to the interleaving scheme of the parity interleaver 908. The output deinterleaved signals are input to the decoder 922. The decoder 922 outputs correspondingly decoded signals of the encoder 900.

Instead of using the information word interleaver 910 of FIG. 9, the position of a column of the parity check matrix may be changed. Therefore, instead of the information word interleaver 910 of FIG. 9, the position of the column of the parity check matrix is changed and used corresponding to the information word interleaver 910. Naturally, the changed parity check matrix can be stored and used in a memory.

10 is a block diagram of a transceiver according to another embodiment of the present invention.

The encoder 1000 of FIG. 10 performs LDPC encoding and the encoded bits are input to the bit interleaver 1002. The bit interleaver 1002 is composed of two blocks, and is composed of a parity interleaver 1008 and a block interleaver 1010. The controller 1012 informs the parity interleaver 1008 and the block interleaver 1010 of the number of parity bits and the position of the start point when the block interleaver 1010 is outputted to match the code rate. The parity interleaver is used in the DVB-T2 system by interleaving only parity bits among the codeword bits. The output bits of the bit interleaver 1002 are input to demux 1004. The demux 1004 is configured based on Tables 3 to 10 of the present invention, and performs the operation of the demux described in detail with reference to FIGS. 6 to 8. Output bits of the demux 1004 are input to a mapping cell to constellation 1006. Naturally, the demux 1004 plays the same role as the signal constellation bit mapper 515 of FIG. 5. In addition, the parity interleaver 1008 is not necessarily a required block in the transmitter 1014.

The interleaving method and the bit mapping method in the transmitter 1014 have been described. Hereinafter, the deinterleaving and bit demapping scheme used in the receiver 1016 will be described. Since the receiver 1016 is configured to correspond to the transmitter 1014, it will be apparent to those skilled in the art and will be described briefly. That is, the Demapping Cell to Constellation 1018 of the receiver 1016 high-order demodulates the received signal to output the modulated signal component bits, and the Mux 1020 bit demaps the output modulated signal component bits to demap the demapping signal. Output The demapping method used here corresponds to the bit mapping method of the transmitter 1014. The bit deinterleaver 1022 bit deinterleaving and outputs the output demapping signal. At this time, the size of the deinterleaver 1022 is the same as the size of the interleaver of the above-described transmitter. The deinterleaver 1022 includes a block deinterleaver 1026 and a parity deinterleaver 1028. The block deinterleaver 1026 sequentially inputs the parity deinterleaved signals in rows, and outputs the deinterleaved signals in a column order. The output deinterleaved signals are input to the parity deinterleaver 1028. The parity deinterleaver 1028 corresponds to an interleaving scheme of the parity interleaver 1008. The output deinterleaved signals are input to the decoder 1024. The decoder 1024 outputs correspondingly decoded signals of the encoder 1000.

The interleaving method and the bit mapping method in the transmitter 500 have been described. Hereinafter, a deinterleaving and bit demapping scheme used in the receiver 550 will be described. Since the receiver 550 is configured to correspond to the transmitter 500, it will be apparent to those skilled in the art and thus will be briefly described. That is, the demodulator 557 of the receiver 550 high-order demodulates the received signal to output the modulated signal component bits, and the signal constellation bit demapper 555 bit demaps and outputs the modulated signal component bits. Output the signal. The demapping method used at this time corresponds to the bit mapping method of the transmitter 500. In addition, since the bit demapper 555 corresponds to the bit mapper 515 of the transmitter 500, the bit demapper 555 is configured as a multiplexer (not shown).

The signal debit-mapped and output is input to the deinterleaver 553. At this time, the size of the deinterleaver is the same as the size of the interleaver of the above-described transmitter. The bit demapped signals are sequentially input to the deinterleaver in rows, and are output in the forward direction (outputted from row 1) in the order of the columns to output the deinterleaved LDPC codeword bits. The output deinterleaved LDPC codewords are input to the decoder 551 and are decoded and output.

Claims (1)

In a data transmission method of a communication system using a low density parity check (LDPC) matrix,
An LDPC encoding process for generating an LDPC codeword by encoding the information data bits when the information data bits are input;
Interleaving the LDPC codeword;
A signal constellation bit mapping process of outputting a mapping signal by mapping the interleaved LDPC codewords to signal constellation bit mapping;
A modulation process of outputting a modulated signal by modulating the mapping signal higher order;
And RF processing the RF through the transmitting antenna by RF processing the modulated signal.

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