KR20120025139A - Variable amplitude pulse generator for driving piezo type inkjet printer head - Google Patents

Variable amplitude pulse generator for driving piezo type inkjet printer head Download PDF

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Publication number
KR20120025139A
KR20120025139A KR1020100087335A KR20100087335A KR20120025139A KR 20120025139 A KR20120025139 A KR 20120025139A KR 1020100087335 A KR1020100087335 A KR 1020100087335A KR 20100087335 A KR20100087335 A KR 20100087335A KR 20120025139 A KR20120025139 A KR 20120025139A
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South Korea
Prior art keywords
voltage pulse
signal
driving
voltage
gate
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KR1020100087335A
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Korean (ko)
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KR101199486B1 (en
Inventor
김종선
이경록
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홍익대학교 산학협력단
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04541—Specific driving circuit
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/0457—Power supply level being detected or varied
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04576—Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads of electrostatic type
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04581—Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads based on piezoelectric elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/07—Ink jet characterised by jet control
    • B41J2/075—Ink jet characterised by jet control for many-valued deflection
    • B41J2/08—Ink jet characterised by jet control for many-valued deflection charge-control type
    • B41J2/085—Charge means, e.g. electrodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/135—Nozzles
    • B41J2/14—Structure thereof only for on-demand ink jet heads
    • B41J2/14201—Structure of print heads with piezoelectric elements
    • B41J2/14233—Structure of print heads with piezoelectric elements of film type, deformed by bending and disposed on a diaphragm
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J29/00—Details of, or accessories for, typewriters or selective printing mechanisms not otherwise provided for
    • B41J29/38—Drives, motors, controls or automatic cut-off devices for the entire printing mechanism
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J29/00—Details of, or accessories for, typewriters or selective printing mechanisms not otherwise provided for
    • B41J29/38—Drives, motors, controls or automatic cut-off devices for the entire printing mechanism
    • B41J29/393—Devices for controlling or analysing the entire machine ; Controlling or analysing mechanical parameters involving printing of test patterns

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  • Particle Formation And Scattering Control In Inkjet Printers (AREA)

Abstract

PURPOSE: A variable voltage pulse generator for actuating a head of a piezoelectric inkjet printer is provided to randomly control size and lifting sections of piezoelectric body actuating voltage pulse according to ink dot size. CONSTITUTION: A variable voltage pulse generator for actuating a head of a piezoelectric inkjet printer comprises a controller(210), a counter(220), a control logic block(230), a reference voltage pulse generation block(240), a variable power voltage feeding block(250), a voltage amplifier(260), and an output buffer(270). The controller outputs LOAD signal, LATCH signal, and actuating data. The counter outputs first to fourth counter signals(Q1~Q4) in response to the LOAD signal. The counter is reset in response to the LATCH signal. The control logic block outputs select signal(Sel_out) selecting a number of the voltage pulse according to the actuating data. The reference voltage pulse generation block generates the voltage pulses in response to the LOAD signal. The variable power voltage feeding block gets the select signal and first to fourth sequence signals and selects one of first to fourth variable powers in order to output for power voltage.

Description

Variable voltage pulse generator for driving head of piezoelectric inkjet printer. {Variable Amplitude Pulse Generator for Driving Piezo Type Inkjet Printer Head}

The present invention relates to a voltage pulse generator for driving an ink jet printer head, and more particularly, to a variable voltage pulse generator for driving an ink jet printer head capable of controlling the magnitude and rise and fall time of a driving voltage pulse. It is about.

A print is a device that outputs in the form of a document for checking the results processed by a computer. Printers are typically equipped with basic components such as multifunction machines, fax machines, electronic cash registers, and automated teller machines.

To date, a daisy wheel printer, a dot pin printer, an ink jet printer, a laser printer, and the like have been developed. In particular, an ink jet printer and a laser printer are widely used.

The basic principle of operation of an inkjet printer is to fill an ink chamber with a thin tube nozzle and generate a pressure inside the ink chamber for a short time to eject ink droplets through the nozzle.

Inkjet printers can be largely divided into piezoelectric and thermal methods. The piezoelectric method is a principle in which the vibrating motion of a piezoelectric body attached in an ink chamber with a nozzle acts as an actuator to eject ink by compression and expansion. On the other hand, in the heating method, bubbles generated instantaneously by applying electricity to a thin film heater having a resistance act as an actuator to inject ink.

Piezoelectric inkjet printers are becoming increasingly widespread, from office printers to tools for industrial and manufacturing processes. At this time, the driving voltage pulse of the ink jet printer head is a signal directly applied to the piezoelectric body, which greatly affects the ink dot size and the ejection speed at which the voltage magnitude and the time at which the voltage acts are ejected.

Therefore, the driving voltage pulse design technology of the inkjet printer head is directly related to the quality of the printer pattern, and in order to secure the quality and reliability of the printer pattern, it is necessary to develop an independent design technique.

1 is a block diagram showing the configuration of a voltage pulse generator for driving a head of a conventional piezoelectric inkjet printer.

Referring to FIG. 1, a voltage pulse generator 100 for driving a head of a conventional piezoelectric inkjet printer includes a controller 110, a digital-analog converter 120, a voltage amplifier 130, and an output buffer 140. It includes.

The controller 110 transfers the driving data previously stored in the memory to the digital-analog converter (DAC) 120, and the digital-analog converter 120 converts the received driving data into an analog signal. .

The voltage amplifier 130 amplifies the converted analog signal to a high voltage, and the output buffer 140 lowers the impedance by increasing the current gain.

2 is a diagram showing a head injection control method of a conventional piezoelectric inkjet printer. Here, the head injection control method of the industrial piezoelectric inkjet printer provided with N nozzles per head is shown. One-bit drive data is input to determine the on / off of the piezoelectric drive switch for each nozzle.

Referring to FIG. 2, the drive switch connected to the piezoelectric body of each nozzle controls head injection through turn on or turn off and receives 1 bit of drive data as an input. In this case, if a fixed voltage pulse occurs once, the corresponding piezoelectric body is driven once and ink is ejected.

However, for large-sized ink ejection, the same voltage pulse must be repeated several times to increase the number of driving of the piezoelectric body.

The conventional voltage pulse generator 100 for driving the head of the piezoelectric inkjet printer has a problem in that the number of driving is repeated when controlling the ink dot size because it generates a voltage pulse having a fixed size.

In addition, in the voltage pulse generator 100 for driving the head of a conventional piezoelectric inkjet printer, the digital-analog converter 120, the voltage amplifier 130, and the output buffer 140 are each composed of individual IC elements. It is difficult to integrate into one chip, and has a disadvantage in size and cost. In particular, the output buffer 140 is to amplify the current, usually composed of a high-power BJT device has a large power consumption problem.

The technical problem to be solved by the present invention is to provide a novel programmable head injection control method for driving a piezoelectric inkjet printer head, and for this purpose, the magnitude of the driving voltage pulse and the rise of the driving voltage pulse in the voltage pulse generator are The present invention provides a variable voltage pulse generator for driving a piezoelectric inkjet printer head capable of controlling the fall time.

The variable voltage pulse generator for driving the head of a piezoelectric inkjet printer according to the present invention for achieving the technical problem, the controller 210 for outputting a LOAD signal, a LATCH signal and driving data, in response to the LOAD signal A counter 220 which outputs a fourth to fourth counter signals Q1 to Q4 and is reset in response to the LATCH signal, and the LOAD signal in response to the driving data and the first to fourth counter signals Q1 to Q4. A control logic block for outputting the first to fourth order signals Sel1 to Sel4 indicating the order of generation of the voltage pulses generated by and the selection signal Sel_out for selecting the number of voltage pulses according to the driving data; 230, the voltage pulses are generated in response to the LOAD signal, and a predetermined number of the voltage pulses is selected and output as a reference voltage pulse in response to the selection signal Sel_out. Receives a reference voltage pulse generating block 240, the selection signal Sel_out and the first to fourth order signals Sel1 to Sel4, and receives one of the first to fourth variable power sources V1 to V4. A variable power supply voltage supply block 250 for selecting and outputting the power supply voltage VDDin and the voltage amplifier 260 for receiving the reference voltage pulse and the power supply voltage VDDin and amplifying the reference voltage pulse to output a high voltage pulse. And an output buffer 270 that increases the current gain in response to the high voltage pulse and the RC time constant control signal and outputs a driving voltage pulse whose rise and fall times are adjusted.

The variable voltage pulse generator for driving the head of the piezoelectric inkjet printer according to the present invention can arbitrarily adjust the size and rising and falling sections of the piezoelectric driving voltage pulse according to the ink dot size, and 0.18um BCD for low power and low cost. The process-based design has the advantage of enabling one-chip implementation.

1 is a block diagram showing the configuration of a voltage pulse generator for driving a head of a conventional piezoelectric inkjet printer.
2 is a diagram showing a head injection control method of a conventional piezoelectric inkjet printer.
3 is a diagram showing a programmable head injection control method of a piezoelectric inkjet printer according to the present invention.
4 is a block diagram showing a configuration of a variable voltage pulse generator for a new head driving method of a piezoelectric inkjet printer according to the present invention.
5 is a diagram illustrating a detailed configuration of a control logic block of a variable voltage pulse generator for driving a head of an inkjet printer according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating a detailed configuration of a reference voltage pulse generation block of a variable voltage pulse generator for driving a head of an inkjet printer according to an embodiment of the present invention.
7 is a diagram illustrating a detailed configuration of an output buffer of a variable voltage pulse generator for driving a head of an inkjet printer according to an embodiment of the present invention.
FIG. 8 is a diagram illustrating a simulation result of controlling the rise and fall times of the basic pulses in the output buffer of FIG. 7.
9 is a view showing the results of the entire simulation of the variable voltage pulse generator for driving the head of the inkjet printer according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

3 is a diagram showing a programmable head injection control method of a piezoelectric inkjet printer according to the present invention.

Referring to FIG. 3, unlike the conventional head injection control method using 1 bit drive data, the head injection control method according to the present invention uses 2 bit drive data (00, 01, 10, 11) to drive the piezoelectric body. do.

Therefore, four different ink dot sizes (no ejection, small size, medium size, and large size) can be controlled by the two-bit drive data. Among the four types, a small voltage pulse is generated when there is no ejection to shake the ink chamber to assist the next ejection. As such, unlike the conventional head ejection control method, the head ejection control method according to the present invention can adjust the fine ink dot size, thereby improving the print quality.

Figure 4 is a block diagram showing the configuration of a variable voltage pulse generator for a new head drive method of the piezoelectric inkjet printer according to the present invention.

Referring to FIG. 4, the variable voltage pulse generator 200 for driving the head of a piezoelectric inkjet printer according to the present invention includes a controller 210, a counter 220, a control logic block 230, and a reference voltage pulse. A block 240, a voltage amplifier 250, and a variable power supply voltage supply block 260. Here, the output buffer 270 may be further included.

The controller 210 outputs driving data, a LOAD signal, and a LATCH signal previously stored in the memory. The drive data is 2-bit data, and one to four drive voltage pulses are generated according to the value (00, 01, 10, 11). At the same time, one of four different ink dot sizes (no ejection, small size, medium size, and large size) corresponding to the drive data is ejected. The LOAD signal indicates the time when each basic voltage pulse is generated, and the LATCH signal is generated at the end of the drive data input by resetting the following counter, and becomes a signal for distinguishing one time frame.

The counter 220 outputs the first to fourth counter signals Q1 to Q4 in response to the LOAD signal, and resets them in response to the LATCH signal. That is, the counter 220 receives the first counter signal Q1 by the first LOAD signal, the second counter signal Q2 by the second LOAD signal, and the third counter signal Q3 by the third LOAD signal. The fourth counter signal Q4 is output by the fourth LOAD signal. After that, the counter 220 is reset in response to the LATCH signal and outputs new first to fourth counter signals Q1 to Q4 in response to the new LOAD signal.

Therefore, the first to fourth counter signals output from the counter 220 are logic level high generated in accordance with the LOAD signal, and may also be regarded as containing information about the number of occurrences and the timing of generation of the voltage pulses generated by the LOAD signal. . In addition, the counter according to an embodiment of the present invention is designed in the form of a typical ring counter (Ring Counter), it is composed of D-flip flop.

The control logic block 230 receives two bits of driving data (00, 01, 10, 11) and the first to fourth counter signals Q1 to Q4, and forms a reference voltage pulse through a gate logic operation. The first to fourth order signals Sel1 to Sel4 indicating the generation order of voltage pulses generated by the selection signal Sel_out and the LOAD signal are selected.

For example, the selection signal Sel_out selects one voltage pulse when driving data is '00', and selects two voltage pulses when driving data is '01'. When the driving data is '10', three voltage pulses are selected. When the driving data is '11', four voltage pulses are selected.

Accordingly, the reference voltage pulse may include a first reference voltage pulse having one voltage pulse, a second reference voltage pulse having two voltage pulses, a third reference voltage pulse having three voltage pulses, and the voltage pulse having four voltage pulses. One of the fourth reference voltage pulses.

The reference voltage pulse generation block 240 generates square voltage pulses in response to the LOAD signal, and selects a predetermined number of the voltage pulses in response to the selection signal Sel_out and outputs the reference voltage pulses. For example, there may be four types of reference voltage pulses from one output voltage output to four output voltage outputs.

As such, there are four types of reference voltage pulses and corresponding driving voltage pulses according to the 2-bit driving data (00, 01, 10, and 11). Therefore, four different ink dot sizes (no ejection, small size, medium size, and large size) can be controlled by the 2-bit driving data.

 The variable power supply voltage generation block 250 receives the selection signal Sel_out and the first to fourth order signals Sel1 to Sel4, and selects one of the first to fourth variable voltages V1 to V4 or the order thereof. As described above, the voltage amplifier 260 outputs the power voltage VDDin of the voltage amplifier 260.

That is, the power source voltage VDDin is formed by using the selection signal Sel_out including the number information of the voltage pulses forming the reference voltage pulse and the first to fourth order signals Sel1 to Sel4 including the generation order information of the voltage pulses. Is changed to V1, V2, V3, and V4. In addition, the power supply voltage VDDin removes noise of the power supply voltage and passes through a regulator for stabilization before the power amplifier 260 is applied.

The power supply voltage generation circuit of the variable power supply voltage generation block 250 according to an embodiment of the present invention uses the voltage divider of a general resistor panel to make a variable voltage V1 to V4 of 0V to 80V. The regulator circuit is a CMOS on-chip regulator circuit that stabilizes the power supply voltage and applies the voltage to the voltage amplifier 260.

Power supply voltage generation circuit and regulator circuit according to an embodiment of the present invention is a general circuit, the detailed description of the detailed configuration is omitted herein.

The voltage amplifier 260 receives the power supply voltage VDDin that is variable with the reference voltage pulse and amplifies each voltage pulse forming the reference voltage pulse and outputs it as a high voltage pulse. At this time, since the power supply voltage VDDin is variable, it can be output as a high voltage pulse consisting of voltage pulses of various sizes.

The voltage amplifier 260 according to an embodiment of the present invention has a general two-stage CMOS differential amplifier structure. For example, if a reference voltage pulse consisting of four voltage pulses is input to the voltage amplifier, the first voltage pulse is the power supply voltage at 20 V, the second voltage pulse is the power supply voltage at 80 V, and the third voltage pulse is the power supply. The voltage is changed to 60V and the fourth voltage pulse is amplified by changing the power supply voltage to 40V.

The output buffer 270 receives the high voltage pulse and outputs a driving voltage pulse whose rise and fall time is adjusted in response to a 2-bit RC time constant control signal. The output buffer 270 has a basic structure of an emitter follower capable of lowering impedance by increasing current gain, and is designed to be programmable to adjust RC time constant through the 2-bit RC time constant control signal. In this case, the RC time constant may be controlled in various ways by increasing the number of bits of the RC time constant control signal.

5 is a diagram illustrating a detailed configuration of a control logic block of a variable voltage pulse generator for driving a head of an inkjet printer according to an embodiment of the present invention.

The control logic block 230 combines two bits of drive data (00, 01, 10, 11) and the first to fourth counter signals Q1 to Q4 to determine the ink dot size, as described above. The selection signal Sel_out for selecting the number of voltage pulses constituting the pulse and the first to fourth order signals Sel1 to Sel4 indicating the generation order of the voltage pulses generated by the LOAD signal are output.

Referring to FIG. 5, the control logic block 230 includes first to third OR gates OR1 to OR3 and first to sixth AND gates AND1 to AND6. Here, D0 represents an upper bit among two bits of drive data and D1 represents a lower bit among two bits of drive data.

The first OR gate OR1 outputs a first driving signal by logically combining logic level high VDD and the upper bit D0 of the driving data, and the second OR gate OR2 is connected to the upper bit D0. The lower bit D1 of the driving data is ORed to output a second driving signal.

The first AND gate outputs a third driving signal by ANDing the upper bit D0 and the upper bit D0, and the second AND gate performs an AND on the upper bit D0 and the lower bit D1. The fourth driving signal is output.

The third AND gate outputs the first sequence signal Sel1 by ANDing the first counter signal Q1 and the first driving signal, and the fourth AND gate includes the second counter signal Q2 and the first counter signal. The second driving signal is logically multiplied to output the second order signal Sel2.

The fifth AND gate outputs the third sequence signal Sel3 by multiplying the third counter signal Q3 and the third driving signal, and the sixth AND gate includes the fourth counter signal Q4 and the fourth counter gate. The fourth driving signal is ANDed to output the fourth order signal Sel4.

Finally, the third OR gate outputs the selection signal Sel_out by ORing the first to fourth order signals.

FIG. 6 is a diagram illustrating a detailed configuration of a reference voltage pulse generation block of a variable voltage pulse generator for driving a head of an inkjet printer according to an embodiment of the present invention.

Referring to FIG. 6, the reference voltage pulse generation block 240 includes a reference voltage pulse including a reference voltage pulse generation circuit 241 for generating voltage pulses according to a LOAD signal and a number of voltage pulses selected by the selection signal Sel_out. And a reference voltage pulse selection circuit 242 for outputting the signal.

The reference voltage pulse generation circuit 241 is synchronized with the LOAD signal to latch a logic level high (VDD) to output the voltage pulses and a pulse width for controlling the width of the voltage pulses. The control unit 242-2 is included.

The pulse width controller 242-2 is a first inverter INV1 positioned between the output of the D-flip flop 241-1 and node 1 nod1, and each drain thereof is connected to node 1 nod1. The first to third NMOS transistors MN1 to MN3 and the respective gates to which the first to third pulse width control signals Bc1 to Bc3 are applied to the respective gates are respectively applied to the first to third NMOS transistors. The first to third capacitors MC1 to MC3 are connected to the sources of MN1 to MN3 and the drains and the sources are connected to each other to be connected to the ground voltage.

 As such, the reference voltage pulse generation circuit 241 generates square voltage pulses in accordance with the LOAD signal in the D-flip flop 242-1, and the first to third pulses in the pulse width controller 242-2. The width of the voltage pulses is adjusted by turning on or off the first to third capacitors MC1 to MC3 through the width control signals Bc1 to Bc3.

The reference voltage pulse selection circuit 242 is turned on or off in response to the second inverter INV2 for inverting the selection signal Sel_out and the selection signal inverted with the selection signal Sel_out and passes through the voltage pulses. Alternatively, a blocking gate and a drain may be connected to the output of the transmission gate, and the source may be connected to a ground voltage, and the fourth NMOS transistor MN4 may be applied to the gate.

As such, the reference voltage pulse selection circuit 242 has the transfer gate turned on or off in response to the selection signal Sel_out. At this time, when the transfer gate is turned on, the voltage pulse generated by the reference voltage pulse generator 241 passes and is output. However, if there is no selection signal Sel_out, the transfer gate is turned off and the output is connected to GND.

For example, when the voltage pulses are generated in accordance with the LOAD signal by the reference voltage pulse generator 241, the voltage pulse may be one of four to four according to the selection signal Sel_out in the reference voltage pulse selector 242. Output the reference voltage pulse.

7 is a diagram illustrating a detailed configuration of an output buffer of a variable voltage pulse generator for driving a head of an inkjet printer according to an embodiment of the present invention.

Referring to FIG. 7, the output buffer 270 includes the npn bipolar junction transistor TR1, the pnp bipolar junction transistor TR2, the first to sixth resistors R1 to R6, and the fifth to eighth enMOS transistors MN5. ~ MN8).

The npn bipolar junction transistor TR1 and the pnp bipolar junction transistor TR2 form a general emitter follower structure, and the first and second resistors R1 and R2 are already formed of the npn bipolar junction transistor TR1. And the emitter of the pnp bipolar junction transistor TR2 are connected in series. The addition of the first and second resistors R1 and R2 is for filtering high frequency components such as glitches occurring in the output waveform.

The third and fourth resistors R3 and R4 are connected in series between the power supply voltage VDDh and the collector of the npn bipolar junction transistor TR1, and the fifth and sixth resistors R5 and R6 are connected to the ground voltage VSS. ) And the collector of the pnp bipolar junction transistor TR2 are connected in series.

The drain of the fifth NMOS transistor MN5 is between the power supply voltage VDDh and the third resistor R3, and the source of the fifth NMOS transistor MN5 is the third resistor R3 and the fourth resistor R4. ) And the upper bit B1 of the 2-bit RC time constant control signal is applied to the gate of the fifth NMOS transistor MN5.

The drain of the sixth NMOS transistor MN6 is between the third resistor R3 and the fourth resistor R4, and the source of the sixth NMOS transistor MN6 is the fourth resistor R4 and the npn bipolar junction transistor. The lower bit B0 of the RC time constant control signal of 2 bits is applied to the gate of the sixth NMOS transistor MN6, respectively, connected between the collectors of TR1.

The drain of the seventh NMOS transistor MN7 is between the collector of the pnp bipolar junction transistor TR and the fifth resistor R5, and the source of the seventh NMOS transistor MN7 is formed of the fifth resistor R5 and the fifth resistor R5. The sixth resistor R6 is connected to each other, and the lower bit B0 of the 2-bit RC time constant control signal is applied to the gate of the seventh NMOS transistor MN7.

The drain of the eighth NMOS transistor MN8 is between the fifth resistor R5 and the sixth resistor R6, and the source of the eighth NMOS transistor MN8 is the sixth resistor R6 and the ground voltage Vss. ) Are connected to each other, and the upper bit B1 of the 2-bit RC time constant control signal is applied to the gate of the eighth NMOS transistor MN8.

In the output buffer according to an embodiment of the present invention, the fifth to eighth NMOS transistors are turned on or turned off by the upper bit B1 and the lower bit B0 of the 2-bit RC time constant control signal, respectively. The time constant changes.

For example, if the upper and lower bits of the 2-bit RC time constant control signal are logic level low, the fifth to eighth NMOS transistors are turned off in mode, and most of the current is passed through the third to sixth resistors. Will flow. Therefore, the RC time constant is the largest, and the rise and fall time of each voltage pulse constituting the driving voltage pulse is the longest.

FIG. 8 is a diagram illustrating a simulation result of controlling the rise and fall times of the basic pulses in the output buffer of FIG. 7.

Referring to FIG. 8, when the logic levels of the 2-bit RC time constant control signals are '00', '01', '10', and '11', the RC time constant decreases in the above order, and the driving voltage pulse is decreased. It can be seen that the rise and fall times of the respective voltage pulses are shortened. In this case, the rise and fall times can be more precisely controlled by increasing the number of bits of the RC time constant control signal.

9 is a view showing the results of the entire simulation of the variable voltage pulse generator for driving the head of the inkjet printer according to an embodiment of the present invention.

Referring to FIG. 9, in the variable voltage pulse generator for driving a head of an inkjet printer according to an exemplary embodiment of the present invention, when two-bit driving data is '00', a driving voltage pulse having only one pulse is generated. In case of '01', a driving voltage pulse with two pulses is generated. In case of '10', a driving voltage pulse with three pulses is generated. In case of '11', a driving voltage pulse with four pulses is generated. Is generated.

In addition, as the power supply voltage of the voltage amplifier 260 is varied, it can be seen that the magnitude of each voltage pulse constituting the driving voltage pulse is differently output.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

Claims (13)

In the voltage pulse generator for driving the head of the piezoelectric inkjet printer,
A controller 210 for outputting a LOAD signal, a LATCH signal and driving data;
A counter 220 for outputting first to fourth counter signals Q1 to Q4 in response to the LOAD signal and resetting in response to the LATCH signal;
First to fourth order signals Sel1 to Sel4 indicating a generation order of voltage pulses generated by the LOAD signal in response to the driving data and the first to fourth counter signals Q1 to Q4, and the driving A control logic block 230 for outputting a selection signal Sel_out for selecting the number of voltage pulses according to the data;
A reference voltage pulse generation block 240 generating the voltage pulses in response to the LOAD signal, selecting a predetermined number of the voltage pulses in response to the selection signal Sel_out, and outputting the predetermined number as a reference voltage pulse;
A variable that receives the selection signal Sel_out and the first to fourth order signals Sel1 to Sel4, selects one of the first to fourth variable power sources V1 to V4, and outputs the selected voltage to the power supply voltage VDDin. A power voltage supply block 250;
A voltage amplifier 260 which receives the reference voltage pulse and the power supply voltage VDDin, amplifies the reference voltage pulse and outputs the high voltage pulse; And
In response to the high voltage pulse and the RC time constant control signal, the head drive of the piezoelectric inkjet printer, comprising: an output buffer 270 that increases current gain and outputs a driving voltage pulse whose rise and fall times are adjusted. Variable voltage pulse generator for The method of claim 1, wherein the RC time constant control signal,
A variable voltage pulse generator for driving the head of a piezoelectric inkjet printer, characterized in that it is 2-bit data. The method of claim 1, wherein the drive data,
A variable voltage pulse generator for driving the head of a piezoelectric inkjet printer, characterized in that it is 2-bit data. The method of claim 1, wherein the first to fourth counter signals Q1 to Q4,
A variable voltage pulse generator for driving the head of a piezoelectric inkjet printer, characterized in that each signal is a high level in accordance with the generation order of the voltage pulses. The method of claim 1, wherein the selection signal Sel_out is
When the driving data is '00', one voltage pulse is selected.
When the driving data is '01', two voltage pulses are selected.
When the driving data is '10', three voltage pulses are selected,
If the drive data is '11', the variable voltage pulse generator for driving the head of the piezoelectric inkjet printer, characterized in that the signal to select the four voltage pulses. The method of claim 5, wherein the reference voltage pulse,
A first reference voltage pulse consisting of one voltage pulse,
A second reference voltage pulse consisting of two voltage pulses,
A third reference voltage pulse consisting of three voltage pulses;
The variable voltage pulse generator for driving the head of the piezoelectric inkjet printer, characterized in that any one of the fourth reference voltage pulse consisting of four voltage pulses. The method of claim 1, wherein the control logic block,
A first OR gate OR1 for ORing logic level high VDD and the lower bit D0 of the driving data to output a first driving signal;
A second OR gate OR2 for ORing the lower bit D0 and the upper bit D1 of the driving data to output a second driving signal;
A first AND gate (AND1) outputting a third driving signal by ANDing the lower bit (D0) and the lower bit (D0);
A second AND gate (AND2) for outputting a fourth driving signal by ANDing the lower bit (D0) and the higher bit (D1);
A third AND gate (AND3) outputting the first order signal (Sel1) by ANDing the first counter signal (Q1) and the first driving signal;
A fourth AND gate (AND4) outputting the second order signal (Sel2) by ANDing the second counter signal (Q2) and the second driving signal;
A fifth AND gate (AND5) outputting the third order signal (Sel3) by ANDing the third counter signal (Q3) and the third driving signal;
A sixth AND gate (AND6) outputting the fourth order signal (Sel4) by multiplying the fourth counter signal (Q4) by the fourth driving signal; And
And a third OR gate (OR3) for ORing the first to fourth order signals to output the selection signal (Sel_out). The method of claim 1, wherein the reference voltage pulse generation block 240,
A reference voltage pulse generation circuit 241 for generating the voltage pulses in response to the LOAD signal and adjusting the width of the voltage pulses in response to first to third pulse width control signals Bc1 to Bc3; And
And a reference voltage pulse selecting circuit 242 for selecting a predetermined number of the voltage pulses in response to the selection signal Sel_out and outputting the predetermined voltage as a reference voltage pulse. Voltage pulse generator. The method of claim 8, wherein the reference voltage pulse generation circuit 241,
A D-flip-flop 241-1 which latches a logic level high VDD in synchronization with the LOAD signal to output the voltage pulses; And
Including a pulse width control unit 241-2 for controlling the width of the voltage pulses,
The pulse width control unit 241-2
A first inverter for inverting the output of the D-flip-flop,
Each drain is connected to an output terminal of the first inverter, and the first to third enMOS transistors MN1 to MN3 to which the first to third pulse width control signals Bc1 to Bc3 are applied to respective gates, and
Each gate is connected to the sources of the first to third NMOS transistors MN1 to MN3, and each of the drain and source is connected to each other to be connected to ground voltages. Variable voltage pulse generator for driving the head of the piezoelectric inkjet printer, characterized in that it comprises a). The method of claim 8, wherein the reference voltage pulse selection circuit 242,
A second inverter for inverting the selection signal Sel_out;
A transmission gate which is turned on or off in response to the selection signal inverted from the selection signal Sel_out and passes or blocks the voltage pulses; And
A drain is connected to the transfer gate output, and a source is connected to a ground voltage, and the head drive of the piezoelectric inkjet printer includes a fourth NMOS transistor MN4 to which the inverted selection signal is applied to the gate. Variable voltage pulse generator for The method of claim 1, wherein the output buffer 270,
An npn bipolar junction transistor TR1 and a pnp bipolar junction transistor TR2 to which the high voltage pulse is applied to each base;
First and second resistors R1 and R2 connected in series between the emitter of the npn bipolar junction transistor and the emitter of the pnp bipolar junction transistor;
Third and fourth resistors R3 and R4 connected in series between a power supply voltage VDDh and a collector of the npn bipolar junction transistor;
Fifth and sixth resistors R5 and R6 connected in series between a ground voltage VSS and a collector of the pnp bipolar junction transistor;
A drain is connected between the power supply voltage VDDh and the third resistor R3, and a source is connected between the third resistor and the fourth resistor R4, and a gate is one of the two bit RC time constant control signals. A fifth enMOS register to which a lower bit B0 is applied;
A drain is connected between the third resistor R3 and the fourth resistor R4, and a source is connected between the fourth resistor and the collector of the npn bipolar junction transistor, and the gate is the 2-bit RC time constant control signal. A sixth NMOS transistor to which an upper bit B1 is applied;
A drain is connected between the collector of the pnp bipolar junction transistor and the fifth resistor R5, a source is connected between the fifth resistor and the sixth resistor, and a gate is an upper bit of the two-bit RC time constant control signal. A seventh NMOS transistor to which (B1) is applied;
A drain is connected between the fifth resistor and the sixth resistor R6, a source is connected between the sixth resistor and the ground voltage Vss, and a gate is a lower bit of the RC bit constant control signal of the two bits. And an eighth NMOS transistor to which B0) is applied. The method of claim 1, wherein the counter 220,
A variable voltage pulse generator for driving a head of a piezoelectric inkjet printer, characterized in that it is designed in the form of a ring counter composed of D-flip flops. The method of claim 1, wherein the power amplifier 260 is
Has a two-stage CMOS differential amplifier structure,
The variable voltage pulse generator for driving the head of the piezoelectric inkjet printer, characterized in that the power supply voltage is variable.

KR20100087335A 2010-09-07 2010-09-07 Variable Amplitude Pulse Generator for Driving Piezo Type Inkjet Printer Head KR101199486B1 (en)

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