KR20120023997A - Method and appatatus for digital-controlled oscillating using wide band active inductor with 3-step coarse tuning - Google Patents

Abstract

PURPOSE: A method and an apparatus for digital-controlled oscillation using wide band active inductors with a 3-step coarse tuning manner are provided to have wide band tuning domain using a 3-step coarse tuning manner. CONSTITUTION: A digital-controlled oscillator core(310) comprises a cap bank, an active inductor, a manual inductor, and a negative GM circuit. A coarse tuning digital controller(320) controls 3-step coarse tuning operation of a digital-controlled oscillator(300). The DCO_OUT and the DCO_OUTB outputted in the digital-controlled oscillator core are dispensed through a 4(or 8)-divider(340). The outputted SDM_CLK is inputted to a sigma-DELTA modulator(330).

Description

METHOD AND APPATATUS FOR DIGITAL-CONTROLLED OSCILLATING USING WIDE BAND ACTIVE INDUCTOR WITH 3-STEP COARSE TUNING}

The following embodiments are directed to a digitally controlled oscillator that is one of the building blocks of a digital phase locked loop.

In order to supply a local oscillator (LO) frequency of a wireless communication transceiver, a phase locked loop configured in various ways is widely used.

The analog phase locked loop uses a very sensitive current source in a high frequency divider, which is an internal block thereof. When the smallest metal-oxide-semiconductor (MOS) device is used in an analog phase locked loop, noise and accuracy issues arise as the process scale decreases.

Digitally configured phase locked loops are insensitive to process variations. Therefore, a digital phase locked loop is used to overcome noise and accuracy issues. Digitally configured phase locked loops require a digitally controlled oscillator as its building block.

In order for the frequency to be adjusted, an adjustment bit must be input into the oscillator. To do this, a digital-to-analog converter is used to convert the adjustment bit into an analog voltage, and then a switch is attached to the capacitor in accordance with the first method and the adjustment bit to adjust the frequency using a varactor. The second method of adjusting the frequency by turning the switch ON / OFF is generally used.

1 shows a typical digital phase locked loop.

The digital phase-locked loop 100 generally includes a Phase Frequency Detector (PFD) 110, a Time to Digital Convertor (TDC) 120, a Digital Loop Filter 130, and an N-Divider. 140 and a Digital Controlled Oscillator (DCO) 150.

The frequencies DCO_OUT and DCO_OUTB output from the digitally controlled oscillator 150 are divided through the N-divider 140 and output as the divided digitally controlled oscillator signal DCO_DIV.

The PFD 110 compares the reference frequency REF_CLK and DCO_DIV and outputs a phase error as a pulse waveform.

The TDC 120 converts the output pulse waveform into a digital signal and outputs the digital signal.

The output digital signal is configured as a negative feed back by the digital loop filter 130 for stability and is input to the digital controlled oscillator 150.

Figure 2 shows a circuit diagram of a voltage controlled oscillator commonly used in a phase locked loop.

The voltage controlled oscillator circuit uses passive element inductors, metal-insulator-metal (MIM) capacitors and varactors. In general, the frequency of the voltage controlled oscillator is adjusted by changing the C value among the L value (inductance) and C value (capacitance).

In the oscillator construction circuit of such a phase locked loop, passive elements L and C occupy most of the construction circuit. Therefore, in the present process, such a component circuit requires a large area.

In addition, in the part where a phase locked loop is required, the provision of the frequency over a wide bandwidth is gradually required.

Since L in the LC resonant tank is a fixed value with passive elements, high capacitance is required to obtain the wide bandwidth of the tuning region. High capacitance also causes the component circuit to take up a large area.

If the frequency is tuned simply by the capacitance value, the slope of the frequency curve is severely changed according to the capacitance value.

This gain mismatch degrades the phase noise performance, which is an important measure of phase locked loops. Additional circuitry and algorithms are required to compensate for this.

According to one aspect of the present invention, a negative resistance, which is a cross-couple of PMOS and NMOS, an active inductor for tuning the frequency, a passive inductor for canceling the reduction of phase noise performance using the active inductor, and a capacitance bank for canceling the PVT change A digitally controlled oscillator is provided.

The digitally controlled oscillator may tune the frequency by adjusting the input current of the active inductor and adjusting the capacitance of the capacitance bank.

The digitally controlled oscillator may further comprise a sigma-delta modulator that enhances the resolution of the frequency.

The digitally controlled oscillator may further include a digital loop filter, and the active inductor may tune the frequency by adjusting the current according to the bit entering the digital loop filter.

The active inductor may include an active inductor control bank for controlling the active inductor.

The active inductor may comprise a first circuit portion configured to provide inductance and a second circuit portion adjusting the amount of current in the MOS to adjust the inductance.

The active inductor may adjust the inductance of the active inductor by adjusting the current amount of the MOS.

The cap bank may comprise an array of metal-insulator-metal capacitors.

The cap bank may further include a MOS switch for adjusting the capacitance value by switching.

The capacitors can be configured using binary weights.

The active inductor can obtain the resolution by adjusting the voltage level of the MOS gate.

The digitally controlled oscillator may further include a coarse tuning digital controller for controlling the frequency tuning step.

The coarse tuning digital controller includes a k-divider for dividing the frequency of the digitally controlled oscillator, an M-bit counter for counting divided clocks, a reference divider for controlling the M-bit counter, and a value counted in the M-bit counter. It may include a digital comparator for comparing the, a coarse tuning map table for converting the required frequency into M-bit, and a three-stage tuning controller for controlling the digitally controlled oscillator.

According to another aspect of the invention, the broadband-tuning step of adjusting the center frequency oscillating by adjusting the main current of the active inductor, the mid-band tuning step of adjusting the oscillation frequency by adjusting the capacitance of the capacitance bank and the active inductor A method of automatic tuning of a digitally controlled oscillator circuit is provided that includes a narrowband-tuning step of adjusting the oscillation frequency by adjusting the negative current.

A three stage coarse tuning method and apparatus is provided that enables frequency tuning in a wide band.

Using a three-step coarse tuning method, an active inductor digitally controlled oscillation method and apparatus having a wideband tuning region is provided.

To minimize the area, a digitally controlled oscillator consisting of active elements is provided.

1 shows a typical digital phase locked loop.
Figure 2 shows a circuit diagram of a voltage controlled oscillator commonly used in a phase locked loop.
3 is a structural diagram of a digitally controlled oscillator according to an embodiment of the present invention.
4 is a circuit diagram of a digitally controlled oscillator core in accordance with an embodiment of the present invention.
5 is a circuit diagram of an active inductor control bank according to an embodiment of the present invention.
6 is a circuit diagram of a cap bank according to an embodiment of the present invention.
7 illustrates an internal schematic of an active inductor according to an embodiment of the present invention.
8 is a flowchart illustrating a three-step coarse tuning method according to an embodiment of the present invention.
9 illustrates the operation of the digital control generator during the first stage coarse tuning according to an embodiment of the present invention.
10 illustrates an operation of an active inductor control bank during first stage coarse tuning according to an embodiment of the present invention.
11 illustrates an operation of a digital control generator during second stage coarse tuning according to an embodiment of the present invention.
12 illustrates the operation of the digital control generator during the third stage coarse tuning according to an embodiment of the present invention.
FIG. 13 illustrates an operation of an active inductor control bank during a third stage coarse tuning according to an embodiment of the present invention.
14 is a structural diagram of a coarse tuning digital controller according to an embodiment of the present invention.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. Like reference numerals in the drawings denote like elements.

Table 1 below shows a performance comparison between a digitally controlled oscillator and a conventional digitally controlled oscillator according to an embodiment of the present invention.

Parameter Reference # 1 Reference # 2 Reference # 3 Example Process 0.13um CMOS 90nm COMS 90nm COMS 0.13um CMOS Supply voltage
(Supply Voltage) 1.5V 1.4 V 1.4 V 1.2 V Power consumption
(Power Consumption) 3.45mW 25.2 mW 25.2 mW 6.6 mW Center frequency
(Center Frequency) 2.4 GHz 3.6 GHz 915 MHz 2.4 GHz 2.8 GHz Phase noise
(Phase Noise)
@ 1MHz Offset 117.0 dBc / Hz 137 dBc / Hz 135.0 dBc / Hz 120.5 dBc / Hz 116 dBc / Hz Tuning range
(Tuning Range) 20.8% 25% 97.6% 58% Fomt 185.6 dBc / Hz 181.7 dBc / Hz 206 dBc / Hz 195.17 dBc / Hz,
192.01 dBc / Hz, Frequency resolution
(Frequency Resolution)
(SDM not used) 23 kHz 12 kHz 40 kHz 4.8 kHz Area 0.54 mm ² 0.17mm ² 0.44 mm ² 0.22 mm ²

Reference # 1 is a digitally controlled oscillator with a structure that tunes to a capacitance bank (hereinafter abbreviated as Cap Bank) using a passive inductor. The digitally controlled oscillator uses less power than the center frequency of 2.4 GHz, but has a disadvantage in that the tuning range is small.

Reference # 2 is a digitally controlled oscillator with a structure that tunes to a cap bank using a passive inductor. The digitally controlled oscillator has a high center frequency of 3.6 GHz and a high phase noise, but consumes a lot of power and has a small tuning range.

Reference # 3 is a digitally controlled oscillator with a structure that tunes to a cap bank using a passive inductor. The digitally controlled oscillator has a high phase noise and a wide tuning range, but has the disadvantage of consuming a lot of power and having a low output frequency.

The digitally controlled oscillator according to an embodiment of the present invention to be described below has a structure using an active inductor which is not used in the conventional digitally controlled oscillator. The digitally controlled oscillator minimizes the area while maintaining the proper phase noise, and can also increase the frequency resolution when no SDM is used. The digitally controlled oscillator can secure a wide tuning range while maintaining low power consumption by using a three-step tuning structure.

3 is a structural diagram of a digitally controlled oscillator according to an embodiment of the present invention.

The digitally controlled oscillator 300 includes a digitally controlled oscillator core 310, a Coarse Turning Digital Controller 320, a Sigma-Delta Modulator 330 and a 4 (or 8) divider ( 340).

The digitally controlled oscillator core 310 includes a cap bank, an active inductor, a passive inductor, and a negative GM (negative resistor) circuit.

The digitally controlled oscillator core 310 may adjust the oscillation frequency by adjusting the current of the active inductor and adjusting the capacitance of the cap bank (hereinafter, abbreviated as cap).

The CONT <63: 0> signal output from the digital loop filter 130 constitutes a frequency curve of the digitally controlled oscillator core 310.

The SDM_IN <4: 0> signal output from the digital loop filter 130 passes through the sigma-delta modulator 330, and the signal passing through the sigma-delta modulator 330 improves the resolution of the curve. Thus, sigma-delta-modulator 330 allows the minimum frequency resolution required to be implemented.

The coarse tuning digital controller 320 controls a three-stage coarse tuning operation of the digitally controlled oscillator 300.

The coarse tuning digital controller 32 outputs three-phase coarse tuning signals FCONT, DCONT <19: 0> and CAPS <9: 0> signals, and adjusts the frequency in three stages through the three signals. Expand the output of 300) to broadband.

In addition, the coarse tuning digital controller 320 outputs the GCONT <9: 0> and RCONT <9: 0> signals.

A detailed configuration of the coarse tuning digital controller 320 according to an embodiment of the present invention will be described in detail with reference to FIG. 14 below.

The DCO_OUT and DCO_OUTB output from the digitally controlled oscillator core 310 are divided by 4 (or 8) -divider 340 and output to SDM_CLK. The output SDM_CLK is input to the sigma-delta modulator 330.

4 is a circuit diagram of a digitally controlled oscillator core in accordance with an embodiment of the present invention.

Digitally controlled oscillator core 310 includes negative GM 410, cap bank 420, passive inductor 430, and active inductor 440. The components 410, 420, 430, and 440 may be considered to be included directly in the digitally controlled oscillator 300.

Negative GM 410 is composed of a cross-coupled P-Channel MOSFET (PMOS) and N-Channel MOSFET (NMOS).

Passive inductor 430 uses active inductor 440 to offset the reduction in phase noise performance caused by a drop in the Q value of the inductor. That is, the passive inductor 430 and the active inductor 440 are combined in the circuit to minimize phase noise and raise the Q value.

The active inductor 440 tunes the frequency by adjusting the current according to the bit coming into the digital loop filter.

The active inductor 440 includes an active inductor control bank 450 for controlling the active inductor 440. That is, the active inductor can be divided into a first circuit portion configured to provide inductance and a second circuit portion adjusting the amount of current in the MOS to adjust the inductance.

A detailed configuration of the active inductor control bank 450 is shown in detail in FIG. 5.

The FCONT, DCONT <19: 0->, and FCDTW <64: 0> signals are input to the active inductor control bank 450. The SDM_OUT and CDTW <63: 0> signals are input to the MUX 460, and the MUX 460 outputs the FCDTW <64: 0> signal according to the RCONT <9: 0> signal.

To generate the basic frequency curve of the digitally controlled oscillator 300, the current of the active inductor 440 is adjusted in detail by the CDTW <63: 0> and SDM_OUT signals.

In addition, the voltage input to the MOS is adjusted by voltage-dividing the CDTW <63: 0> and SMD_OUT signals. Voltage division is achieved by the RCONT <9: 0> signal. By adjusting the voltage as described above, the current of the active inductor 440 may be adjusted in more detail.

The cap bank 420 cancels out PVT variation (Process Voltage and Temperature Variation). One example of the configuration of the cap bank is described in detail with reference to FIG. 6 below.

5 is a circuit diagram of an active inductor control bank according to an embodiment of the present invention.

As shown, the input signals of the active inductor control bank 450 are FCONT, DCONT <19: 0> and FCDTW <64: 0>. The active inductor control bank 450 controls the active inductor 440 by outputting output signals Cell_OUT and Cell_OUTB based on the input signals.

6 is a circuit diagram of a cap bank according to an embodiment of the present invention.

As shown, the cap bank 420 is comprised of an array of MIM capacitors 610, and can offset PVT variations using the array of MIM capacitors 610.

The output frequency of the digitally controlled oscillator core 310 by attaching a switch 620 in the MIM capacitor to the intermediate node, adjusting the cap value with the switch according to the input signal CAPS <9: 0> coming from the coarse tuning block. Can be adjusted.

Each capacitance is composed of binary weights. This configuration makes it possible to quickly find the desired frequency curve during coarse tuning.

7 illustrates an internal schematic of an active inductor according to an embodiment of the present invention.

Active inductor 440 is PMOS M ₁ 710, M ₂ 712, M ₃ 720, M ₄ 722, M ₅ 730, M ₆ 732, M ₇ 740, M ₈ 742, M ₉ 750, M ₁₀ 752, M ₁₁ 760 and M ₁₂ 762 and include resistors R ₁ 780 and R ₂ 782.

Inductance of the active inductor 440 may be represented by Equation 1 below.

As can be seen in Equation 1, by adjusting the current flowing in the PMOS M ₇ (740), M ₈ (742), M ₉ (750), M ₁₀ (752), M ₁₁ (760) and M ₁₂ (762) By varying the inductance, the oscillation frequency can be adjusted.

The gate of the PMOS M ₁₁ 760 and M ₁₂ 762 is connected to the frequency control bit FCONT. Therefore, the oscillating center frequency is adjusted in accordance with the value of FCONT.

PMOS M ₉ (750) and M ₁₀ (752) were connected to DCONT <19: 0>. Thus, according to the value of DCONT <19: 0>, the narrow-frequency tuning range curve is adjusted.

Adjusting the amount of current by the size of the MOS is limited. Thus, the desired resolution is achieved by adjusting the voltage level of the MOS gate.

R ₁ 780 and R ₂ 782 scale down the digital value CONT <63: 0> coming from the digital loop filter to a predetermined voltage level.

The frequency can be fine tuned by controlling the PMOS arrays M ₇ 740 and M ₈ 742 with the scaled down digital values CONT <63: 0>.

In addition, due to the output signal SDM_OUT of the sigma-delta modulator 330, the minimum resolution value implemented in the PMOS array is divided by 25. This improves the resolution of the frequency to be implemented.

8 is a flowchart illustrating a three-step coarse tuning method according to an embodiment of the present invention.

Three stage coarse tuning is intended for automatic tuning of digitally controlled oscillator circuits and frequencies. Three-stage coarse tuning changes the active inductance to have wide frequency tuning zeroes.

The basic concept of three-phase coarse tuning is as follows.

The first concept is to have a cap bank 420 having a mid-band tuning region.

A second concept is to add a FCONT control signal that can extend the tuning range of the cap bank 420. The FCONT control signal extends the tuning range of the cap bank 420 by shifting the frequency curve of the cap bank 420 up and down according to the value of CAPS <9: 0>.

There is a limit to the resolution of the frequency curve that can be realized by the cap bank 420.

The third concept is to overcome the limitations of the frequency curve resolution that the active inductor 440 can implement with the cap bank 420 described above by generating a frequency curve again using DCONT <19: 0>.

In step S810, first step coarse tuning is performed. The first stage coarse tuning is wideband-frequency range tuning.

FCONT is determined in the first stage coarse tuning. The FCONT determined in the first stage coarse tuning may adjust the oscillating center frequency by adjusting the main current of the active inductor 440, thereby implementing a wideband-tuning range of 1.4 GHz.

In step S820, a second step coarse tuning is performed. The second stage coarse tuning is mid band-frequency range tuning.

In the second stage coarse tuning, CAPS <9: 0> is determined. The CAP <9: 0> determined in the second stage coarse tuning may adjust the oscillation frequency by adjusting the capacitance of the cap bank 420, thereby implementing a mid-band tuning range of 0.9 GHz.

In step S830, a third step coarse tuning is performed. The third stage coarse tuning is narrowband-frequency range tuning.

In the third stage coarse tuning, DCONT <19: 0> is determined. The DCONT <19: 0> determined in the third stage coarse tuning may adjust the oscillation frequency by adjusting the sub current of the active inductor 440, thereby implementing a narrowband-tuning range of 2.7 MHz. have.

The third stage coarse tuning adjusts the active inductor to cover the second stage coarse tuning range.

In addition, in implementing the frequency curve of the digitally controlled oscillator core 310, a resolution of 0.14 kHz may be implemented through the CDTW <63: 0> and the sigma-delta modulator 330.

9 illustrates the operation of the digital control generator during the first stage coarse tuning according to an embodiment of the present invention.

In FIG. 9, a portion of the above-described digitally controlled oscillator core 310 operating during first stage coarse tuning is displayed.

In a first stage coarse tuning, a frequency band is determined.

The first stage coarse tuning is wideband-frequency range tuning. The inductance of the active inductor 440 varies greatly with FCONT, which adjusts the main current of the active inductor 440. As the inductance changes significantly, the oscillating center frequency changes. By using this change of frequency, the desired frequency band can be selected.

Each frequency band has a difference in the GHz band.

Once the frequency band is determined, two stage coarse tuning is started.

10 illustrates an operation of an active inductor control bank during first stage coarse tuning according to an embodiment of the present invention.

In FIG. 10, the portion of the above-described active inductor control bank 450 operating in the first stage coarse tuning is shown.

It can be seen that the part associated with the input signal FCONT operates.

11 illustrates an operation of a digital control generator during second stage coarse tuning according to an embodiment of the present invention.

In FIG. 11, a portion of the digitally controlled oscillator core 310 described above, which operates during the second stage coarse tuning, is displayed.

The second stage coarse tuning is mid-frequency range tuning, which uses CAPS <9: 0>, which is the control signal of the cap bank 420 of the digitally controlled oscillator core 310.

Using the change in the frequency curve in accordance with CAPS <9: 0>, the frequency curve is determined by finding the required frequency curve. Prior to entering fine tuning, a frequency tuning range that varies with the Least Significant Bit (LSB) of the cap bank 420 should be able to be covered in fine tuning.

That is, Equation 2 below must be satisfied before fine tuning.

In fine tuning to fine-tune the frequency, as the resolution is increased by minimizing the frequency variation per beat, the area covered by the fine tuning is relatively small. As resolution decreases, the area covered by fine tuning increases, which goes against the goal of increasing resolution in fine tuning. Thus, three stage narrowband frequency tuning is required.

12 illustrates the operation of the digital control generator during the third stage coarse tuning according to an embodiment of the present invention.

In FIG. 12, a portion of the digitally controlled oscillator core 310 described above, which operates during the third stage coarse tuning, is displayed.

The third stage coarse tuning is narrowband-frequency range tuning.

The third stage coarse tuning uses DCONT <19: 0> to fine-tune the current value of the active inductor 440 to produce a tighter frequency curve between the minimum frequency tuning ranges of the cap bank 420.

This tuning method allows a digitally controlled oscillator core 310 having a cap bank 420 having a midband frequency tuning region to have a wideband frequency tuning region.

In addition, in the cap bank 420, the frequency variation according to the LSB is relatively large. This amount of change is covered in the active inductor 440.

FIG. 13 illustrates an operation of an active inductor control bank during a third stage coarse tuning according to an embodiment of the present invention.

In FIG. 13, the portion of the above-described active inductor control bank 450 operating in the third stage coarse tuning is indicated.

It can be seen that the part associated with the input signal DCONT <19: 0> is operating.

14 is a structural diagram of a coarse tuning digital controller according to an embodiment of the present invention.

The coarse tuning digital controller 320 may include a K-divider 1410, an M-bit counter 1420, a reference divider 1430, a digital comparator 1440, and a coarse tuning map table ( Map table 1450 and a three-stage tuning controller 1460.

K-divider 1410 divides the frequency of digitally controlled oscillator 300.

The M-bit counter 1420 counts the divided clock.

The reference divider 1430 controls the M-bit counter 1420.

The digital comparator 1440 compares the value counted in the M-bit counter.

Coarse tuning map table 1450 converts the required frequency into M-bits.

The three stage tuning controller 1460 controls the digitally controlled oscillator 300 or the digitally controlled oscillator core 310.

As much as the capacitance is required for a digitally controlled oscillator to have a wide tuning range with only the cap bank as in the conventional approach. The digitally controlled oscillator core 310 according to an embodiment of the present invention can tune even with a much smaller amount of capacitance. Thus, digitally controlled oscillator 300 has an advantage in area.

In addition, according to the conventional method, the slope of the frequency curve changes toward the wide band. That is, the amount of change in the gain value of the digitally controlled oscillator has a different value for each frequency curve. This characteristic affects phase noise.

However, in the case of the frequency curve actually used in one embodiment of the present invention, the region of the frequency curve itself has a narrow band range. Therefore, the influence on the page noise is small.

After the three-step coarse tuning described above, the frequency curve and the frequency tuning region of the digitally controlled oscillator core 310 are determined according to the output values FCON and CAPS <9: 0>. The frequency tuning region of the capacitance actually constructed as a result of the frequency curve and the frequency tuning region is about 0.9 GHz. This indicates that an effect of about 1.4 GHz was obtained by three stages of coarse tuning.

Method according to an embodiment of the present invention is implemented in the form of program instructions that can be executed by various computer means may be recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of the computer-readable recording medium include magnetic media such as a hard disk, a floppy disk and a magnetic tape, optical recording media such as CD-ROM and DVD, magnetic recording media such as a floppy disk Optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

100: digital phase locked loop
300: digitally controlled oscillator
310: digitally controlled oscillator core
320: coarse tuning digital controller

Claims (1)

Negative resistance, which is a cross-couple of PMOS and NMOS;
An active inductor tuning the frequency;
A passive inductor using the active inductor to offset reduction in phase noise performance; And
Cap banks to offset PVT changes
Including, a digitally controlled oscillator.

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