KR20120006705A - Nonvolatile memory device and phase change memory device - Google Patents

Abstract

PURPOSE: A nonvolatile memory device and a phase change memory device are provided to perform a data write operation at various clock frequencies by storing an operation mode corresponding to various clock frequencies in a mode register. CONSTITUTION: A cell array(100) includes a plurality of unit cells. A write driving unit(400) writes data in a unit cell. A buffer control circuit includes a data input buffer, a buffer control circuit, and a mode register. The write operation speed of the data input buffer is controlled according to an operation mode.

Description

Nonvolatile memory device and phase change memory device

Embodiments of the present invention relate to a nonvolatile memory device.

Among semiconductor memory devices, a memory device having a characteristic of storing data even when power is not supplied is referred to as a nonvolatile memory device. Among the nonvolatile memories, phase change memory (Phase Change Memory), although non-volatile, is characterized by having a data processing speed of about volatile dynamic random access memory (DRAM).

1A and 1B show a phase change resistor (PCR) element 4 according to the prior art.

1A and 1B, the phase change resistance element 4 is formed by inserting a phase change material (PCM) 2 between the upper electrode 1 and the lower electrode 3. When a voltage is applied to the upper electrode 1 and the lower electrode 3, current flows through the phase change material 2 to change the temperature and change the electrical conduction state.

2A and 2B are diagrams for explaining the principle of data storage of the phase change resistance element 4 according to the prior art.

Referring to FIG. 2A, when a current below a threshold flows through the phase change resistance element 4, the phase change material 2 is crystallized. When the phase change material 2 is in a crystalline phase, it becomes a material of low resistance. As a result, a current can flow between the upper electrode 1 and the lower electrode 3.

Meanwhile, referring to FIG. 2B, when a current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change material 2 is higher than the melting point. When the phase change material 2 melts into an amorphous phase, it becomes a material of high resistance. As a result, a current hardly flows between the upper electrode 1 and the lower electrode 3.

Accordingly, the phase change resistive element 4 can correspond to different data in the above two states. For example, the phase change resistance element 4 can correspond to a low resistance state to data "1" and a high resistance state to data "0".

In addition, since the state of the phase change material 2 does not change even when the power to the phase change memory device is turned off, the above data can be stored non-volatilely.

3 is a graph illustrating a write operation of a phase change resistance cell according to the prior art.

Referring to FIG. 3, when current flows between the upper electrode 1 and the lower electrode 3 of the phase change resistance device 4 for a predetermined time, heat is generated.

When a current below a threshold flows for a predetermined time, the phase change material 2 is in a crystallized state by the low temperature heating state. As a result, the phase change resistance element 4 is in a Set state.

On the contrary, when a current above a threshold flows for a predetermined time, the phase change material 2 becomes an amorphous state due to the high temperature heating state. As a result, the phase change resistance element 4 is in a reset state.

Using this property, a low voltage is applied to the phase change resistance element 4 for a long time to write the set state in the write operation.

On the contrary, a high voltage is applied to the phase change resistance element 4 for a short time to write the reset state in the write operation.

The phase change resistance memory senses data written to the phase change resistance element 4 by applying a sensing current to the phase change resistance element 4 during the sensing operation.

Embodiments of the present invention relate to a technique for controlling write operation characteristics of data to be written input from an external system.

According to an embodiment of the present invention, a nonvolatile memory device includes a cell array including unit cells, a write driver for writing data to unit cells, and data to be written to unit cells from an external system, and are written according to an operation mode. And a data input circuit for controlling the operation speed.

The embodiment of the present invention has an advantage in that it is possible to control the write operation characteristic of the data to be written, for example, the write operation speed, which is input from the external system.

In addition, the embodiment of the present invention can store an operation mode corresponding to various clock frequencies in a mode register, thereby providing an effect of performing a data write operation at various clock frequencies.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1A and 1B are views for explaining a phase change resistance device according to the prior art.
2A and 2B are diagrams for explaining the principle of data storage of a phase change resistance device according to the prior art;
3 is a graph illustrating a write operation of a phase change resistance cell according to the prior art.
4 illustrates a nonvolatile memory device according to an embodiment of the present invention.
5 is a diagram illustrating a data input circuit of a nonvolatile memory device according to an embodiment of the present invention.
6 illustrates a buffer control circuit of a nonvolatile memory device according to an embodiment of the present invention.
7 is a circuit diagram illustrating a data input buffer of a nonvolatile memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 illustrates a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 4, a nonvolatile memory device according to an embodiment of the present invention includes a cell array 100, a local column switch 200, a global column switch 300, a sense amplifier and a write driver 400, and a sensing reference voltage. The generator 500 includes a data transmitter 600, a data output driver 700, a data input circuit 800, and a data input / output pad 900.

The cell array 100 includes a plurality of unit cells. Each of the plurality of unit cells includes a memory device, and data is stored in the memory device.

As the memory device, various devices may be used. For example, a ferroelectric capacitor, a phase change resistance element, a spin torque transfer (STT) element, a magnetoresistive element, or the like may be used.

One side of the unit cell is connected to the local column switch 200 through bit lines BL1 to BLN.

For example, the unit cell may have a column connected to the local column switch 200 through the bit lines BL1 to BLN.

The local column switch 200 selects a specific bit line among the plurality of bit lines BL1 to BLN to sense data stored in a unit cell connected to the specific bit line or to write data to the unit cell.

The local column switch 200 is connected to the global column switch 300 through the global bit line GBL.

The global column switch 300 controls whether the cell array 100 is selected according to the global switching signal GYSW.

For example, when the global switching signal GYSW is activated, the global column switch 300 includes the sensing voltage or the write voltage applied from the sense amplifier and the write driver 400 to the cell array 100 through the local column switch 200. The supplied unit cells.

On the contrary, when the global switching signal GYSW is deactivated, the sensing voltage or the write voltage applied from the global column switch 300 sense amplifier and the write driver 400 is not supplied. As a result, the read / write operation of the entire cell array 100 is not performed.

The sense amplifier and the write driver 400 perform a read / write operation on the unit cell included in the cell array 100.

When a specific bit line is selected by the local column switch 200 while the global switching signal GYSW is activated, a read / write operation is performed on a unit cell connected to the specific bit line.

During the read operation, when the data is output through the data data line SAI stored in the unit cell, the sense amplifier and the write driver 400 compare the signal input through the data line SAI with the sensing reference voltage VSREF.

For example, when the signal input through the data line SAI is greater than the sensing reference voltage VSREF, the sense amplifier and the write driver 400 determine that the data is "1". On the contrary, when the signal input through the data line SAI is smaller than the sensing reference voltage VSREF, the sense amplifier and the write driver 400 determine that the data is "0".

The sense amplifier and the write driver 400 may include a differential amplifier circuit for differentially amplifying a signal input through the data line SAI and the sensing reference voltage VSREF.

Meanwhile, the write driver applies a write voltage to the cell array 100 in accordance with data to be written from the outside during the write operation.

For example, when writing data “1”, the sense amplifier and write driver 400 writes the first level to the unit cell connected to the bit line selected through the global column switch 300 and the local column switch 200. Supply the voltage.

On the contrary, when writing the data "0", the sense amplifier and the write driver 400 may write the write voltage of the second level to the unit cell connected to the bit line selected through the global column switch 300 and the local column switch 200. Supply.

If the unit cell of the cell array 100 includes a phase change resistance element, data may be written in various ways by adjusting the voltage level of the write voltage or the application time of the write voltage.

The sensing reference voltage generator 500 generates the sensing reference voltage VSREF and supplies the sensed reference voltage VSREF to the sense amplifier and the write driver 400.

The data transfer unit 600 receives the data determined by the sense amplifier and the write driver 400 through the global input / output line GIO. The data transfer unit 600 drives the determined data and transfers the data to the data output driver 700.

When the sense amplifier and write driver 400 and the data output driver 700 are simply connected by the global input / output line GIO, the data may be distorted by the line resistance of the global input / output line GIO. However, when the data is driven and transmitted once in the middle using the data transfer unit 600, the determined data may be accurately transmitted to the data output driver 700.

The data output driver 700 drives a signal input from the data transmitter 600 through the global input / output transmission line GIO_RPT, and outputs the driven data to an external system through the data input / output pad 900.

When the data output driver 700 drives and outputs a signal, distortion of a signal that may occur due to line resistance may be minimized.

The data input / output pad 900 outputs data driven by the data output driver 700 to an external system.

In the write operation, the data input / output pad 900 receives a signal corresponding to data to be written from an external system.

The input signal is input to the data input circuit 800 through the data input line D_IN.

The data input circuit 800 drives the data to be written and transmits the data to the data transfer unit 600. In this case, the data input circuit 800 may include a buffer circuit.

The data input circuit 800 of the nonvolatile memory device according to an embodiment of the present invention can control the write operation characteristic.

For example, the data input circuit 800 may control the write operation speed. In particular, the data input circuit 800 can control the clock frequency.

The data input circuit 800 may operate in a plurality of operation modes by a control signal input from an external system. Each mode of operation may be set to have a different clock frequency.

In addition, the data input circuit 800 may include a mode register therein and operate in a plurality of operation modes stored in the mode register. Each mode of operation may be set to have a different clock frequency.

As such, the data input circuit 800 of the nonvolatile memory device according to an exemplary embodiment of the present invention may set an operation mode by a control of an external system or a mode register included therein to perform write operations at different clock frequencies. Will be.

5 illustrates a data input circuit 800 of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 5, a data input circuit 800 of a nonvolatile memory device according to an embodiment of the present invention may include a mode register 810, a buffer control circuit 820, a data input buffer 830, and a reference voltage generator ( 840).

The mode register 810 stores information about an operation mode. The mode register 810 outputs different mode control signals RWL according to the operation mode.

Table 1 shows that the mode register 810 outputs different mode control signals RWL according to the operation mode in the nonvolatile memory device according to the embodiment of the present invention.

RWL
Mode register Mode 1 Mode 2 Mode 3 Mode 4 RWL1 0 0 0 One RWL2 0 0 One 0 RWL3 0 0 One One RWL4 0 One 0 0 RWL5 0 One 0 One RWL6 0 One One 0

Referring to Table 1, for example, the mode register 810 outputs all of the mode control signals RWL1 to RWL6 to 0 in mode 1, and the mode control signals RWL1 to RWL3 to 0 in mode 2 and the mode control signal RWL4. Output RWL6 to 1, output mode control signals RWL1, RWL4, RWL5 to 0 in mode 3, mode control signals RWL2, RWL3, RWL6 to 1, and mode control signals RWL2, RWL4, RWL6 to 0 in mode 4. Outputs the mode control signals RWL1, RWL3, RWL5 to 1.

As such, the mode register 810 may output mode control signals RWL1 to RWL6 corresponding to various operation modes.

Each of these various operation modes may be set to represent different write operation characteristics. For example, the various modes of operation are set to have different clock frequencies such that the data input buffer 830 can perform data write operations at different clock frequencies.

The buffer control circuit 820 generates the activation signal EN according to the buffer activation signal BUF_EN.

For example, when the buffer activation signal BUF_EN is activated and input, the buffer control circuit 820 outputs the activation signal EN in an activated state so that the data input buffer 830 performs a driving operation.

On the contrary, when the buffer activation signal BUF_EN is deactivated and input, the buffer control circuit 820 outputs the activation signal EN in an inactive state so that the data input buffer 830 does not perform a driving operation.

The buffer control circuit 820 generates the write control signal WL according to the mode control signal RWL output from the mode register 810.

The write control signal WL represents a signal for controlling the write operation characteristic of the data input buffer 830. The write control signal WL may control the write operation characteristic of the data input buffer 830. For example, the write control signal WL allows the data input buffer 830 to perform write operations at different clock frequencies.

The data input buffer 830 drives the data to be written which is input from the external system through the data input / output pad 900 and outputs the data to the cell array 100.

The data input buffer 830 is controlled by the activation signal EN output from the buffer control circuit 820.

For example, when the activation signal EN is input in an activation state, the data input buffer 830 performs a driving operation. In contrast, when the activation signal EN is input in an inactive state, the data input buffer 830 does not perform a driving operation.

When the activation signal EN is input in an activated state, the data input buffer 830 compares and drives the signal input through the data input line D_IN with a reference voltage VREF.

For example, the data input buffer 830 may include a differential amplifier circuit for differentially amplifying a signal input through the data input line D_IN and a reference voltage VREF.

The data input buffer 830 is characterized in that the write operation is controlled according to the write control signal WL. For example, the data input buffer 830 may perform a write operation at different clock frequencies according to the write control signal WL.

The reference voltage generator 840 generates a reference voltage VREF and supplies it to the data input buffer 830.

6 illustrates a buffer control circuit 820 of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 6, the buffer control circuit 820 of the nonvolatile memory device generates an activation signal EN and a write control signal WL according to the buffer activation signals BUF_EN and the mode control signals RWL1 to RWL6.

For example, the buffer control circuit 820 may generate an activation signal EN by performing a logic operation on the buffer activation signal BUF_EN and the mode control signal RWL1.

For example, the buffer control circuit 820 may generate a write control signal WL1 by performing a logical operation on the buffer activation signal BUF_EN and the mode control signals RWL2 and RWL3.

For example, the buffer control circuit 820 may generate a write control signal WL2 by performing a logic operation on the buffer activation signal BUF_EN and the mode control signal RWL4.

For example, the buffer control circuit 820 may generate a write control signal WL3 by performing a logical operation on the buffer activation signal BUF_EN and the mode control signals RWL5 and RWL6.

As such, the buffer control circuit 820 generates the activation signals and the write control signals WL1 to WL3 according to the buffer activation signals BUF_EN and the mode control signals RWL1 to RWL6, so that the data input buffer 830 can operate in various light operation modes. do.

The configuration of the buffer control circuit 820 illustrated in FIG. 6 is not limited to the logic element illustrated in FIG. 6, and may be implemented using various logic elements.

7 is a circuit diagram illustrating a data input buffer 830 of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 7, the data input buffer 830 of the nonvolatile memory device according to an embodiment of the present invention includes a differential amplifier circuit 831 for differentially amplifying a signal input through the data input line D_IN and a reference voltage VREF. do.

The differential amplifier circuit 831 includes PMOS transistors P5 and P6 that perform precharge operations according to the activation signal EN.

The differential amplifier circuit 831 is connected in parallel with the PMOS transistors P5 and P6, and the PMOS transistor P6 includes the PMOS transistors P7 and P8 having a gate connected to the drain terminal in common.

The differential amplifier circuit 831 includes an NMOS transistor N4 having a channel connected in series to the PMOS transistor P5 and a data input line D_IN connected to a gate terminal.

The differential amplifier circuit 831 includes an NMOS transistor N5 in which a channel is connected in series to the PMOS transistor P6 and a reference voltage VREF is input to the gate terminal.

The differential amplification circuit 831 includes NMOS transistors N7 to N9 in which a channel is connected between a node connected to each source terminal of the NMOS transistor N4 and the NMOS transistor N5 and a ground terminal, and the write control signals WL1 to WL3 are input to the respective gate terminals. It includes.

NMMOS transistors N7 ~ N9 act as current sources.

PMOS transistors P5 to P8 are pulled up.

The driving capability of the data input buffer 830 of the nonvolatile memory device according to the embodiment of the present invention varies according to the write control signals WL1 to WL3.

For example, when only the write control signal WL1 is activated and input, only the NMOS transistor N7 operates as a current source to drive the differential amplifier circuit 831.

When the write control signals WL1 to WL3 are all activated and input, the NMOS transistors N7 to N9 all operate as current sources to drive the differential amplifier circuit 831.

As described above, when the driving capability of the differential amplifier circuit 831 is set differently according to the write control signal WL, the clock frequency of the data input buffer 830 is changed during the write operation.

For example, when only the write control signal WL1 is activated, an operation period corresponding to the clock frequency may be set to tck = 3.75ns. When only the write control signal WL2 is activated, an operation period corresponding to the clock frequency may be set to tck = 2 / 5ns. When only the write control signal WL3 is activated, an operation period corresponding to the clock frequency may be set to tck = 2 / 15ns.

As such, the data input buffer 830 of the nonvolatile memory device according to the embodiment of the present invention may set the operation speed of the write operation differently according to the write control signal WL.

Claims (20)

A cell array including a plurality of unit cells;
A write driver which writes data to the unit cell; And
And a data input circuit configured to receive data to be written to the unit cell from an external system and to control a write operation speed according to an operation mode. The circuit of claim 1, wherein the data input circuit is
A data input buffer for driving and outputting the data to be written;
A buffer control circuit for controlling a write operation speed of the data input buffer according to the operation mode; And
And a mode register for storing the operation mode and outputting another mode control signal to the buffer control circuit in accordance with the operation mode. The method of claim 2, wherein the data input buffer is
And a driving operation is activated by an activation signal. The method of claim 3, wherein the data input buffer is
And determining data by comparing a reference voltage with the data to be written. The method of claim 4, wherein the light driving unit
And writing the data determined in the data input buffer to the unit cell. The nonvolatile memory device of claim 4, further comprising a reference voltage generator configured to generate the reference voltage. 3. The data input circuit of claim 2, wherein the data input circuit is
And controlling an operating speed by controlling a clock frequency in accordance with the operation mode. 8. The method of claim 7, wherein the mode register is
And storing a plurality of operation modes corresponding to the clock frequency. The method of claim 8, wherein the buffer control circuit is
And a control signal for controlling an operation speed of the data input buffer according to the mode control signal. 10. The method of claim 9, wherein the data input buffer is
And a driving capability is controlled by the control signal. A cell array including a plurality of phase change memory cells;
A write driver to write data of the phase change memory cell; And
And a data input circuit configured to receive data to be written to the unit cell from an external system, and to control a write operation speed according to an operation mode. 12. The apparatus of claim 11, wherein the data input circuit is
A data input buffer for driving and outputting the data to be written;
A buffer control circuit for controlling a write operation speed of the data input buffer according to the operation mode; And
And a mode register for storing the operation mode and outputting different mode control signals to the buffer control circuit according to the operation mode. The method of claim 12, wherein the data input buffer is
And a driving operation is activated by an activation signal. The method of claim 13, wherein the data input buffer is
And changing data by comparing a reference voltage with the data to be written. 15. The method of claim 14, wherein the light driving unit
And write the data determined in the data input buffer to the phase change memory cell. The method of claim 14,
And a reference voltage generator configured to generate the reference voltage. 13. The apparatus of claim 12, wherein the data input circuit is
And operating speed by controlling a clock frequency in accordance with the operation mode. 18. The method of claim 17, wherein the mode register is
And storing a plurality of operation modes corresponding to the clock frequency. 19. The circuit of claim 18, wherein the buffer control circuit is
And a control signal for controlling an operation speed of the data input buffer according to the mode control signal. 20. The apparatus of claim 19, wherein the data input buffer is
And a driving capability is controlled by the control signal.

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