KR20120005847A - Non volatile memory device - Google Patents

Non volatile memory device Download PDF

Info

Publication number
KR20120005847A
KR20120005847A KR1020100066525A KR20100066525A KR20120005847A KR 20120005847 A KR20120005847 A KR 20120005847A KR 1020100066525 A KR1020100066525 A KR 1020100066525A KR 20100066525 A KR20100066525 A KR 20100066525A KR 20120005847 A KR20120005847 A KR 20120005847A
Authority
KR
South Korea
Prior art keywords
data
output
bank
gdl
input
Prior art date
Application number
KR1020100066525A
Other languages
Korean (ko)
Inventor
김보겸
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100066525A priority Critical patent/KR20120005847A/en
Publication of KR20120005847A publication Critical patent/KR20120005847A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

PURPOSE: A nonvolatile memory device is provided to improve a data input and output speed by supporting a synchronous mode. CONSTITUTION: An IO pad(110) receives external input data and synchronizes the external input data with a rising edge and a falling edge of a data strobe signal to output the first input data and the second input data. A latch unit(120) divides the first input data and the second input data into a plurality of bank data according to a bank selection signal. A plain mux unit(130) outputs a plurality of bank data into a plurality of plain data according to a plain selection signal. A sense amplification group receives a plurality of plain data and transmits the plurality of plain data to a page buffer group.

Description

 Non volatile memory device

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device capable of performing data input and output operations in synchronization with an external system clock.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

Among nonvolatile memory devices, flash memory devices generally support only asynchronous mode and thus cannot support the synchronous mode described in the Open NAND Flash Interface (ONFI) specification.

1 is a block diagram illustrating a data input circuit of a nonvolatile memory device according to the prior art.

Referring to FIG. 2, the data input circuit includes a latch unit 12 for latching a plurality of data input from an IO pad 11 and an IO pad 11 to which data is input from the outside and outputting the data to a plurality of global data lines. It includes.

 The IO pad 11 receives external input data in synchronization with a write signal WE # activated during a data input operation. At this time, the external input data received is synchronized sequentially when the write signal WE # transitions from the low level to the high level, and the data DIN <7: 0> is input to the latch unit 12 through one data line. Is sent.

The latch unit 12 transmits data to a plurality of global data lines in response to the data strobe clock DCLK and the bank select signal SEL_BANK. In this case, the plurality of global data lines are divided into banks and have two data lines (even and odd) per bank.

The data input circuit of the nonvolatile memory device according to the related art described above is synchronized with data when the write signal WE # transitions from low level to low level when data is input through the IO pad 11. Synchronous mode could not be supported because it is sequentially input.

2 is a block diagram illustrating a data output circuit of a nonvolatile memory device according to the related art.

Referring to FIG. 2, the data output circuit receives a plurality of output data and outputs the mux part 22 and the data DOR <7: 0> received from the mux part 22 to output to the IO pad. IO pad 21 for outputting is included.

The mux unit 22 selects even output data IOOUT_EV <7: 0> or odd output data IOOUT_OD <7: 0> in response to the address signal AX <0> and selects the selected data DOR <7: 0>) to the IO pad 21.

The IO pad 21 synchronizes the transmitted data DOR <7: 0> with the read signal RE # and outputs it externally.

The data output circuit of the conventional nonvolatile memory device synchronizes the data DOR <7: 0> when the read signal RE # transitions from the low level to the high level when outputting data to the outside. Synchronous mode could not be supported.

An object of the present invention is to input and output data in the data input and output circuit of the nonvolatile memory device when the data strobe signal transitions from the low level to the high level and input and output when the transition from the high level to the low level The present invention provides a data input circuit and a data output circuit of a nonvolatile memory device having improved data input / output operation speed by allowing data to be synchronized so that the data input / output operation supports a synchronous mode.

According to an embodiment of the present invention, an nonvolatile memory device receives an external input data and synchronizes it with a rising edge and a falling edge of a data strobe signal, respectively, and outputs the first input data and the second input data, and A latch unit for dividing the first input data and the second input data into a plurality of bank data according to a bank selection signal, and for dividing the plurality of bank data into a plurality of plane data according to a plane selection signal. It contains a plain mux.

The IO pad is configured to input the external data in a synchronous mode in synchronization with the data strobe signal.

A nonvolatile memory device according to another embodiment of the present invention may include a page buffer group for sensing and outputting data stored in a plurality of memory cell blocks, and a plurality of data output from the page buffer group to group first and second data. A mux circuit for outputting the output data and an IO pad for receiving the first and second output data and synchronizing them with the rising and falling edges of the clock signal, respectively, and outputting the external output data.

The mux circuit senses the data output from the page buffer group and outputs it as global data, and a plane mux for grouping the global data into plane data in response to a plane selection signal and outputting it as bank data. A bank mux for grouping the bank data into banks in response to a bank selection signal and outputting the bank data into even data and odd data, and outputting the even data and odd data in response to an address signal to the first output data; And an even odd mux for outputting the second output data.

According to an exemplary embodiment of the present invention, when a data strobe signal transitions from a low level to a high level and when a data strobe signal transitions from a low level to a high level when data is input or output from a data input and output circuit of a nonvolatile memory device, an input / output is performed. By synchronizing the data so that the data input / output operation supports the synchronous mode, the data input / output operation speed is improved.

1 is a block diagram illustrating a data input circuit of a nonvolatile memory device according to the prior art.
2 is a block diagram illustrating a data output circuit of a nonvolatile memory device according to the related art.
3 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.
4 is a waveform diagram of data and signals for explaining a data input operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.
5 is a block diagram illustrating a nonvolatile memory device according to another embodiment of the present invention.
FIG. 6 is a waveform diagram illustrating data and signals for explaining a data output operation of a nonvolatile memory device according to another exemplary embodiment.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

3 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3, the nonvolatile memory device includes an IO pad 110, a latch unit 120, a plane mux unit 130, a sense amplifier group 140, and a page buffer group 150.

The IO pad 110 receives external input data in synchronization with the data strobe signal DQS, and receives the latch unit as the first input data DINR <7: 0> and the second input data DINF <7: 0>. 120). More specifically, the external input data is synchronized to the rising edge of the data strobe signal DQS to transmit the first input data DINR <7: 0> to the latch unit 120, and the external input data is transmitted to the data strobe signal ( The second input data DINF <7: 0> is transmitted to the latch unit 120 in synchronization with the falling edge of the DQS. This enables the synchronous mode for data input operation.

The latch unit 120 receives the first input data DINR <7: 0> and the second input data received from the IO pad 110 in response to the data strobe clock DCLK and the bank select signal SEL_BANK. DINF <7: 0>) divided into banks (GDL_EV_B0 <7: 0>, GDL_OD_B0 <7: 0>, GDL_EV_B1 <7: 0>, GDL_OD_B1 <7: 0>) into multiple global data lines. At this time, a number of global data lines are divided into banks and have two data lines (even and odd) per bank. The IO pad 110 and the latch unit 120 are connected to at least two data lines that transmit the first input data DINR <7: 0> and the second input data DINF <7: 0>.

The plane mux unit 130 inputs a plurality of data GDL_EV_B0 <7: 0>, GDL_OD_B0 <7: 0>, GDL_EV_B1 <7: 0>, and GDL_OD_B1 <7: 0> output from the latch unit 120. In response to the plane selection signal SEL_PLANE, a plurality of pieces of data GDL_EV_B0 <7: 0>, GDL_OD_B0 <7: 0>, GDL_EV_B1 <7: 0>, and GDL_OD_B1 <7: 0> are divided by planes. Data (GDL_EV_BO_PO <7: 0>, GDL_OD_BO_PO <7: 0>, GDL_EV_B1_PO <7: 0>, GDL_OD_B1_PO <7: 0>, GDL_EV_BO_P1 <7: 0>, GDL_OD_BO_P1 <7: 0>, GDL_EV_B_B_B , GDL_OD_B1_P1 <7: 0>).

The sense amplifier group 140 includes a plurality of sense amplifier circuits SA, and each of the sense amplifier circuits SA is output from the plane mux unit 130 and includes a plurality of data (GDL_EV_BO_PO <7: 0>, GDL_OD_BO_PO < 7: 0>, GDL_EV_B1_PO <7: 0>, GDL_OD_B1_PO <7: 0>, GDL_EV_BO_P1 <7: 0>, GDL_OD_BO_P1 <7: 0>, GDL_EV_B1_P1 <7: 0>, GDL_OD_B1_P1 <7: 0>) Receives and outputs it to the page buffer 150.

The page buffer group 150 includes a plurality of page buffer units PB, and the plurality of page buffer units PB correspond to one memory cell block (not shown). The page buffer group 150 includes a plurality of data (LID_EV_BO_PO <7: 0>, LID_OD_BO_PO <7: 0>, LID_EV_B1_PO <7: 0>, LID_OD_B1_PO <7: 0>, received from the sense amplifier group 140. LID_EV_BO_P1 <7: 0>, LID_OD_BO_P1 <7: 0>, LID_EV_B1_P1 <7: 0>, LID_OD_B1_P1 <7: 0>) are transferred to the memory cell block for programming.

4 is a waveform diagram of data and signals for explaining a data input operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

A data input operation of a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4 as follows.

First, external input data D0 to D15 are sequentially input through the IO pad 110. The IO pad 110 receives external input data in synchronization with the data strobe signal DQS generated using the external clock CLK, and receives the first input data DINR <7: 0> and the second input data DINF. <7: 0>) to the latch unit 120. More specifically, the external input data is synchronized to the rising edge of the data strobe signal DQS to transmit the first input data DINR <7: 0> to the latch unit 120, and the external input data is transmitted to the data strobe signal ( The second input data DINF <7: 0> is transmitted to the latch unit 120 in synchronization with the falling edge of the DQS. This enables the synchronous mode for data input operation. In this case, the first input data DINR <7: 0> and the second input data DINF <7: 0> are transmitted to the latch unit 120 through different wires.

The latch unit 120 receives the first input data DINR <7: 0> and the second input data received from the IO pad 110 in response to the data strobe clock DCLK and the bank select signal SEL_BANK. DINF <7: 0>) divided into banks (GDL_EV_B0 <7: 0>, GDL_OD_B0 <7: 0>, GDL_EV_B1 <7: 0>, GDL_OD_B1 <7: 0>) into multiple global data lines. Output The plane mux unit 130 inputs a plurality of data GDL_EV_B0 <7: 0>, GDL_OD_B0 <7: 0>, GDL_EV_B1 <7: 0>, and GDL_OD_B1 <7: 0> output from the latch unit 120. In response to the plane selection signal SEL_PLANE, a plurality of pieces of data GDL_EV_B0 <7: 0>, GDL_OD_B0 <7: 0>, GDL_EV_B1 <7: 0>, and GDL_OD_B1 <7: 0> are divided by planes. Data (GDL_EV_BO_PO <7: 0>, GDL_OD_BO_PO <7: 0>, GDL_EV_B1_PO <7: 0>, GDL_OD_B1_PO <7: 0>, GDL_EV_BO_P1 <7: 0>, GDL_OD_BO_P1 <7: 0>, GDL_EV_B_B_B , GDL_OD_B1_P1 <7: 0>). The sense amplifier group 140 includes a plurality of sense amplifier circuits SA, and each of the sense amplifier circuits SA is output from the plane mux unit 130 and includes a plurality of data (GDL_EV_BO_PO <7: 0>, GDL_OD_BO_PO < 7: 0>, GDL_EV_B1_PO <7: 0>, GDL_OD_B1_PO <7: 0>, GDL_EV_BO_P1 <7: 0>, GDL_OD_BO_P1 <7: 0>, GDL_EV_B1_P1 <7: 0>, GDL_OD_B1_P1 <7: 0> Receives and outputs it to the page buffer 150. The page buffer group 150 includes a plurality of page buffer units PB, and the plurality of page buffer units PB correspond to one memory cell block (not shown). The page buffer group 150 includes a plurality of data (LID_EV_BO_PO <7: 0>, LID_OD_BO_PO <7: 0>, LID_EV_B1_PO <7: 0>, LID_OD_B1_PO <7: 0>, received from the sense amplifier group 140. LID_EV_BO_P1 <7: 0>, LID_OD_BO_P1 <7: 0>, LID_EV_B1_P1 <7: 0>, LID_OD_B1_P1 <7: 0>) are transferred to the memory cell block for programming.

5 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 5, a nonvolatile memory device includes a page buffer group 510, a sense amplifier group 520, a plane mux unit 530, a bank mux unit 540, an even odd mux unit 550, and an IO pad. 560.

The page buffer group 510 includes a plurality of page buffer units PB, and the plurality of page buffer units PB correspond to one memory cell block (not shown). The page buffer group 510 senses data sensed by sensing programmed data of a plurality of memory cell blocks (LID_EV_BO_PO <7: 0>, LID_OD_BO_PO <7: 0>, LID_EV_B1_PO <7: 0>, LID_OD_B1_PO <7: 0> , LID_EV_BO_P1 <7: 0>, LID_OD_BO_P1 <7: 0>, LID_EV_B1_P1 <7: 0>, LID_OD_B1_P1 <7: 0> are transmitted to the sense amplifier group 520.

The sense amplifier group 520 may output data LID_EV_BO_PO <7: 0>, LID_OD_BO_PO <7: 0>, LID_EV_B1_PO <7: 0>, LID_OD_B1_PO <7: 0>, and LID_EV_BO_P1 <7 from the page buffer group 510. : Sensing the data sensed by sensing: 0>, LID_OD_BO_P1 <7: 0>, LID_EV_B1_P1 <7: 0>, LID_OD_B1_P1 <7: 0>). GDL_EV_BO_PO <7: 0>, GDL_OD_BO_PO <7: 0> 1, GDL_EV_ <7: 0>, GDL_OD_B1_PO <7: 0>, GDL_EV_BO_P1 <7: 0>, GDL_OD_BO_P1 <7: 0>, GDL_EV_B1_P1 <7: 0>, GDL_OD_B1_P1 <7: 0>) Output

The plane mux unit 530 may transmit the global data GDL_EV_BO_PO <7: 0>, GDL_OD_BO_PO <7: 0>, GDL_EV_B1_PO <7: 0>, GDL_OD_B1_PO <7: 0>, and GDL_EV_BO_P1 <7 in response to the plane selection signal SEL_PLANE. : 0>, GDL_OD_BO_P1 <7: 0>, GDL_EV_B1_P1 <7: 0>, GDL_OD_B1_P1 <7: 0>, by grouping the plane data by bank data (GDL_EV_B0 <7: 0>, GDL_OD_B0 <7: 0>, GDL_EV_B1 : 0>, GDL_OD_B1 <7: 0>).

The bank mux unit 540 outputs bank data GDL_EV_B0 <7: 0>, GDL_OD_B0 <7: 0>, GDL_EV_B1 <7: 0>, and GDL_OD_B1 <7: 0> output from the plane mux unit 530 for each bank. Grouping is performed to output even data (IOOUT_EV <7: 0>) and odd output data (IOOUT_OD <7: 0>).

The even-odd mux unit 550 groups the even output data (IOOUT_EV <7: 0>) and the odd output data (IOOUT_OD <7: 0>) output from the bank mux unit 540, and then the address signal AX < 0>) to output the first output signal DOR <7: 0> and the second output signal DOF <7: 0>.

The IO pad 560 receives the first output signal DOR <7: 0> and the second output signal DOF <7: 0> received from the even-odd mux unit 550 in response to the clock signal CLK. ) More specifically, the first output signal DOR <7: 0> is output to the outside in synchronization with the rising edge of the clock signal CLK, and the second output signal DOF is synchronized with the falling edge of the clock signal CLK. Output <7: 0>) to the outside. This enables synchronous mode in data output operation. The IO pad 560 and the even-odd mux unit 550 are at least two data lines for transmitting the first output signal DOR <7: 0> and the second output signal DOF <7: 0>. Connected.

FIG. 6 is a waveform diagram illustrating data and signals for explaining a data output operation of a nonvolatile memory device according to an exemplary embodiment.

A data output operation of a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 5 and 6 as follows.

First, the page buffer group 510 senses the sensed data (LID_EV_BO_PO <7: 0>, LID_OD_BO_PO <7: 0>, LID_EV_B1_PO <7: 0>, LID_OD_B1_PO <7: 0 by sensing programmed data of a plurality of memory cell blocks. >, LID_EV_BO_P1 <7: 0>, LID_OD_BO_P1 <7: 0>, LID_EV_B1_P1 <7: 0>, and LID_OD_B1_P1 <7: 0> are transmitted to the sense amplifier group 520. The sense amplifier group 520 may output data LID_EV_BO_PO <7: 0>, LID_OD_BO_PO <7: 0>, LID_EV_B1_PO <7: 0>, LID_OD_B1_PO <7: 0>, and LID_EV_BO_P1 <7 from the page buffer group 510. : Sensing the data sensed by sensing: 0>, LID_OD_BO_P1 <7: 0>, LID_EV_B1_P1 <7: 0>, LID_OD_B1_P1 <7: 0>). GDL_EV_BO_PO <7: 0>, GDL_OD_BO_PO <7: 0> 1, GDL_EV_ <7: 0>, GDL_OD_B1_PO <7: 0>, GDL_EV_BO_P1 <7: 0>, GDL_OD_BO_P1 <7: 0>, GDL_EV_B1_P1 <7: 0>, GDL_OD_B1_P1 <7: 0>) Output The plane mux unit 530 may transmit the global data GDL_EV_BO_PO <7: 0>, GDL_OD_BO_PO <7: 0>, GDL_EV_B1_PO <7: 0>, GDL_OD_B1_PO <7: 0>, and GDL_EV_BO_P1 <7 in response to the plane selection signal SEL_PLANE. : 0>, GDL_OD_BO_P1 <7: 0>, GDL_EV_B1_P1 <7: 0>, GDL_OD_B1_P1 <7: 0>, by grouping the plane data by bank data (GDL_EV_B0 <7: 0>, GDL_OD_B0 <7: 0>, GDL_EV_B1 : 0>, GDL_OD_B1 <7: 0>). The bank mux unit 540 outputs bank data GDL_EV_B0 <7: 0>, GDL_OD_B0 <7: 0>, GDL_EV_B1 <7: 0>, and GDL_OD_B1 <7: 0> output from the plane mux unit 530 for each bank. Grouping is performed to output even data (IOOUT_EV <7: 0>) and odd output data (IOOUT_OD <7: 0>). The even-odd mux unit 550 groups the even output data (IOOUT_EV <7: 0>) and the odd output data (IOOUT_OD <7: 0>) output from the bank mux unit 540, and then the address signal AX < 0>) to output the first output signal DOR <7: 0> and the second output signal DOF <7: 0>.

The IO pad 560 receives the first output signal DOR <7: 0> and the second output signal DOF <7: 0> received from the even-odd mux unit 550 in response to the clock signal CLK. ) More specifically, the first output signal DOR <7: 0> is output to the outside in synchronization with the rising edge of the clock signal CLK, and the second output signal DOF is synchronized with the falling edge of the clock signal CLK. Output <7: 0>) to the outside. This enables synchronous mode in data output operation.

110: IO pad 120: Latch
130: plain musbu 140: sense amplifier group
150: page buffer group

Claims (9)

An IO pad configured to receive external input data and synchronize the external input data to the rising edge and the falling edge of the data strobe signal, respectively, and output the first input data and the second input data;
A latch unit for dividing and outputting the first input data and the second input data into a plurality of bank data according to a bank selection signal; And
And a plane mux unit configured to divide and output the plurality of bank data into a plurality of plane data according to a plane selection signal.
The method of claim 1,
And a sense amplifier group for receiving the plurality of plane data and transmitting the plurality of plane data to a page buffer group.
Following claim 1
And the IO pad is configured to input the external data in a synchronous mode in synchronization with the data strobe signal.
The method of claim 1,
The latch unit divides the first input data and the second input data to correspond to each bank in response to a strobe clock and the bank selection signal, and outputs the output data to a plurality of global data lines. Nonvolatile memory device consisting of two lines per bank.
The method of claim 1,
And an IO pad and the latch unit connected to at least two data lines.
A page buffer group for sensing and outputting data stored in a plurality of memory cell blocks;
A mux circuit for grouping a plurality of data output from the page buffer group and outputting the first and second output data; And
And an IO pad configured to receive the first and second output data and synchronize the first and second output data to the rising and falling edges of the clock signal to output the external output data.
The method according to claim 6,
The mux circuit
A sense amplifier group for sensing data output from the page buffer group and outputting the data as global data;
A plane mux unit for grouping the global data into planes in response to a plane selection signal and outputting the global data as bank data;
A bank mux for grouping the bank data into banks in response to a bank selection signal and outputting the bank data as even data and odd data; And
And an even-odd mux for outputting the even data and the odd data as the first output data and the second output data in response to an address signal.
Following the claim 6,
And the IO pad is synchronized with the clock signal to output the first output data and the second output data in a synchronous mode.
The method according to claim 6,
And the IO pad and the MUX circuit are connected to at least two data lines.





KR1020100066525A 2010-07-09 2010-07-09 Non volatile memory device KR20120005847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100066525A KR20120005847A (en) 2010-07-09 2010-07-09 Non volatile memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100066525A KR20120005847A (en) 2010-07-09 2010-07-09 Non volatile memory device

Publications (1)

Publication Number Publication Date
KR20120005847A true KR20120005847A (en) 2012-01-17

Family

ID=45611803

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100066525A KR20120005847A (en) 2010-07-09 2010-07-09 Non volatile memory device

Country Status (1)

Country Link
KR (1) KR20120005847A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10007603B2 (en) 2014-06-25 2018-06-26 Samsung Electronics Co., Ltd. Nonvolatile memory device and operating method thereof for performing dumping operations between cache latch and data latch of page buffers during input/output operations

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10007603B2 (en) 2014-06-25 2018-06-26 Samsung Electronics Co., Ltd. Nonvolatile memory device and operating method thereof for performing dumping operations between cache latch and data latch of page buffers during input/output operations

Similar Documents

Publication Publication Date Title
KR100784865B1 (en) Nand flash memory device and memory system including the same
KR101145784B1 (en) Semiconductor memory device and memory system having the same
KR102167598B1 (en) Semiconductor device
US7542371B2 (en) Memory controller and memory system
CN105719685B (en) Semiconductor device and method of driving the same
US7827431B2 (en) Memory card having memory device and host apparatus accessing memory card
KR20200083641A (en) Apparatus and method comprising memory instructions for semiconductor memory
TW201108244A (en) Memory devices and systems including write leveling operations and methods of performing write leveling operations in memory devices and systems
US6909643B2 (en) Semiconductor memory device having advanced data strobe circuit
CN109584944B (en) Input/output circuit supporting multiple input shift register function and memory device
JP2007048281A (en) Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory
US9318177B2 (en) Semiconductor devices and semiconductor systems including the same
KR101138832B1 (en) Semiconductor memory device and method operating the same
CN100576140C (en) Produce the circuit and the method for the clock signal of digital signal processor and storer
US20180225236A1 (en) Memory controller, storage device, information processing system, and memory control method
KR20110056124A (en) Memory controller, memory device and memory system capable of reducing a power consumption
CN104778965A (en) Semiconductor devices and semiconductor systems including the same
KR101895519B1 (en) Semiconductor memory device
KR20120005847A (en) Non volatile memory device
CN108962305B (en) Data alignment circuit and semiconductor device including the same
JP2015103262A (en) Semiconductor device
KR20130119170A (en) Pipe register circuit and semiconductor memory apparatus comprising the same
KR100878125B1 (en) Synchronized double data rate flash memory apparatus and memory interface apparatus
KR20160005994A (en) Semiconductor Memory Apparatus
KR102573131B1 (en) Memory device for high speed data transfer

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination