KR20120005349A - Data strobe signal input circuit - Google Patents

Data strobe signal input circuit Download PDF

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Publication number
KR20120005349A
KR20120005349A KR1020100066049A KR20100066049A KR20120005349A KR 20120005349 A KR20120005349 A KR 20120005349A KR 1020100066049 A KR1020100066049 A KR 1020100066049A KR 20100066049 A KR20100066049 A KR 20100066049A KR 20120005349 A KR20120005349 A KR 20120005349A
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KR
South Korea
Prior art keywords
signal
data strobe
buffering
buffer enable
synchronization
Prior art date
Application number
KR1020100066049A
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Korean (ko)
Inventor
김정현
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100066049A priority Critical patent/KR20120005349A/en
Publication of KR20120005349A publication Critical patent/KR20120005349A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

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Abstract

PURPOSE: A circuit for inputting a data strobe signal is provided to steadily receive a data strobe signal even if the input time point of a data strobe signal is changed. CONSTITUTION: A buffering signal generating unit(11) buffers a data strobe signal and outputs the data strobe into a buffering signal. The buffering signal generating unit enables for the enable period of a buffer enable signal. A buffer enable signal generating part(12) generates the buffer enable signal. The buffer enable signal enables according to an internal write pulse signal. The buffer enable signal disables after a burst length period.

Description

Data strobe signal input circuit {DATA STROBE SIGNAL INPUT CIRCUIT}

The present invention relates to a data strobe signal input circuit.

In the semiconductor memory device, efforts have been made to improve the operation speed while increasing the degree of integration. In an effort to improve the operation speed, a so-called double date rate (DDR) synchronous memory device that inputs and outputs 2 bits of data to 1 tCK of a clock has been proposed. In addition, the semiconductor memory device transmits and receives a data strobe signal to and from the memory controller in order to accurately align the data input / output points in the high speed operation.

The data strobe signal goes through the postamble and returns to the high impedance state. However, there is a case where a ringing phenomenon occurs due to noise before the data strobe signal returns to high impedance. As such, when a ringing phenomenon occurs after the postamble, an error occurs in the process of latching data with the data strobe signal.

Therefore, recent semiconductor memory devices have circuits for preventing errors due to ringing of the data strobe signal.

1 is a block diagram showing a data strobe signal input circuit according to the prior art.

As illustrated in FIG. 1, the data strobe signal input circuit shifts the internal light pulse signal WTINT according to the internal clock ICLK to generate the first to fourth shifting signals WT1R to WT4R. (1), a buffer enable signal generation unit 2 for outputting any one of the internal light pulse signal WTINT and the first to fourth shifting signals WT1R to WT4R as a buffer enable signal DISDSP; A buffer unit 3 is configured to buffer the data strobe signal DQS and output the data strobe rising signal DQSR and the data strobe polling signal DQSF, and to disable the response in response to the buffer enable signal DISDSP.

Referring to the operation of the data strobe signal input circuit as shown in FIG. 2 is a timing diagram illustrating a case where a data strobe signal is input at a normal time point (tDQSSnor).

As illustrated in FIG. 2, when the light command WT is input at a time t1, the internal light pulse signal WTINT is enabled at a high level at time t2. When the internal light pulse signal WTINT is generated, the shifting unit 1 first to fourth shifting signals WT1R to WT4R which sequentially enable the internal light pulse signal WTINT in synchronization with the internal clock ICLK. ) When the first to fourth shifting signals WT1R to WT4R are generated, the buffer enable signal generation unit 2 disables the fourth shifting signal WT4R from the enable point of the internal light pulse signal WTINT. A buffer enable signal DISDSP is generated that enables up to a point in time. When the buffer enable signal DISDSP is generated, the buffer unit 3 buffers the data strobe signal DQS during the period in which the buffer enable signal DISDSP is enabled, thereby causing the data strobe rising signal DQSR and the data strobe polling signal. Create (DQSF).

Since the dummy pulse DP due to the ringing phenomenon is generated in the data strobe signal DQS after the time t3 at which the buffer enable signal DISDSP is disabled, the dummy pulse DP is connected to the data strobe rising signal DQSR. It does not affect the generation of the data strobe polling signal (DQSF). Accordingly, the semiconductor memory device may stably latch data input together with the data strobe signal DQS according to the data strobe rising signal DQSR and the data strobe polling signal DQSF.

3 is a timing diagram illustrating a case where a data strobe signal is input at a early time (tDQSSmin).

As shown in FIG. 3, when the light command WT is input at a time t1, the internal light pulse signal WTINT is enabled at a high level at time t2. When the internal light pulse signal WTINT is generated, the shifting unit 1 first to fourth shifting signals WT1R to WT4R which sequentially enable the internal light pulse signal WTINT in synchronization with the internal clock ICLK. ) When the first to fourth shifting signals WT1R to WT4R are generated, the buffer enable signal generation unit 2 disables the fourth shifting signal WT4R from the enable point of the internal light pulse signal WTINT. A buffer enable signal DISDSP is generated that enables up to a point in time. When the buffer enable signal DISDSP is generated, the buffer unit 3 buffers the data strobe signal DQS during the period in which the buffer enable signal DISDSP is enabled, thereby causing the data strobe rising signal DQSR and the data strobe polling signal. Create (DQSF).

However, when the data strobe signal DQS is input as early as shown in FIG. 3, the dummy pulse DP due to the ringing occurs before the time point t4 at which the buffer enable signal DISDSP is disabled. Is generated). That is, the dummy pulse DP exists in the enable period of the buffer enable signal DISDSP, which affects the generation of the data strobe rising signal DQSR and the data strobe polling signal DQSF. Accordingly, the dummy pulse DP1 is also generated in the data strobe rising signal DQSR and the data strobe polling signal DQSF, so that data input together with the data strobe signal DQS cannot be stably latched.

The present invention discloses a data strobe signal input circuit that can stably receive even when the input time point of the data strobe signal is varied.

To this end, the present invention buffers a data strobe signal and outputs it as a buffering signal. Provided is a data strobe signal input circuit including a buffer enable signal generation unit for generating a buffer enable signal for disabling after a set bus-transition period.

1 is a block diagram showing a data strobe signal input circuit according to the prior art.
2 and 3 are timing diagrams illustrating an operation of a data strobe signal input circuit as shown in FIG. 1.
4 is a block diagram illustrating a data strobe signal input circuit according to an exemplary embodiment of the present invention.
FIG. 5 is a circuit diagram illustrating a buffering signal generator shown in FIG. 4.
FIG. 6 is a circuit diagram illustrating a section signal generator shown in FIG. 4.
FIG. 7 is a circuit diagram illustrating a buffer enable signal output unit shown in FIG. 4.
FIG. 8 is a circuit diagram illustrating a phase divider shown in FIG. 4.
9 to 11 are timing diagrams illustrating operations of a data strobe signal input circuit as shown in FIG. 4.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

4 is a block diagram illustrating a data strobe signal input circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 4, a buffering signal generator 11, a buffer enable signal generator 12, and a phase divider 13 are configured.

As shown in FIG. 5, the buffering signal generator 11 includes a buffer 111 and a buffering signal output 112. The buffer unit 111 may include a first differential input buffer 1111 that receives the data strobe signal DQS and a reference voltage VREF, and a second differential that receives the data strobe signal DQS and the inverted data strobe signal DQSB. A first NAND gate ND1 is configured to NAND the outputs of the input buffer 1112 and the first and second differential input buffers 1111 and 1112 to output the prebuffered signal DQSBUF. The inversion data strobe signal DQSB is a signal in which the phase of the data strobe signal DQS is inverted. The buffer 111 buffers the data strobe signal DQS and outputs the pre-buffering signal DQSBUF. The buffering signal output unit 112 includes a first AND gate which ANDs the pre-buffering signal DQSBUF and the buffer enable signal DQSDSP to output the buffering signal DQSIR.

The buffering signal generator 11 having the above configuration buffers the data strobe signal DQS and outputs the buffered signal DQSIR. At this time, the buffering signal generator 11 enables the enable period of the buffer enable signal DQSDSP.

The buffer enable signal generator 12 includes an interval signal generator 121 and a buffer enable signal output unit 122.

As shown in FIG. 6, the interval signal generation unit 121 includes an edge detector 1211 and an interval signal output unit 1211. The edge detector 1211 NORs the outputs of the inversion delay circuit 1213 and the buffering signal DQSIR and the inversion delay circuit 1213 that inverts the buffering signal DQSIR and outputs them as the synchronization signal DQSP. The first NOR gate NOR1 is formed. The edge detector 1211 having such a configuration detects the polling time of the buffering signal DQSIR and outputs it as a synchronization signal DQSP. The interval signal output unit 1212 shifts the pull-up voltage VDD according to the synchronization signal DQSP, and outputs the first shifter 1214 and the first signal according to the synchronization signal DQSP. The second shift signal 12T shifts the shifting signal SH1 and outputs the first shift signal WT2R and the second shift signal SH2 by shifting the first shift signal WT2R according to the synchronization signal DQSP. ) And a fourth shifter 1217 for shifting the second shifting signal SH2 and outputting the second shift signal WT4R according to the synchronization signal DQSP. The first and second shifters 1214 and 1215 are reset in response to the internal light pulse signal WTINT, and the third and fourth shifters 1216 and 1217 are reset in response to the reset signal RSTS. Here, the first interval signal WT2R is enabled in response to the internal light pulse signal WTINT and disabled in response to the second rising time of the synchronization signal DQSP. The second interval signal WT4R is enabled in response to the internal light pulse signal WTINT and is disabled in response to the fourth rising time of the synchronization signal DQSP. In addition, the interval signal output unit 1212 further includes a reset signal generator 1218 that receives the internal light pulse signal WTINT and the bus trace control signal BL4 and outputs the reset signal. The section signal output unit 1212 having the above configuration sequentially shifts the pull-up voltage VDD according to the synchronization signal DQSP to generate the first and second section signals WT2R and WT4R.

The section signal generation unit 121 having the above configuration generates the first and second section signals WT2R and WT4R having different pulse widths in synchronization with the buffering signal DQSIR.

As shown in FIG. 7, the buffer enable signal output unit 122 outputs the first interval signal WT2R and the bus trace control signal BL4 as a pre-buffer enable signal PREDISDSP. The AND gate 131 and the pre-buffer enable signal PREDISDSP and the second interval signal WT4R are knocked out and output as a buffer enable signal DISDSP. The buffer enable signal output unit 122 outputs the first section signal WT2R as a buffer enable signal DISDSP when the bus trace control signal BL4 is at a high level, and the bus trace control signal BL4 is at a low level. In this case, the second interval signal WT4R is output as a buffer enable signal DISDSP. The buffer enable signal output unit 122 configured as described above outputs any one of the first and second interval signals WT2R and WT4R as the buffer enable signal DISDSP according to the set bus trend.

As illustrated in FIG. 8, the phase dividing unit 13 inverts the buffer 131 and the buffering signal DQSIR, which buffer the buffering signal DQSIR and output the data strobe rising signal DQSR, to poll the data strobe. The inverter IN1 outputs the signal DQSF. The phase divider 13 divides the phase of the buffering signal DQSIR to generate a data strobe rising signal DQSR and a data strobe polling signal DQSF.

The operation of the data strobe signal input circuit having such a configuration will be described below.

FIG. 9 is a timing diagram illustrating the operation of the data strobe signal input circuit as shown in FIG. 4, in which the input time point of the data strobe signal is normal tDQSSnor.

As shown in FIG. 9, when the light command WT is input at the time t1 of the external clock ECLK, the internal light pulse signal WTINT is enabled at a high level at the time t2 of the internal clock ICLK. Here, the internal clock ICLK is generated by buffering the external clock ECLK.

Subsequently, when the data strobe signal DQS is input at the time t3, the buffering signal generator 11 generates the buffering signal DQSIR. That is, the buffering signal generation unit 11 transitions the buffering signal DQSIR whenever the data strobe signal DQS transitions.

Subsequently, when the buffering signal DQSIR is generated, the edge detector 1211 detects a polling time point of the buffering signal DQSIR and outputs it as a synchronization signal DQSP. The section signal output unit 1211 generates the first and second section signals WT2R and WT4R described above in synchronization with the synchronization signal DQSP. Here, when the internal light pulse signal WTINT is enabled at a high level, the first interval signal WT2R is enabled at a low level, and then is disabled at a high level in response to the second rising time of the synchronization signal DQSP. When the internal light pulse signal WTINT is enabled at a high level, the second interval signal WT4R is enabled at a low level, and then is disabled at a high level in response to the fourth rising time of the synchronization signal DQSP. do.

Subsequently, the buffer enable signal output unit 122 outputs one of the first and second interval signals WT2R and WT4R as the buffer enable signal DISDSP according to the level of the bus-trans control signal BL4. do. For example, if the set bus trend is 4, the bus trend control signal BL4 becomes high level and the first interval signal WT2R is output as the buffer enable signal DISDSP. If the set bus trend is 8, the bus trend control is performed. The signal BL4 becomes low level and the second interval signal WT4R is output as the buffer enable signal DISDSP. In the following, it is exemplified that the bus trance is eight.

The buffer enable signal DISDSP generated as described above is enabled at a high level in response to the rising time of the internal light pulse signal WTINT, and is disabled at a low level in response to the fourth rising time of the synchronization signal DQSP. do. Accordingly, the buffering signal generator 11 buffers the data strobe signal DQS during the enable period of the buffer enable signal DISDSP and outputs the buffered signal DQSIR. In this case, the buffering signal DQSIR does not buffer the dummy pulse DP of the data strobe signal DQS. This is because the buffer enable signal DISDSP is disabled before the dummy pulse DP is generated.

Accordingly, since the signal according to the dummy pulse DP is not generated in the buffering signal DQSIR, the data strobe rising signal DQSR and the data strobe polling signal DQSF are stably generated, thereby stably latching the data. can do.

In general, the transition time point of the data strobe signal DQS changes according to the set bus trend. For example, if the bus trance is 4, the data strobe signal DQS is made four times. If the bus trance is 8, the data strobe signal DQS is made eight times. Therefore, when the disable point of the buffer enable signal DISDSP is set according to the bus trend as in the present embodiment, the dummy pulse DP of the data strobe signal DQS due to the ringing phenomenon is not buffered. That is, since the buffering signal DQSIR can be generated stably, the data input together with the data strobe signal DQS can be stably latched.

If the data strobe signal DQS is input to the fast time point tDQSSmin as shown in FIG. 10, the disable time point of the first and second section signals WT2R and WT4R detects a polling time point of the buffering signal DQSIR. And one of the first and second section signals WT2R and WT4R are output as the buffer enable signal DISDSP according to the set bus trend, and thus the buffering signal DQSIR. ) Does not include the dummy pulse DP of the data strobe signal DQS.

11, the dummy pulse DP of the data strobe signal DQS is not included in the buffering signal DQSIR even when the data strobe signal DQS is input at the slow time tDQSSmax as shown in FIG.

11: buffering signal generator
12: buffer enable signal generator
13: phase divider

Claims (13)

A buffering signal generator for buffering the data strobe signal and outputting the buffered signal as an enable period of the buffer enable signal; And
And a buffer enable signal generator configured to enable a buffer enable signal according to an internal light pulse signal and to disable a buffer enable signal after a bus-transition period set in synchronization with the buffering signal.
The method of claim 1, wherein the buffering signal generation unit
A buffer unit for buffering the data strobe signal and outputting it as a pre-buffering signal; And
And a buffering signal output unit configured to output the pre-buffering signal as the buffering signal in response to the buffer enable signal.
3. The data strobe signal input circuit of claim 2, wherein the buffering signal output unit is a first logic circuit that draws the buffer enable signal and the prebuffer signal and outputs the buffered signal.
The method of claim 1, wherein the buffer enable signal generation unit
A section signal generation unit configured to enable first and second section signals according to the internal light pulse signal, wherein the first and second section signals are disabled in synchronization with the buffering signal; And
And a buffer enable signal output unit configured to output one of the first and second interval signals as the buffer enable signal according to the set bus trend.
The method of claim 4, wherein the section signal generation unit
An edge detector which detects a polling time of the buffering signal and outputs the synchronization signal; And
And a section signal output unit configured to sequentially shift the pull-up voltage according to the synchronization signal to generate the first and second section signals.
The method of claim 5, wherein the section signal output unit
A first shifter shifting the pull-up voltage according to the synchronization signal to output a first shifting signal;
A second shifter for shifting the first shifting signal according to the synchronization signal and outputting the first shifting signal;
A third shifter configured to shift the first interval signal according to the synchronization signal and output a second shifting signal; And
And a fourth shifter for shifting the second shifting signal according to the synchronization signal and outputting the second shifting signal as the second interval signal.
The data strobe signal input circuit of claim 6, wherein the section signal output unit further comprises a reset signal generation unit configured to output an internal light pulse signal and a bus trace control signal as a reset signal.
The data strobe signal input circuit of claim 6, wherein the first and second shifters are reset in response to the internal light pulse signal, and the third and fourth shifters are reset in response to the reset signal.
5. The data strobe signal input circuit of claim 4, wherein the first interval signal is enabled in response to an internal light pulse signal and disabled in response to a second rising time of the synchronization signal.
5. The data strobe signal input circuit of claim 4, wherein the second interval signal is enabled in response to an internal light pulse signal and disabled in response to a fourth rising time of the synchronization signal.
The method of claim 4, wherein the buffer enable signal output unit
A second logic circuit for drawing the first interval signal and the bus-transmission control signal and outputting them as pre-buffer enable signals; And
And a third logic circuit for knocking out the pre-buffer enable signal and the second interval signal and outputting the buffered enable signal.
The method of claim 4, wherein the buffer enable signal output unit outputs the first interval signal as the buffer enable signal when the bus trace control signal is at a high level, and the second interval signal when the bus trace control signal is at a low level. And a data strobe signal input circuit outputting the signal as the buffer enable signal.
The data strobe signal input circuit of claim 1, further comprising a phase division unit configured to divide a phase of the buffering signal to generate a data strobe rising signal and a data strobe polling signal.
KR1020100066049A 2010-07-08 2010-07-08 Data strobe signal input circuit KR20120005349A (en)

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KR1020100066049A KR20120005349A (en) 2010-07-08 2010-07-08 Data strobe signal input circuit

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