KR20120004697A - Appratus for recovering clock and data with a wide range of frequency for low frequency circuit - Google Patents

Abstract

PURPOSE: An apparatus for recovering a clock and data is provided to reduce the burdens of a PD(Phase Detector) structure and a PD design by maintaining a clock frequency through a loop including the PD. CONSTITUTION: A PLL(Phase locked loop) input circuit unit(110) matches a phase and a frequency between an input signal and a first feedback signal by receiving the first feedback signal of a PPL and the input signal. A band selection circuit unit(120) selects a specific VCO(Voltage Controlled Oscillator) among VCOs(121). A divider(130) controls a frequency of a specific VCO output with a preset division ratio. An interpolator(140) divides the output of the divider into four phases. A data recovery input circuit unit(150) includes a half-rate RD(151), a charge pump(152), and a loop filter(113). A serializer(160) recoveries data by serially rising sampling data.

Description

APPRATUS FOR RECOVERING CLOCK AND DATA WITH A WIDE RANGE OF FREQUENCY FOR LOW FREQUENCY CIRCUIT}

The present invention relates to a clock and data recovery apparatus supporting a wide frequency range for low frequencies. More specifically, the present invention adjusts phase and frequency between the input signal and the output signal of the frequency divider while the input signal corresponds to a training sequence section. Data for switching the signal to flow along the PLL loop, and while performing the data sampling of the input signal while maintaining the clock frequency of the VCO while the input signal corresponds to the data (significant information, not the training sequence) reception interval. The present invention relates to a clock and data recovery apparatus supporting a wide frequency range for low frequencies, characterized by switching a signal to flow along a recovery loop.

In the art of the present invention, research has been actively conducted on a phase locked loop such as a phase-locked loop (PLL) for synchronizing a phase of a received signal.

The PLL is a frequency negative feedback circuit configured to keep the frequency of the output signal constant at all times. The PLL detects a phase difference between the input signal and the output signal and generates a VCO (Voltage Controlled Oscillator). By controlling, it is possible to transmit a fixed frequency signal.

It plays a huge role in the transmission and communication of digital signals by fixing the frequency by continuously cycling until the transmitted signal matches the reference frequency.

In particular, the PLL circuit allows the signal to remain at a particular phase. In other words, the correct fixed point is forcibly held so that the phase of the periodic signal is not shaken. Especially in the RF system, it is mainly used to prevent the shaking of the frequency which is used as the frequency source, because the concept of integrating the frequency is the concept of fixed phase and fixed frequency.

This PLL circuit can also be used for clock and data recoverers that support a wide frequency range for low frequencies. In this case, the circuit must be configured in accordance with the pattern of the input signal to restore the clock and data, so that efficient recovery with low digital processing burden can be achieved. The circuit must be configured to cover a wide frequency range. There has been an issue about whether or not it can be supported, and research is being conducted to improve it.

It is an object of the present invention to solve all the problems described above.

In addition, another object of the present invention is to provide a clock and data recovery apparatus having a simple structure with little burden for digital processing in a frequency detector (FD) and a phase detector (PD).

In addition, another object of the present invention is to provide a clock and data recovery apparatus having a very low burden on the structure and design of a PD operating during data recovery.

Representative configurations of the present invention for achieving the above object of the present invention are as follows.

According to an aspect of the present invention, in a clock and data recovery apparatus supporting a wide frequency range for low frequency, while an input signal corresponds to a training sequence (input form in which 1 and 0 are periodically repeated), Receives the first feedback signal of the input signal and the PLL loop, adjusts the phase and frequency between the input signal and the first feedback signal, and processes these signals to rotate the PLL loop to a voltage controlled oscillator (VCO). A PLL input circuit unit for inputting a band selection circuit unit including at least one of the VCOs and selecting a specific VCO among the at least one VCOs with reference to a frequency range of a clock that the VCOs can output; And receiving the output of the specific VCO and adjusting the frequency of the output of the specific VCO to a predetermined division ratio to configure the PLL circuit. A signal is switched to flow along the PLL loop configured to include a divider for providing the first feedback signal to a unit, and the input signal is input to a data (significant information rather than the training sequence) section. While applicable, receive a second feedback signal of the input signal and a data recovery loop to adjust the phase between the input signal and the second feedback signal and allow these signals to run through the data recovery loop. A data recovery input circuit unit for processing the input to the specific VCO, sampling the input signal with reference to the second feedback signal, and receiving the output of the data recovery input circuit unit and covering the specific VCO; A VCO unit for outputting a clock according to the divider, and receiving an output of the VCO unit. And a divider for adjusting the frequency of the output of the VCO unit to a predetermined division ratio, and receiving the output of the divider into four phases and outputting a signal of a specific phase among them to the data recovery input circuit unit. An apparatus is provided for switching a signal to flow along the data recovery loop including an interpolation unit for transmitting a feedback signal.

According to the present invention, since there is little burden on digital processing in a frequency detector (FD) and a phase detector (PD), it is possible to provide a clock and data recovery apparatus that can be implemented with a simple structure.

In addition, the present invention can provide a clock and data recovery device having a very low burden on the structure and design of the PD since the loop including the PD needs only to maintain the clock frequency of the VCO during data recovery.

In addition, the present invention can provide a clock and data recovery apparatus having a low additional encoding burden in addition to a training sequence.

1 is a view showing the overall configuration of a clock and data recovery apparatus supporting a low frequency wide frequency range according to an embodiment of the present invention.
FIG. 2 illustrates in detail an example of circuit operation while an input signal corresponds to a training sequence section in a clock and data recovery apparatus supporting a low frequency wide frequency range according to an embodiment of the present invention. Drawing.
3 illustrates an example of a circuit operation while an input signal corresponds to a data (significant information rather than a training sequence) period in a clock and data recovery apparatus supporting a wide frequency range for low frequency according to an embodiment of the present invention. It is a figure which shows in detail.
4 is a diagram illustrating in detail an example of a timing block diagram of a clock and data recovery apparatus supporting a wide frequency range for low frequencies according to an embodiment of the present invention.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. In the drawings, like reference numerals refer to the same or similar functions throughout the several aspects, and length, area, thickness, and the like may be exaggerated for convenience.

DETAILED DESCRIPTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

[Preferred Embodiments of the Invention]

Configuration of the entire system

1 is a view showing the overall configuration of a clock and data recovery apparatus supporting a low frequency wide frequency range according to an embodiment of the present invention.

Referring to FIG. 1, a clock and data recovery apparatus according to an exemplary embodiment of the present invention may include a PLL input circuit unit 110, a band selection circuit unit 120, a divider 130, and an interpolator ( 140, the data recovery input circuit unit 150, and the serializer 160 may be included.

First, when the input signal Din corresponds to a training sequence (input form in which 1 and 0 are periodically repeated), the PLL input circuit unit 110 according to an embodiment of the present invention is shown in FIG. 2. Similarly, the first feedback signal (ie, the divider 130) of the input signal and the PLL loop (that is, the loop composed of the PLL input circuit unit 110, the band selection circuit unit 120, and the divider 130). Output signal) to adjust the phase and frequency between the input signal and the first feedback signal, and through the PFD 111, the charge pump 112, and the loop filter 113 which will be described later, the band selection circuit unit ( And a function of inputting the voltage controlled oscillator (VCO) 121 included in the 120). A more detailed description thereof will be described later with reference to FIG. 2.

Here, the band selection circuit unit 120 according to an embodiment of the present invention includes at least one VCO 121, and with reference to the frequency range of the clock that the VCO 121 can output. A function of selecting a specific VCO among the at least one VCO 121 may be performed. A more detailed description thereof will be described later with reference to FIG. 2.

In addition, the divider 130 according to an embodiment of the present invention receives the output of a specific VCO, adjusts the frequency of the output of the specific VCO to a predetermined division ratio, and transmits the first feedback signal to the PLL component circuit unit 110. It can serve as a function. A more detailed description thereof will be described later with reference to FIG. 2.

Next, while the input signal Din corresponds to a data (significant information other than the training sequence) receiving section, the data recovery input circuit unit 150 according to an embodiment of the present invention may input the input as shown in FIG. 3. Second feedback signal of the signal and data recovery loop (that is, the loop consisting of the data recovery input circuit unit 150, the VCO unit 121, the divider 130, and the interpolation unit 140) (that is, the interpolation unit 140). Output signal) and adjust the phase between the input signal and the second feedback signal, and these signals pass through the half-rate PD 151, the charge pump 152, and the loop filter 113 to the VCO unit 121. (Ie, the specific VCO determined when the input signal Din corresponds to the training sequence section). In this case, the data recovery input circuit unit 150 according to an embodiment of the present invention may perform a function of sampling the input signal with reference to the second feedback signal. A detailed description thereof will be described later with reference to FIG. 3.

Here, the VCO unit 121 according to an embodiment of the present invention receives the output of the data recovery input circuit unit 150 and outputs a clock according to the frequency covered by the specific VCO to the divider 130. can do. A detailed description thereof will be described later with reference to FIG. 3.

In addition, the divider 130 receives the output of the VCO unit 121 and adjusts the frequency of the output of the VCO unit 121 to a predetermined division ratio. A detailed description thereof will be described later with reference to FIG. 3.

In addition, the interpolation unit 140 receives the output of the divider 130 and divides the signal into four phases, and outputs a signal of a specific phase among them to the data recovery input circuit unit 150 to the second feedback signal. It can perform the function of transmitting. A detailed description thereof will be described later with reference to FIG. 3.

FIG. 2 illustrates in detail an example of circuit operation while an input signal corresponds to a training sequence section in a clock and data recovery apparatus supporting a low frequency wide frequency range according to an embodiment of the present invention. Drawing.

2, the PLL input circuit unit 110 may include a PFD 111, a charge pump 112, and a loop filter 113.

In detail, the PFD 111 is a component for detecting not only a phase difference but also a frequency difference. The PFD 111 outputs the input signal and the output of the frequency divider 130 while the input signal Din corresponds to a training sequence section. The signal may be received as a signal to detect a phase difference and a frequency difference between the input signal and the first feedback signal.

In addition, the charge pump 112 may perform a function of pushing and pulling an amount of charge determined by referring to the output of the PFD 111, and the loop filter 113 may be formed at the charge pump 112. And a capacitor for accumulating or releasing the pushing and pulling charges, and providing an output to the band selection circuitry 120. Here, the loop filter 113 may be implemented as a low pass filter (LPF).

Also, the band selection circuit unit 120 receives a plurality of VCOs 121 for receiving the output of the loop filter 113 as an input voltage and outputting a frequency proportional thereto while the input signal Din corresponds to the training sequence. ) May be included. In addition, the band selection circuit unit 120 may include a finite state machine (FSM) 124, which is output by passing the output of the loop filter 113 through predetermined comparators 122 and 123. By receiving a comparator output signal, a function of outputting a VCO selection signal for selecting the specific VCO among the plurality of VCOs 121 may be performed.

For example, suppose you have three VCOs, assuming that VCO1 covers a frequency range of 10 to 20 Hz, VCO2 covers a frequency range of 20 Hz to 30 Hz, and VCO3 covers 30 to 40 Hz. Make sure your VCO2 is selected. For this purpose, for example, it is assumed that the outputs of the comparators 122 and 123 output 1 when higher than the reference and 0 when lower when comparing the value near the reference VDD and the value near the GND. In this case, if VCO1 is initially selected, the PLL loop will operate during the training sequence and the VCO control voltage will continue to rise to produce an output frequency of 28 Hz. When the value is almost equal to VDD, the comparator outputs 1 and the FSM 124 selects VCO2.

On the other hand, the divider 130 receives the output of the FSM 124 to adjust the predetermined division ratio, and adjusts the frequency of the output of the specific VCO according to the adjusted division ratio to the PFD 111 to the first Function to provide as a feedback signal can be performed.

In detail, the divider 130 may be a programmable divider and may vary the dividing ratio according to the control bit. For example, if the control bit is 0, it will be divided by 1, by 1, 2, etc.

In addition, the divider 130 may also perform a function for generating a low frequency that the VCO does not cover. For example, if the correct frequency is 8 Hz to sample data, the frequency range 130 may not satisfy the frequency range. In this case, the VCO control voltage will be close to GND to lower the output frequency and the output of comparator 123, which is referenced to a value near GND, will be zero. If VCO1 is selected and the output of the comparator 123 with reference to the value near GND is 0, the FSM 124 sets the control bit of the divider 130 to 1 according to the VCO1 selection state and the state where the comparator output value is 0. Change the divider ratio to 2. In this case, even though VCO1 outputs 16Hz, the output passed through the divider becomes 8Hz, in which case the PLL loop can be locked.

3 illustrates an example of a circuit operation while an input signal corresponds to a data (significant information rather than a training sequence) period in a clock and data recovery apparatus supporting a wide frequency range for low frequency according to an embodiment of the present invention. It is a figure which shows in detail.

First, the data recovery input circuit unit 150 may include a half-rate PD 151, a charge pump 152, and a loop filter 113.

Specifically, the half-rate PD 151 receives the second feedback signal that is an output from the 4x1 MUX 143 of the input signal and the interpolator 141 while the input signal Din corresponds to the data reception interval. And a function of sampling the input signal with reference to the second feedback signal. Here, since a clock having a frequency of 1/2 of the data rate is used, half-rate PD is used.

In addition, the charge pump 152 may perform a function of pushing and pulling a charge by an amount determined by referring to the output of the Half-Rate PD 151, and the loop filter 113 is illustrated in FIG. 2. It can be implemented as the same filter as the loop filter 113 present on the path of the PLL loop in Equation 2, and includes a capacitor for accumulating or releasing charge pushed by the charge pump 152 and output to the VCO unit 121 Can provide a function.

On the other hand, the VCO unit 121 may perform a function of receiving the output of the loop filter 113 and providing a signal to the divider 130, the VCO unit 121 on the PLL loop with reference to FIG. It may operate based on the particular VCO determined.

The interpolator 140 may include an interpolator 141 and a 4x1 MUX 143. In some cases, the buffer 142 is located between the interpolator 141 and the 4x1 MUX 143. Can be digitized.

The interpolator 141 may receive an output of the divider 130 and divide the output into four phases.

In addition, the buffer 142 may perform a function of digitizing each signal divided into four phases output from the interpolator 141, and the 4x1 MUX 143 receives a digitized signal and receives a double specific phase, For example, a function of inputting a signal having a phase of 90 degrees to the half-rate PD 151 as the second feedback signal may be performed.

Here, the half-rate PD 151 may perform the function of sampling the input signal at the rising edge and the falling edge of the second feedback signal.

Meanwhile, while the input signal corresponds to the data receiving section, the apparatus may further include a serializer 160 for receiving an input signal sampled by the half-rate PD 151 and restoring original data. In addition, the serializer 160 may perform a function of restoring data by serializing the sampling data at the rising edge and the falling edge using 2 × 1 MUX. For example, referring to FIG. 4, it can be seen that Data 1 is sampled at the rising edge of the clock having a phase of 90 degrees and Data 2 is sampled at the falling edge. The two sampling data are serialized using a 2: 1 MUX. To restore the original data.

Here, in the description with reference to FIG. 3, the case of restoring data using the 4x1 MUX 143 and the Half-Rate PD 151 has been described as an example, but the present disclosure is not limited thereto and various modifications may be assumed. will be.

For example, instead of selecting a 90 degree phase on the 4x1 MUX 143 to be input to the Half-Rate PD 151 using both rising and falling edges, select a 90 degree and 270 degree phase on the 4x2 MUX. And they can be input to two full-rate PDs, respectively. Here, the two full-rate PDs may each sample at the rising edge of the clock of 90 degrees and perform sampling at the rising edge of the clock of 270 degrees.

Although the present invention has been described by specific embodiments such as specific components and the like, but the embodiments and the drawings are provided to assist in a more general understanding of the present invention, the present invention is not limited to the above embodiments. For those skilled in the art, various modifications and variations can be made from these descriptions. Therefore, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, I will say.

110: PLL input circuit
120: band selection circuit section
130: dispenser
140: interpolator
150: data recovery input circuit unit
160: serializer

Claims (11)

In a clock and data recovery apparatus supporting a wide frequency range for low frequency,
While the input signal corresponds to the training sequence (input form in which 1 and 0 are repeated periodically),
Receives the first feedback signal of the input signal and the PLL loop, adjusts the phase and frequency between the input signal and the first feedback signal, and processes these signals to rotate the PLL loop to a voltage controlled oscillator (VCO). PLL input circuit section to be input,
A band selection circuit unit including at least one VCO, for selecting a specific VCO among the at least one VCO with reference to a frequency range of a clock that the VCO can output;
A divider for receiving the output of the specific VCO and adjusting the frequency of the output of the specific VCO to a predetermined division ratio to provide the first feedback signal to the PLL component circuitry.
Switching a signal to flow along the PLL loop configured to include, while the input signal corresponds to a data (significant information other than the training sequence) receiving interval,
Receiving a second feedback signal of the input signal and the data recovery loop (Data Recovery Loop) to match the phase between the input signal and the second feedback signal, and processing these signals to run the data recovery loop to the specific A data recovery input circuit unit configured to be input to a VCO and to sample the input signal with reference to the second feedback signal;
A VCO unit for receiving an output of the data recovery input circuit unit and outputting a clock according to a frequency covered by the specific VCO to the divider;
A divider for receiving an output of the VCO unit and adjusting a frequency of the output of the VCO unit to a predetermined division ratio; and
An interpolation unit for receiving the output of the divider, dividing the signal into four phases, outputting a signal of a specific phase among them, and transmitting the second feedback signal to the data recovery input circuit unit;
And switch a signal to flow along the data recovery loop configured to include. The method of claim 1,
The PLL input circuit unit,
Receiving the output of the input signal and the divider as the first feedback signal while the input signal corresponds to the training sequence section, and for detecting a phase difference and a frequency difference between the input signal and the first feedback signal. PFD,
A charge pump for pushing and pulling an amount of charge determined by referring to the output of the PFD, and
And a loop filter including a capacitor for accumulating or releasing charge that is pushed and pulled by said charge pump and providing an output to said band selection circuitry. The method of claim 2,
And the loop filter is a low pass filter (LPF). The method of claim 2,
The band selection circuit unit,
While the input signal corresponds to the training sequence interval,
A plurality of VCOs for receiving the output of the loop filter as an input voltage and outputting a frequency proportional thereto; and
A finite state machine (FSM) capable of outputting a VCO selection signal for selecting the specific VCO among the plurality of VCOs by receiving a comparator output signal output by passing the output of the loop filter through a predetermined comparator.
Apparatus comprising a. The method of claim 4, wherein
The divider is,
Receiving the output of the FSM, adjusting the predetermined division ratio, and adjusting the frequency of the output of the specific VCO according to the adjusted division ratio to provide the PFD as the first feedback signal. The method of claim 1,
And a serializer for receiving an input signal sampled by the data recovery input circuit unit and restoring original data. The method of claim 6,
The data recovery input circuit unit,
Half-Rate PD receiving the input signal and the second feedback signal from the interpolator while the input signal corresponds to the data reception section, and sampling the input signal with reference to the second feedback signal;
A charge pump for pushing and pulling an amount of charge determined by referring to the output of the half-rate PD, and
And a loop filter including a capacitor for accumulating or releasing charge that is pushed and pulled by said charge pump and providing an output to said VCO portion. The method of claim 7, wherein
The interpolation unit,
An interpolator for receiving the output of the divider and dividing it into four phases, and
4x1 MUX that receives the output of the interpolator and inputs a signal having a double specific phase to the Half-Rate PD as the second feedback signal
Apparatus comprising a. The method of claim 8,
The specific phase is 90 degrees. 10. The method of claim 9,
Wherein the Half-Rate PD samples the input signal at a rising edge and a falling edge of the second feedback signal. The method of claim 10,
The serializer,
And restore the data by serializing the sampling data at the rising edge and the falling edge using a 2x1 MUX.

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