KR20110133770A - Semiconductor package and stacked semiconductor package using the same - Google Patents

Semiconductor package and stacked semiconductor package using the same Download PDF

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Publication number
KR20110133770A
KR20110133770A KR1020100053358A KR20100053358A KR20110133770A KR 20110133770 A KR20110133770 A KR 20110133770A KR 1020100053358 A KR1020100053358 A KR 1020100053358A KR 20100053358 A KR20100053358 A KR 20100053358A KR 20110133770 A KR20110133770 A KR 20110133770A
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KR
South Korea
Prior art keywords
pad
substrate
semiconductor package
semiconductor chip
semiconductor
Prior art date
Application number
KR1020100053358A
Other languages
Korean (ko)
Inventor
이승엽
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100053358A priority Critical patent/KR20110133770A/en
Publication of KR20110133770A publication Critical patent/KR20110133770A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

A semiconductor package and a laminated semiconductor package having the same are disclosed. The disclosed semiconductor package includes a substrate having a connection pad formed on an upper surface thereof and a ball land formed on a lower surface thereof, a semiconductor chip mounted on the substrate and having a bonding pad formed thereon, and formed between the substrate and the semiconductor chip, An internal mounting part including a first pad connected to the first pad and a second pad electrically connected to the first pad and connected to a bonding pad of the semiconductor chip, and formed on the semiconductor chip and electrically connected to the first pad And a mounting frame including an external mounting unit on which a third pad is formed, a folding unit connecting the internal mounting unit and the external mounting unit.

Description

Semiconductor package and laminated semiconductor package having the same {SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE USING THE SAME}

The present invention relates to a semiconductor package and a laminated semiconductor package having the same.

As the trend toward thinner and shorter electronic devices has increased, high density and high mounting of the semiconductor package, which is a core element, have become an important factor.In the case of computers, a large amount of random access memory (RAM) and flash as the memory capacity increases Although the size of semiconductor chips such as flash memory is increased, semiconductor packages have been studied to be miniaturized according to the above requirements.

Meanwhile, one of several types of semiconductor packages capable of miniaturizing the size of a semiconductor package is a ball grid array package that attaches conductive balls to a lower portion of the semiconductor package. The ball grid array package has a spherical solder ball on the back surface of the substrate. Conductive balls such as balls are arranged in a predetermined state to be used instead of outer leads, and the package body area can be made smaller than the QFP (Quad Flat Package) type, and unlike QFP, there is no deformation of the lead. There is this.

1 is a cross-sectional view of a multilayer semiconductor package according to the prior art.

Referring to FIG. 1, the multilayer semiconductor package according to the related art has a structure in which second and third semiconductor packages 2 and 3 are stacked and connected on a first semiconductor package 1. At this time, the connection between the first, second, and third semiconductor packages 1, 2, and 3 is made by designing a circuit board of each semiconductor package longer than the package body and attaching solder balls 4 to the extra circuit board portions. .

However, in the related art, the circuit board has a problem of taking up a lot of space on the side surface as the length of the circuit board is longer than that of the package body.

SUMMARY OF THE INVENTION An object of the present invention is to provide a novel and lightweight semiconductor package and a laminated semiconductor package having the same.

According to an aspect of the present invention, a semiconductor package includes a substrate having a connection pad formed on an upper surface thereof and a ball land formed on a lower surface thereof, a semiconductor chip mounted on the substrate and formed with a bonding pad, and formed between the substrate and the semiconductor chip. An internal mounting part including a first pad connected to a connection pad of a substrate and a second pad electrically connected to the first pad and connected to a bonding pad of the semiconductor chip, and formed on the semiconductor chip And a mounting frame including an external mounting part including a third pad electrically connected to the external mounting part, a folding part connecting the internal mounting part and the external mounting part.

The mounting frame may further include a shielding member formed on an outer surface of the inner mounting portion, the outer mounting portion, and the folding portion and electrically separated from the first, second, and third pads.

The shield member is characterized in that it comprises copper.

And a first connection member formed between the connection pad of the substrate and the first pad of the internal mounting portion, and a second connection member formed between the second pad of the internal mounting portion and the bonding pad of the semiconductor chip. It features.

The first and second connection members may include any one of a solder ball and a bump.

And a first underfill member filled between the substrate and the internal mounting portion, and a second underfill member filled between the internal mounting portion and the semiconductor chip.

And a mold part for exposing an external connection terminal mounted on the ball land of the substrate and a third pad of the external mounting part and sealing the upper surface of the substrate including the mounting frame and the semiconductor chip.

According to another aspect of the present invention, a stacked semiconductor package includes a substrate having a connection pad formed on an upper surface thereof and a ball land formed on a lower surface thereof, a semiconductor chip mounted on the substrate and having a bonding pad formed therebetween, and formed between the substrate and the semiconductor chip. An internal mounting part including a first pad connected to a connection pad of the substrate and a second pad electrically connected to the first pad and connected to a bonding pad of the semiconductor chip, the semiconductor pad being formed on the semiconductor chip A mounting frame including an external mounting part having a third pad electrically connected to the first pad on a first surface facing the chip, a folding part connecting the internal mounting part and the external mounting part, and a ball land of the substrate; A plurality of semiconductor packages including a plurality of stacked semiconductor packages each including an external connection terminal to be mounted; The external connection terminal of the semiconductor package located on the upper side of the paper is mounted on the third pad of the mounting frame of the semiconductor package located on the lower side.

The semiconductor package may further include an additional semiconductor package stacked on a semiconductor package positioned on the top of the plurality of stacked semiconductor packages and having a different shape from the stacked plurality of semiconductor packages.

The additional semiconductor package includes a first semiconductor chip having a first pad having a connection pad formed on an upper surface thereof and a ball land formed on a lower surface thereof, a first semiconductor chip having a bonding pad connected to the connection pad of the first substrate, and a ball land of the first substrate. And a first external connection terminal mounted on the third pad of the mounting frame of the uppermost semiconductor package.

The additional semiconductor package may further include a first mold part sealing an upper surface of the first substrate including the first semiconductor chip.

According to the present invention, the side size of the semiconductor package can be effectively reduced, and the size of the multilayer semiconductor package using the same can be reduced. In addition, the electromagnetic wave is shielded, there is an effect that the electromagnetic interference by the electromagnetic wave is prevented.

1 is a cross-sectional view showing a laminated semiconductor package according to the prior art.
2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
3 and 4 are exploded views of the mounting frame.
5 is a cross-sectional view illustrating a multilayer semiconductor package according to a first embodiment of the present invention.
6 is a cross-sectional view illustrating a multilayer semiconductor package according to a second embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention, and FIGS. 3 and 4 are exploded views of a mounting frame.

Referring to FIG. 2, the semiconductor package 10 according to an embodiment of the present invention includes a substrate 100, a semiconductor chip 200, and a mounting frame 300. In addition, the apparatus further includes first and second connection members 400 and 500, first and second underfill members 600 and 700, a mold part 800, and an external connection terminal 900.

The substrate 100 may be a printed circuit board (PCB).

The substrate 100 has an upper surface 110 and a lower surface 120. The connection pad 130 is formed on the upper surface 110 of the substrate 100, and the ball land 140 is formed on the lower surface 120. The connection pad 130 and the borland 140 are electrically connected through a circuit pattern (not shown) formed in the substrate 100. Although not shown, the circuit pattern includes circuit wires formed on different layers and conductive vias connecting circuit wires formed on different layers.

The semiconductor chip 200 is mounted on the substrate 100.

The semiconductor chip 200 has one surface 210 corresponding to the substrate 100 and the other surface 220 opposite to one surface 210, and a bonding pad 230 is formed on one surface 210 of the semiconductor chip 200. .

The semiconductor chip 200 includes a circuit unit (not shown) for storing and processing data therein, and the bonding pad 230 corresponds to an electrical contact of a circuit unit for connection with the outside.

The mounting frame 300 is formed of a flexible insulating material, for example, a base film.

2 to 4, the mounting frame 300 includes an internal mounting unit 310, an external mounting unit 320, and a folding unit 330.

The internal mounting unit 310 is formed between the substrate 100 and the semiconductor chip 200.

The internal mounting unit 310 has one surface and the other surface opposite to one surface. One surface of the internal mounting unit 310 corresponds to the substrate 100, and the other surface of the internal mounting unit 310 corresponds to the semiconductor chip 200.

A first pad 311 connected to the connection pad 130 of the substrate 100 is formed on one surface of the internal mounting unit 310, and a bonding pad 230 of the semiconductor chip 200 is formed on the other surface of the internal mounting unit 310. The second pad 312 is formed to be connected to. The first pad 311 and the second pad 312 are electrically connected to each other through a first circuit pattern 341 formed in the mounting frame 300.

The first connection member 400 is formed between the connection pad 130 of the substrate 100 and the first pad 311 of the internal mounting unit 310. The first connection member 400 includes any one of a solder ball and a bump. In order to improve the reliability of the joint part, the first underfill member 600 is filled between the substrate 100 and the internal mounting part 310.

The second connection member 500 is formed between the second pad 312 of the internal mounting unit 310 and the bonding pad 230 of the semiconductor chip 200. The second connection member 500 includes any one of a solder ball and a bump. In order to improve the reliability of the joint part, the second underfill member 700 is filled between the internal mounting part 310 and the semiconductor chip 200.

The external mounting unit 320 is formed on the semiconductor chip 200. The external mounting unit 320 has a first surface facing the semiconductor chip 200 and a second surface facing the first surface. The third pad 321 is formed on the first surface of the external mounting unit 320. The third pad 321 is electrically connected to the first pad 311 of the internal mounting unit 310 through the second circuit pattern 342 formed in the mounting frame 300.

The folding unit 330 connects the internal mounting unit 310 and the external mounting unit 320.

The mounting frame 300 further includes a shielding member 340 for shielding electromagnetic waves.

The shielding member 340 is formed to be electrically separated from the first, second, and third pads 311, 312, and 321 on the outer surfaces of the inner mounting portion, the outer mounting portion, and the folding portions 310, 320, and 330. . In the present embodiment, the shield member 340 includes copper (Cu).

Referring again to FIG. 2, the mold part 800 seals the upper surface of the substrate 100 including the semiconductor chip 200 and the mounting frame 300, and the external connection terminal 900 is formed on the lower surface of the substrate 100. It is mounted to the ball land 140 formed in 102. In the present embodiment, the external connection terminal 900 is formed of solder balls.

Stacked semiconductor packages having the semiconductor package 10 described above are shown in FIGS. 5 and 6.

5 is a cross-sectional view illustrating a multilayer semiconductor package according to a first embodiment of the present invention.

Referring to FIG. 5, the multilayer semiconductor package 30 according to the first embodiment of the present invention has a structure in which three semiconductor packages 10 having the above-described structure are stacked on each other.

Although the present embodiment shows that three semiconductor packages 10 are stacked and described, the present invention is not limited thereto and includes all cases in which the number of stacked semiconductor packages 10 is two or more.

The external connection terminal 900 of the upper semiconductor package disposed above the semiconductor packages 10 is mounted on the third pad 321 of the lower semiconductor package. In this manner, three semiconductor packages 10 are sequentially stacked to form a laminated semiconductor package 30.

6 is a cross-sectional view illustrating a multilayer semiconductor package according to a second embodiment of the present invention.

The multilayer semiconductor package 40 according to the second embodiment of the present invention has a configuration substantially the same as that of the multilayer semiconductor package 30 according to the first embodiment described with reference to FIG. 5 except for the additional semiconductor package 20. Have Therefore, duplicate descriptions of the same components will be omitted, and the same components and the same reference numerals will be given to the same components.

Referring to FIG. 6, the multilayer semiconductor package 40 according to the second embodiment is a semiconductor package on a semiconductor package 10 positioned at the top of the multilayer semiconductor package 30 according to the first embodiment illustrated in FIG. 5. An additional semiconductor package 20 having a shape different from those of 10 is further laminated.

In the present embodiment, the additional semiconductor package 20 includes a first substrate 21, a first semiconductor chip 22, and a first external connection terminal 25. In addition, the first mold part 26 is further included.

The first substrate 21 may be a printed circuit board (PCB). The first substrate 21 has an upper surface 21A and a lower surface 21B. A connection pad 21C is formed on the upper surface 21A of the first substrate 21, and a ball land 21D is formed on the lower surface 21B.

The first semiconductor chip 22 is mounted on the top surface 21A of the first substrate 21. The first semiconductor chip 22 has a bonding pad 22A connected to the connection pad 21C of the first substrate 21 on one surface corresponding to the first substrate 21. A third connecting member 23 is formed between the connection pad 21C of the first substrate 21 and the bonding pad 22A of the first semiconductor chip 22. The third connection member 23 includes one of bump and solder balls. In order to improve the reliability of the joint part, the third underfill member 24 is filled between the first semiconductor chip 22 and the first substrate 21.

The first external connection terminal 25 is mounted on the first borland 21D formed on the lower surface 21B of the first substrate 21 and is mounted on the third pad 321 of the semiconductor package 10 positioned at the top thereof. do. In the present embodiment, the first external connection terminal 25 is formed of solder balls.

The first mold part 26 seals the upper surface of the first substrate 21 including the first semiconductor chip 22.

As described in detail above, the side size of the semiconductor package can be effectively reduced, and the size of the multilayer semiconductor package using the same can be reduced. In addition, the electromagnetic wave is shielded, there is an effect that the electromagnetic interference by the electromagnetic wave is prevented.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

100: semiconductor chip
200: substrate
300: mounting frame

Claims (11)

A substrate having a connection pad formed on an upper surface thereof and a ball land formed on a lower surface thereof;
A semiconductor chip mounted on the substrate and having a bonding pad formed thereon; and
An internal mounting part formed between the substrate and the semiconductor chip and including a first pad connected to the connection pad of the substrate and a second pad electrically connected to the first pad and connected to a bonding pad of the semiconductor chip; A mounting frame including an external mounting part formed on the semiconductor chip and having a third pad electrically connected to the first pad, and a folding part connecting the internal mounting part and the external mounting part;
A semiconductor package comprising a. The method of claim 1,
The mounting frame may further include a shielding member formed on an outer surface of the inner mounting portion, the outer mounting portion, and the folding portion and electrically separated from the first, second and third pads. The method of claim 2,
The shielding member comprises a semiconductor package, characterized in that the copper. The method of claim 1,
A first connection member formed between the connection pad of the substrate and the first pad of the internal mounting unit; and
A second connection member formed between the second pad of the inner mounting portion and the bonding pad of the semiconductor chip;
The semiconductor package further comprises. The method of claim 4, wherein
The first and second connection members, the semiconductor package, characterized in that it comprises any one of a solder ball, bump. The method of claim 4, wherein
A first underfill member filled between the substrate and the internal mounting portion;
A second underfill member filled between the internal mounting portion and the semiconductor chip;
The semiconductor package further comprises. The method of claim 1,
An external connection terminal mounted on the ball land of the substrate;
A mold part exposing the third pad of the external mounting part and sealing the upper surface of the substrate including the mounting frame and the semiconductor chip;
The semiconductor package further comprises. A substrate having a connection pad formed on an upper surface thereof and a ball land formed on a lower surface thereof, a semiconductor chip mounted on the substrate and having a bonding pad formed thereon, and a first pad formed between the substrate and the semiconductor chip and connected to a connection pad of the substrate And a second pad electrically connected to the first pad and connected to a bonding pad of the semiconductor chip, the first pad formed on the semiconductor chip and facing the semiconductor chip. A plurality of stacked frames each including an external mounting unit including an external mounting unit having a third pad electrically connected to the external connection unit, a folding unit connecting the internal mounting unit and the external mounting unit, and external connection terminals mounted on the ball lands of the substrate. Two semiconductor packages,
An external connection terminal of a semiconductor package positioned at an upper side of the plurality of stacked semiconductor packages is mounted on a third pad of a mounting frame of a semiconductor package positioned at a lower side thereof. The method of claim 8,
The semiconductor package of claim 1, further comprising an additional semiconductor package stacked on a semiconductor package positioned on a top of the stacked semiconductor packages and having a different shape from the stacked semiconductor packages. The method of claim 9,
The additional semiconductor package,
A first substrate having a connection pad formed on an upper surface thereof and a ball land formed on a lower surface thereof;
A first semiconductor chip having a bonding pad connected to the connection pad of the first substrate; and
A first external connection terminal mounted on a ball land of the first substrate and mounted on a third pad of a mounting frame of the uppermost semiconductor package;
Laminated semiconductor package comprising a. The method of claim 10,
The additional semiconductor package further comprises a first mold part sealing an upper surface of the first substrate including the first semiconductor chip.
KR1020100053358A 2010-06-07 2010-06-07 Semiconductor package and stacked semiconductor package using the same KR20110133770A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100053358A KR20110133770A (en) 2010-06-07 2010-06-07 Semiconductor package and stacked semiconductor package using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100053358A KR20110133770A (en) 2010-06-07 2010-06-07 Semiconductor package and stacked semiconductor package using the same

Publications (1)

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KR20110133770A true KR20110133770A (en) 2011-12-14

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