KR20110131777A - Bank architecture - Google Patents

Bank architecture Download PDF

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Publication number
KR20110131777A
KR20110131777A KR1020100051395A KR20100051395A KR20110131777A KR 20110131777 A KR20110131777 A KR 20110131777A KR 1020100051395 A KR1020100051395 A KR 1020100051395A KR 20100051395 A KR20100051395 A KR 20100051395A KR 20110131777 A KR20110131777 A KR 20110131777A
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KR
South Korea
Prior art keywords
bank
block
row decoder
repeater
signal
Prior art date
Application number
KR1020100051395A
Other languages
Korean (ko)
Inventor
최돈현
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100051395A priority Critical patent/KR20110131777A/en
Publication of KR20110131777A publication Critical patent/KR20110131777A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

The present invention relates to a bank structure capable of minimizing a row decoder by using a repeater (REPEATER) in a semiconductor device. According to an aspect of the present invention, there is provided a bank structure including: a row decoder configured to generate signals to be used in a bank at one side of a bank including a bank up block and a bank down block; A repeater is provided to perform a driving operation required in a process in which a signal generated by the row decoder is transferred to the bank up block or the bank down block.

Description

Bank Structure {BANK ARCHITECTURE}

The present invention relates to a bank structure capable of minimizing a row decoder by using a repeater (REPEATER) in a semiconductor device.

The semiconductor memory device includes a large number of cells CELL, which are data storage spaces. The cell may include a storage node for storing data, a bit line serving as a data input / output line, a cell transistor connecting the storage node to the bit line, and a word line serving as the cell transistor gate voltage line. It is composed. The cells constructed in this way are divided into banks, and the semiconductor memory device has a plurality of banks. 1 illustrates such a conventional bank structure. In the conventional bank structure shown, the semiconductor device activates a word line and performs a necessary control operation while increasing a row address for each bank.

Figure 2 shows in more detail each bank structure in the prior art. In the bank structure shown, a row decoder and a global signal according to row address generation are shown for each bank.

In the conventional bank structure, two row decoders (X-DEC) are provided for bank 0 as shown. Since the two row decoders are provided in the long axis direction of the chip as shown in the drawing, there is a problem in that the net-die (NET-DIE) competitiveness due to the layout configuration is inferior.

Accordingly, an object of the present invention is to provide a bank structure that can reduce the consumption area of a row decoder in a bank structure composed of a plurality of banks.

A bank structure according to the present invention for achieving the above object, in a bank structure having a plurality of banks, a row decoder provided on one side of the bank consisting of a bank up block and a bank down block to generate signals to be used in the bank ; A repeater is provided to perform a driving operation required in a process in which a signal generated by the row decoder is transferred to the bank up block or the bank down block.

The present invention uses only one row decoder per bank. A repeater between the bank up block and the bank down block occupies a much smaller area than the row decoder. In addition, a driver for generating a signal to be used in the bank up block is installed inside the repeater, thereby eliminating the loading problem caused by the signal transfer from the row decoder to the bank up block directly. This configuration enables the present invention to reduce the size of the chip by the area difference while replacing the conventional spatial arrangement portion that the row decoder had to occupy with a repeater.

1 is a diagram illustrating a bank structure having a plurality of banks in the related art.
2 is a detailed structural diagram of one bank.
3 is a bank structure diagram having a plurality of banks according to an embodiment of the present invention.
4 is a detailed structural diagram of one bank according to an embodiment of the present invention.
5 is a block diagram illustrating a signal generator included in a row decoder according to an exemplary embodiment of the present invention.
6 is a block diagram of a signal generator included in a repeater according to an exemplary embodiment of the present invention.

Hereinafter, a bank structure according to the present invention will be described in detail with reference to the accompanying drawings.

3 illustrates a bank structure diagram according to an embodiment of the present invention. 4 shows a detailed arrangement diagram for each bank.

As shown, the present invention includes one row decoder (X-DEC) 30 corresponding to row address generation for each bank. That is, one row decoder 30 generates a bank up signal and a bank down signal. Therefore, in the bank structure of the present invention having eight banks, only eight row decoders are required. The row decoder 30 is provided in the longitudinal direction of the bank (chip), as shown in FIG. In the present invention, by using only one row decoder 30 in each bank, a repeater 40 is provided to solve a problem in the signal transmission process. The repeater 40 is located between the bank up block and the bank down block.

5 is a configuration of various signal generators included in the row decoder of the present invention. 6 illustrates a configuration of signal generators included in a repeater in the present invention.

The row decoder 30 of the present invention includes a block selector BLOCK SELECTION 20 for selecting a mat MAT in an up block B0_UP 10 of a bank and a down block B0_DN 11 of a bank. . And a generator (WLOFF GEN.) 21 for generating word line off signals WLOFF_U and WLOFF_D of the corresponding bank block through the mat selection signals MS_U and MS_D of the block selector 20. And a generator (BAX2 GEN.) 22 for generating an internal address signal.

The block selector 20, the word line off signal generator 21, and the internal address signal generator 22 generate a signal to be commonly used in the bank up block 10 and the bank down block 11. . Therefore, the above-described configurations are generated by dividing the signal to be used in the bank up block 10 and the signal to be used in the bank down block 11.

Next, the row decoder 30 further includes configurations for generating signals to be used in the bank down block 11. That is, the sense amplifier control signal generator (SA CTRL GEN .; 23), the bit line level equalization signal generator (BLEQ GEN .; 24), the word line control signal generator (FXB GEN .; Generate signals to be used in 11).

Meanwhile, the repeater internal configuration illustrated in FIG. 6 is a configuration for generating signals to be used in the bank up block 10. That is, the sense amplifier control signal generator SA CTRL GEN 26, the bit line level equalization signal generator BLEQ GEN 27, the word line control signal generator FXB GEN 28, and the like are provided in a bank up block ( Generate signals to be used in 10).

According to the above configuration, the bank structure of the present invention generates or transmits signals required by the bank up block and the bank down block through the following control.

First, as shown in FIG. 4, in the present invention, only one row decoder 30 is provided in one bank. A repeater 40 is provided between the bank up block 10 and the bank down block 11 to generate a signal to be used in the bank up block 10 using the signal generated by the row decoder 30. . Since the repeater 40 occupies a relatively much smaller area than the row decoder, the repeater 40 becomes very efficient for the layout configuration inside the chip.

Since the row decoder 30 is located at one side of the bank, the global signal transmitted from the row decoded 30 to the bank must be transmitted to both the bank up block 10 and the bank down block 11. Therefore, the bank down block 11 adjacent to the row decoder 30 has no problem in receiving and using the generated signal of the row decoder 30 as it is, but the bank up block 10 has no problem with the row decoder 30. ) And a certain interval is dropped, the loading (loading) becomes large. Therefore, this invention solves this part using the said repeater 40. FIG.

That is, the AXE <0>, <1> signals, which are the highest address of the row ROW, are decoded, are input to the respective mats MAT of the row decoder 30, and the block selector 20 receives the AXE < One of the mat select signals MS_U and MS_D is enabled in a high state in accordance with the high state of the 0> and <1> signals.

The mat select signal MS_U is transmitted to the repeater 40 through a global signal line, and is input to the sense amplifier control signal generator 26 and the bit line level signal equalization circuit 27 in the repeater 40. do. The sense amplifier control signal generation unit 26 enables one mat of the bank up block 10 by enabling the SAN_U signal and the SAP_U signal.

Meanwhile, the mat select signal MS_U input to the word line control signal generation unit 21 in the row decoder 30 enables the word line off control signal WLOFF_U and the word line off control signal WLOFF_U. Is transmitted to the repeater 40 through the global signal line. Then, it is input to the word line signal generator 28 inside the repeater 40 to control the precharge time of FXB_U <0: 7>. That is, the off timing of the word line is controlled.

Next, the mat select signal MS_D is input to the sense amplifier control signal generator 23 in the row decoder 30 and the bit line level signal equalization circuit 24. The sense amplifier control signal generator 23 enables the one mat of the bank down block 11 by enabling the SAN_D signal and the SAP_D signal.

Meanwhile, the mat select signal MS_D input to the word line control signal generator 21 in the row decoder 30 enables the word line off control signal WLOFF_D and the word line off control signal WLOFF_D. Is input to the word line signal generator 25 and controls the precharge time of FXB_D <0: 7>. That is, the off timing of the word line is controlled.

In the present invention, the SAENB and SAEPB signals used in the sense amplifier control signal generator and the AX01 <0: 3> signals used in the word line control signal generator are located in the XY-CROSS part located at some corners of the bank. It is made and delivered to the row decoder 30 and the repeater 40 through the global signal line.

As described above, the present invention uses only one using two row decoders per bank. A repeater between the bank up block and the bank down block occupies a much smaller area than the row decoder. In addition, a driver for generating a signal to be used in the bank up block is installed inside the repeater, thereby eliminating the loading problem caused by the signal transfer from the row decoder to the bank up block directly. This configuration enables the present invention to reduce the size of the chip by the area difference while replacing the conventional spatial arrangement portion that the row decoder had to occupy with a repeater.

The above-described preferred embodiment of the present invention is disclosed for the purpose of illustration, and is configured to reduce the area occupied by the row decoder by using a repeater in a plurality of bank structures to be applied when controlling the operation of the bank. Can be. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

10,11 bank block 20block selector
21: word line off control signal generator 22: internal address generator
23, 26: sense amplifier control signal generator 30: row decoder
24, 27: bit line level signal equalization circuit 40: repeater
25,28: word line control signal generator

Claims (3)

A bank structure having a plurality of banks, comprising: a row decoder provided on one side of a bank including a bank up block and a bank down block to generate signals to be used in the bank;
And a repeater for performing a driving operation required in a process in which a signal generated by the row decoder is transferred to the bank up block or the bank down block. The method of claim 1,
The repeater is provided between a bank up block and a bank down block. The method of claim 2,
The repeater may include a generator for generating a sense amplifier control signal and a bit line level equalization signal word line control signal to be used in a bank up block by using a mat selection signal received through a global line from the row decoder. The bank structure characterized by the above-mentioned.

KR1020100051395A 2010-05-31 2010-05-31 Bank architecture KR20110131777A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100051395A KR20110131777A (en) 2010-05-31 2010-05-31 Bank architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100051395A KR20110131777A (en) 2010-05-31 2010-05-31 Bank architecture

Publications (1)

Publication Number Publication Date
KR20110131777A true KR20110131777A (en) 2011-12-07

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100051395A KR20110131777A (en) 2010-05-31 2010-05-31 Bank architecture

Country Status (1)

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KR (1) KR20110131777A (en)

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