KR102017182B1 - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
- Publication number
- KR102017182B1 KR102017182B1 KR1020120095698A KR20120095698A KR102017182B1 KR 102017182 B1 KR102017182 B1 KR 102017182B1 KR 1020120095698 A KR1020120095698 A KR 1020120095698A KR 20120095698 A KR20120095698 A KR 20120095698A KR 102017182 B1 KR102017182 B1 KR 102017182B1
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- KR
- South Korea
- Prior art keywords
- cell
- column
- decoding unit
- mat
- row
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
A semiconductor memory device having a cell mat, comprising: a memory bank including a plurality of cell mats, a row address decoding unit for decoding a row address to select a row column of the plurality of cell mats, and a column address And a column address decoding unit for selecting column columns of the plurality of cell mats, wherein the column address decoding unit receives activation information of the plurality of cell mats from the row address decoding unit. do.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to a semiconductor memory device having a cell mat.
In general, as the integration of semiconductor memory devices including DDR Double Data Rate Synchronous DRAM (SDRAM) increases rapidly, tens of millions of memory cells are provided in one semiconductor memory device. These memory cells are arranged in an array according to a predetermined rule, and the memory cell arrays are grouped in a predetermined number and are called a cell mat.
1 is a block diagram for describing a part of a general semiconductor memory device.
Referring to FIG. 1, a semiconductor memory device includes a
The
The row
The column
Hereinafter, a simple circuit operation of the semiconductor memory device will be described.
First, when the row address ADD_ROW is input from the outside, the row
Then, when the column address ADD_COL is input from the outside, the column
As described above, the semiconductor memory device selects a row column and a column column of a plurality of memory cell arrays to access memory cells corresponding to the row address ADD_ROW and the column address ADD_COL and perform a read or write operation on the accessed memory cells. Perform.
As shown in the figure, the first to n-th mat activation information INF_M1, INF_M2, INF_M3, ... INF_Mn are transmitted to the column
Embodiments of the present invention provide a semiconductor memory device in which signal transmission lines for transmitting cell mat activation signals are efficiently arranged.
In an embodiment, a semiconductor memory device may include a memory bank including a plurality of cell mats; A row address decoding unit for decoding row addresses and selecting row columns of the plurality of cell mats; And a column address decoding unit for decoding a column address and selecting column columns of the plurality of cell mats, wherein the column address decoding unit receives activation information of the plurality of cell mats from the row address decoding unit. can do.
In an embodiment, a semiconductor memory device may include a memory bank disposed in a core region and including a plurality of cell mats; A mat information generator disposed in the ferry area and configured to receive row addresses and generate activation information of the plurality of cell mats; And a column address decoding unit disposed in the ferry area and configured to select column columns of the plurality of cell mats in response to the activation information and the column address.
In an embodiment, a semiconductor memory device may include: a normal cell mat disposed in a core region and including a normal memory cell array; A redundancy cell mat disposed in the core region, the redundancy cell mat including a redundancy memory cell array for generating its own activation information-first activation information; A mat information generator arranged in the ferry area and configured to receive a row address and generate activation information of the normal cell mat-second activation information; And a column address decoding unit disposed in the ferry area and configured to select a column column of the memory cell array in response to the first and second activation information and the column address.
Preferably, the plurality of redundant cell mats may be provided, and each of the plurality of redundant cell mats may transmit corresponding first activation information to the column address decoding unit.
According to the embodiment of the present invention, it is possible to efficiently arrange the signal transmission line for transmitting the cell mat activation signal, thereby reducing the burden in designing the core region.
By effectively arranging signal transmission lines carrying cell mat activation signals, the spatial efficiency of the core area can be increased.
1 is a block diagram for describing a part of a general semiconductor memory device.
2 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a first embodiment of the present invention.
3 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a second embodiment of the present invention.
Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .
2 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a first embodiment of the present invention.
2, a semiconductor memory device includes a
The
The row
The column
In the semiconductor memory device according to the first embodiment of the present invention, the cell mat activation information INF_M is generated in the
Before describing the second embodiment, a redundancy cell provided in the semiconductor memory device will be described.
As described above, innumerable memory cells exist in the cell mat of the semiconductor memory device, and if any one of the memory cells fails, the semiconductor memory device may not perform a desired operation. . In recent years, as the process technology of semiconductor memory devices develops, there is a probability that defects occur only in a small amount of memory cells. ) Is very inefficient. Therefore, in order to compensate for this, the semiconductor memory device includes not only a normal memory cell but also a redundancy memory cell that is separately designed. If a defect occurs in the normal memory cell, the redundancy memory is included. It is used by replacing a cell. In the second embodiment to be described below, a redundancy cell mat including this redundancy memory cell array is constructed.
3 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a second embodiment of the present invention.
Referring to FIG. 3, a semiconductor memory device includes a
The
The row
The column
The semiconductor memory device according to the second embodiment of the present invention generates normal cell mat activation information INF_NOR_M in the
Hereinafter, a brief circuit operation of the semiconductor memory device according to the second embodiment will be described.
First, when a row address ADD_ROW is input from the outside, the row
Meanwhile, if the row address ADD_ROW accesses a defective normal memory cell, the word line of the
Then, when the column address ADD_COL is input from the outside, the column
As described above, the semiconductor memory device according to the first and second embodiments of the present invention generates a cell mat activation signal corresponding to a normal cell mat in the ferry region, and thus, when designing the core region, the cell mat activation signal It is not necessary to consider the arrangement of the signal transmission line for transmitting the. That is, the burden on designing the core region can be reduced, which means that the space efficiency of the core region is increased.
Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.
In the above-described embodiment, the redundancy activation information INF_RDC_M is generated as an example in the
In addition, the position and type of the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently according to the polarity of the input signal.
210: memory bank
220: row address decoding section
230: column address decoding unit
Claims (6)
A row address decoding unit for decoding row addresses and selecting row columns of the plurality of cell mats; And
A column address decoding unit for decoding a column address and selecting column columns of the plurality of cell mats,
And the column address decoding unit receives activation information of the plurality of cell mats from the row address decoding unit.
A mat information generator disposed in the ferry area and configured to receive row addresses and generate activation information of the plurality of cell mats; And
A column address decoding unit disposed in the ferry area and configured to select column columns of the plurality of cell mats in response to the activation information and column addresses
A semiconductor memory device having a.
A redundancy cell mat disposed in the core region, the redundancy cell mat including a redundancy memory cell array for generating its own activation information-first activation information;
A mat information generator arranged in the ferry area and configured to receive a row address and generate activation information of the normal cell mat-second activation information; And
A column address decoding unit disposed in the ferry region and configured to select a corresponding column column among the normal memory cell array or the redundant memory cell array in response to the first and second activation information and a column address;
A semiconductor memory device having a.
And a row address decoding unit configured to decode the row address to select a row column of the normal cell mat and the redundancy cell mat.
It is provided with a plurality of redundancy cell mat,
Each of the plurality of redundancy cell mats transfers corresponding first activation information to the column address decoding unit.
Priority Applications (1)
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KR1020120095698A KR102017182B1 (en) | 2012-08-30 | 2012-08-30 | Semiconductor memory device |
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KR1020120095698A KR102017182B1 (en) | 2012-08-30 | 2012-08-30 | Semiconductor memory device |
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KR20140029841A KR20140029841A (en) | 2014-03-11 |
KR102017182B1 true KR102017182B1 (en) | 2019-09-02 |
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