KR102017182B1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR102017182B1
KR102017182B1 KR1020120095698A KR20120095698A KR102017182B1 KR 102017182 B1 KR102017182 B1 KR 102017182B1 KR 1020120095698 A KR1020120095698 A KR 1020120095698A KR 20120095698 A KR20120095698 A KR 20120095698A KR 102017182 B1 KR102017182 B1 KR 102017182B1
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South Korea
Prior art keywords
cell
column
decoding unit
mat
row
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KR1020120095698A
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Korean (ko)
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KR20140029841A (en
Inventor
신선혜
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에스케이하이닉스 주식회사
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Priority to KR1020120095698A priority Critical patent/KR102017182B1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device having a cell mat, comprising: a memory bank including a plurality of cell mats, a row address decoding unit for decoding a row address to select a row column of the plurality of cell mats, and a column address And a column address decoding unit for selecting column columns of the plurality of cell mats, wherein the column address decoding unit receives activation information of the plurality of cell mats from the row address decoding unit. do.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to a semiconductor memory device having a cell mat.

In general, as the integration of semiconductor memory devices including DDR Double Data Rate Synchronous DRAM (SDRAM) increases rapidly, tens of millions of memory cells are provided in one semiconductor memory device. These memory cells are arranged in an array according to a predetermined rule, and the memory cell arrays are grouped in a predetermined number and are called a cell mat.

1 is a block diagram for describing a part of a general semiconductor memory device.

Referring to FIG. 1, a semiconductor memory device includes a memory bank 110, a row address decoding unit 120, and a column address decoding unit 130. For reference, the memory bank 110 is disposed in the core region 140, and the row address decoding unit 120 and the column address decoding unit 130 are disposed in the ferry region 150.

The memory bank 110 includes first to n-th cell mats 110_1, 110_2, 110_3,... 110_n each configured of a plurality of memory cell arrays, and the first to n-th cell mats 110_1, 110_2, 110_3. The first to nth mat activation information (INF_M1, INF_M2, INF_M3, ... INF_Mn) generated in each of the ... ... 110_n) has a word line activated on its mat in response to the row select signal WL. Has information. In other words, the first to nth mat activation information INF_M1, INF_M2, INF_M3,... INF_Mn have activation information of the corresponding cell mat.

The row address decoding unit 120 decodes a row address ADD_ROW input from the outside to generate a row select signal WL. Here, the row select signal WL is a signal for selecting a row column of the memory cell array included in the first to nth cell mats 110_1, 110_2, 110_3,... 110_n.

The column address decoding unit 130 generates a column selection signal YI by decoding the column address ADD_COL input from the outside. Here, the column select signal YI is a signal for selecting a column column of the memory cell array included in the first to nth cell mats 110_1, 110_2, 110_3,... 110_n.

Hereinafter, a simple circuit operation of the semiconductor memory device will be described.

First, when the row address ADD_ROW is input from the outside, the row address decoding unit 120 decodes the row address to activate the corresponding row select signal WL, and in response to the row select signal WL, the first to n th signals are output. The word lines of the corresponding row columns of the memory cell arrays of the cell mats 110_1, 110_2, 110_3,... 110_n are activated. Here, activation of the word line means that the row column corresponding to the row address ADD_ROW is selected. In this case, the cell mat transmits information indicating that the word line is activated, that is, mat activation information, to the column address decoding unit 130.

Then, when the column address ADD_COL is input from the outside, the column address decoding unit 130 decodes it to activate the corresponding column select signal YI, and according to the column select signal YI, the first to nth cells. The bit lines of the corresponding column columns of the memory cell arrays of the mats 110_1, 110_2, 110_3,... 110_n are activated. Here, activation of the bit line means that the column column corresponding to the column address ADD_COL is selected.

As described above, the semiconductor memory device selects a row column and a column column of a plurality of memory cell arrays to access memory cells corresponding to the row address ADD_ROW and the column address ADD_COL and perform a read or write operation on the accessed memory cells. Perform.

As shown in the figure, the first to n-th mat activation information INF_M1, INF_M2, INF_M3, ... INF_Mn are transmitted to the column address decoding unit 130 through n signal transmission lines. That is, n signal transmission lines must be arranged in the core region 140. However, since the core region 140 is a region where the memory cell array and the control circuits for sensing and amplifying the memory cells are concentrated, the first to nth mat activation information INF_M1, INF_M2, INF_M3, ... INF_Mn are transmitted. N signal transmission lines to be a burden when designing the core region 140.

Embodiments of the present invention provide a semiconductor memory device in which signal transmission lines for transmitting cell mat activation signals are efficiently arranged.

In an embodiment, a semiconductor memory device may include a memory bank including a plurality of cell mats; A row address decoding unit for decoding row addresses and selecting row columns of the plurality of cell mats; And a column address decoding unit for decoding a column address and selecting column columns of the plurality of cell mats, wherein the column address decoding unit receives activation information of the plurality of cell mats from the row address decoding unit. can do.

In an embodiment, a semiconductor memory device may include a memory bank disposed in a core region and including a plurality of cell mats; A mat information generator disposed in the ferry area and configured to receive row addresses and generate activation information of the plurality of cell mats; And a column address decoding unit disposed in the ferry area and configured to select column columns of the plurality of cell mats in response to the activation information and the column address.

In an embodiment, a semiconductor memory device may include: a normal cell mat disposed in a core region and including a normal memory cell array; A redundancy cell mat disposed in the core region, the redundancy cell mat including a redundancy memory cell array for generating its own activation information-first activation information; A mat information generator arranged in the ferry area and configured to receive a row address and generate activation information of the normal cell mat-second activation information; And a column address decoding unit disposed in the ferry area and configured to select a column column of the memory cell array in response to the first and second activation information and the column address.

Preferably, the plurality of redundant cell mats may be provided, and each of the plurality of redundant cell mats may transmit corresponding first activation information to the column address decoding unit.

According to the embodiment of the present invention, it is possible to efficiently arrange the signal transmission line for transmitting the cell mat activation signal, thereby reducing the burden in designing the core region.

By effectively arranging signal transmission lines carrying cell mat activation signals, the spatial efficiency of the core area can be increased.

1 is a block diagram for describing a part of a general semiconductor memory device.
2 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a first embodiment of the present invention.
3 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a second embodiment of the present invention.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a first embodiment of the present invention.

2, a semiconductor memory device includes a memory bank 210, a row address decoding unit 220, and a column address decoding unit 230. As will be described below, in the first embodiment of the present invention, the cell mat activation information INF_M is generated in the ferry region 250.

The memory bank 210 includes first to nth cell mats 210_1, 210_2, 210_3,... 210_n each configured of a plurality of memory cell arrays. The first to n-th cell mats 210_1, 210_2, 210_3,... 210_n may select row rows of the corresponding cell mat in response to the row select signal WL and corresponding cell mats in response to the column select signal YI. The column column of is selected.

The row address decoding unit 220 generates a row select signal WL by decoding the row address ADD_ROW input from the outside. More specifically, the row address decoding unit 220 includes a mat information generation unit 221, which generates the cell mat activation information INF_M and generates the column address decoding unit 230. To pass. Here, the cell mat activation information INF_M has information about the cell mat activated among the first to nth cell mats 210_1, 210_2, 210_3,... 210_n in response to the row address ADD_ROW.

The column address decoding unit 230 generates a column selection signal YI in response to an externally input column address ADD_COL and cell mat activation information INF_M.

In the semiconductor memory device according to the first embodiment of the present invention, the cell mat activation information INF_M is generated in the ferry region 250, and the column address decoder 230 is generated through a signal transmission line disposed in the ferry region 250. To pass). In the first embodiment, the cell mat activation information INF_M is transmitted by arranging only one signal transmission line for transmitting cell mat activation information INF_M. However, a plurality of cell mats are arranged by arranging a plurality of signal transmission lines. It is also possible to deliver the activation information INF_M in parallel.

Before describing the second embodiment, a redundancy cell provided in the semiconductor memory device will be described.

As described above, innumerable memory cells exist in the cell mat of the semiconductor memory device, and if any one of the memory cells fails, the semiconductor memory device may not perform a desired operation. . In recent years, as the process technology of semiconductor memory devices develops, there is a probability that defects occur only in a small amount of memory cells. ) Is very inefficient. Therefore, in order to compensate for this, the semiconductor memory device includes not only a normal memory cell but also a redundancy memory cell that is separately designed. If a defect occurs in the normal memory cell, the redundancy memory is included. It is used by replacing a cell. In the second embodiment to be described below, a redundancy cell mat including this redundancy memory cell array is constructed.

3 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a second embodiment of the present invention.

Referring to FIG. 3, a semiconductor memory device includes a memory bank 310, a row address decoding unit 320, and a column address decoding unit 330.

The memory bank 310 includes a normal cell mat 311 and a redundancy cell mat 312. The redundancy cell mat 312 according to the second embodiment of the present invention may generate the redundancy cell mat activation information INF_RDC_M corresponding to the word line included in the redundancy cell mat 312 and transmit it to the column address decoding unit 330. Do.

The row address decoding unit 320 generates a row select signal WL by decoding the row address ADD_ROW input from the outside. In more detail, the row address decoding unit 320 includes a mat information generation unit 321, which generates the normal cell mat activation information INF_NOR_M and generates a column address decoding unit 330. To pass). Here, the normal cell mat activation information INF_NOR_M has information about the normal cell mat activated in the normal cell mat 311 in response to the row address ADD_ROW.

The column address decoding unit 330 generates a column selection signal YI in response to an externally input column address ADD_COL, normal cell mat activation information INF_NOR_M, and redundancy cell mat activation information INF_RDC_M.

The semiconductor memory device according to the second embodiment of the present invention generates normal cell mat activation information INF_NOR_M in the ferry region 350, and generates redundancy cell mat activation information INF_RDC_M in the core region 340.

Hereinafter, a brief circuit operation of the semiconductor memory device according to the second embodiment will be described.

First, when a row address ADD_ROW is input from the outside, the row address decoding unit 320 decodes it to activate a corresponding row select signal WL, and in response to the row select signal WL, the normal cell mat 311. The word line of the corresponding row column of the memory cell array is activated. At this time, the mat information generator 321 of the row address decoder 320 generates information indicating that the word line of the corresponding normal cell mat is activated, that is, normal matt activation information INF_NOR_M, and transmits the generated information to the column address decoder 330. do.

Meanwhile, if the row address ADD_ROW accesses a defective normal memory cell, the word line of the redundancy cell mat 312 is activated. At this time, the redundancy cell mat 312 generates information indicating that the word line of the corresponding redundancy cell mat is activated, that is, redundancy mat activation information INF_RDC_M, and transmits the information to the column address decoding unit 330.

Then, when the column address ADD_COL is input from the outside, the column address decoding unit 130 activates the column selection signal YI according to the normal mat activation information INF_NOR_M and the redundancy mat activation information INF_RDC_M, and selects this column. According to the signal YI, the bit line of the corresponding column column of the normal cell mat 311 or the memory cell array of the redundancy cell mat 312 is activated.

As described above, the semiconductor memory device according to the first and second embodiments of the present invention generates a cell mat activation signal corresponding to a normal cell mat in the ferry region, and thus, when designing the core region, the cell mat activation signal It is not necessary to consider the arrangement of the signal transmission line for transmitting the. That is, the burden on designing the core region can be reduced, which means that the space efficiency of the core region is increased.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

In the above-described embodiment, the redundancy activation information INF_RDC_M is generated as an example in the core region 340. However, when the row address decoding unit 320 detects whether a repair operation is performed, the redundancy activation unit INF_RDC_M is also ferry. It is possible to create in area 350.

In addition, the position and type of the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently according to the polarity of the input signal.

210: memory bank
220: row address decoding section
230: column address decoding unit

Claims (6)

A memory bank comprising a plurality of cell mats;
A row address decoding unit for decoding row addresses and selecting row columns of the plurality of cell mats; And
A column address decoding unit for decoding a column address and selecting column columns of the plurality of cell mats,
And the column address decoding unit receives activation information of the plurality of cell mats from the row address decoding unit.
A memory bank disposed in the core region and including a plurality of cell mats;
A mat information generator disposed in the ferry area and configured to receive row addresses and generate activation information of the plurality of cell mats; And
A column address decoding unit disposed in the ferry area and configured to select column columns of the plurality of cell mats in response to the activation information and column addresses
A semiconductor memory device having a.
delete A normal cell mat disposed in the core region and including a normal memory cell array;
A redundancy cell mat disposed in the core region, the redundancy cell mat including a redundancy memory cell array for generating its own activation information-first activation information;
A mat information generator arranged in the ferry area and configured to receive a row address and generate activation information of the normal cell mat-second activation information; And
A column address decoding unit disposed in the ferry region and configured to select a corresponding column column among the normal memory cell array or the redundant memory cell array in response to the first and second activation information and a column address;
A semiconductor memory device having a.
Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein
And a row address decoding unit configured to decode the row address to select a row column of the normal cell mat and the redundancy cell mat.
Claim 6 has been abandoned upon payment of a setup registration fee. The method of claim 4, wherein
It is provided with a plurality of redundancy cell mat,
Each of the plurality of redundancy cell mats transfers corresponding first activation information to the column address decoding unit.
KR1020120095698A 2012-08-30 2012-08-30 Semiconductor memory device KR102017182B1 (en)

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