KR20110127091A - Low-temperature polysilicon thin film and method of manufacturing the same, transistor and display apparatus - Google Patents

Low-temperature polysilicon thin film and method of manufacturing the same, transistor and display apparatus Download PDF

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KR20110127091A
KR20110127091A KR1020110046992A KR20110046992A KR20110127091A KR 20110127091 A KR20110127091 A KR 20110127091A KR 1020110046992 A KR1020110046992 A KR 1020110046992A KR 20110046992 A KR20110046992 A KR 20110046992A KR 20110127091 A KR20110127091 A KR 20110127091A
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thin film
low temperature
temperature polysilicon
polysilicon thin
amorphous silicon
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KR1020110046992A
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Korean (ko)
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김원석
김필석
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보에 테크놀로지 그룹 컴퍼니 리미티드
청두 비오이 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드
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Application filed by 보에 테크놀로지 그룹 컴퍼니 리미티드, 청두 비오이 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 filed Critical 보에 테크놀로지 그룹 컴퍼니 리미티드
Publication of KR20110127091A publication Critical patent/KR20110127091A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE: A polysilicon thin film with low temperature by interlayer grain growth silicon, a manufacturing method thereof, a transistor, and a display device thereof are provided to efficiently control an off-state current by arranging a catalyst layer in the intermediate position of an amorphous silicon layer. CONSTITUTION: A buffer layer(12) is formed on a substrate. A first amorphous silicon thin film is formed in the buffer layer. A catalyst particle(22) is formed in the first amorphous silicon thin film. A second amorphous silicon thin film is formed to cover the first amorphous silicon thin film and the catalyst particle. A polysilicon thin film with low temperature is formed by crystallizing the first amorphous silicon thin film and the second amorphous silicon thin film using the catalyst particle.

Description

Low-temperature polysilicon thin film and method of manufacturing the same, transistor and display apparatus

The present invention relates to a low temperature polysilicon thin film, a method of manufacturing the same, a transistor, and a display device.

With the development of flat panel display technology, the Active Matrix Organic Light Emitting Diode (hereinafter abbreviated as AMOLED) has advantages in lightness, thickness, self-luminous and high response speed. Has become a development trend of liquid crystal display devices.

The AMOLED includes an active switch, an insulating layer, a transparent layer, a light emitting layer, and a metal which are sequentially formed on a bottom layer of a substrate. Among them, the active switch is transparently connected through the contact hole in order to control the writing of the image data. In response to the recent increase in AMOLED size, an active switch usually adopts a low temperature poly-silicon TFT (hereinafter abbreviated as LTPS-TFT) as a pixel switch control element. The quality of the low temperature polysilicon thin film used to fabricate the LTPS-TFT is directly related to the representation of the electrical properties of the LTPS-TFT. Therefore, the manufacturing technology of low temperature polysilicon thin film is getting more and more attention.

In addition, a low-temperature polysilicon thin film can be manufactured by employing a non-laser metal induced crystallization method (hereinafter referred to as MIC). The process of this MIC method is shown in FIGS.

1 is a schematic diagram (1) of a cross section of a manufacturing process according to an embodiment of a conventional method for producing a low temperature polysilicon thin film, and FIG. 3 is a schematic diagram (2) of a cross section, and FIG. 3 is a schematic diagram (3) of a cross section of a manufacturing process according to an embodiment of a conventional method for producing a low temperature polysilicon thin film.

First, nickel particles 13 are applied to the surface of the buffer layer 12 disposed on the glass substrate 11, and then the amorphous silicon layer 14 covering the buffer layer 12 and the nickel particles 13 is deposited. . The amorphous silicon layer 14 is converted into a polysilicon layer through a crystallization process. The polysilicon layer contains polysilicon crystal particles 15 in which a plurality of nickel particles 13 are grown as nuclei.

The distribution of the threshold voltage Vth of the transistor produced from the low temperature polysilicon thin film obtained by the MIC method is relatively stable. However, the following drawbacks exist. That is, in the crystallization process, nickel silicide is formed on the contact surface 16 of the amorphous silicon layer 14 and the nickel particles 13 shown in FIG. 3. The contact surface 16 is a gate oxide interface during fabrication of the transistor by the low temperature polysilicon thin film, the nickel silicide has a constant conductivity, and the channel region when the fabricated low temperature polysilicon thin film transistor is in the off state. It becomes unstable by increasing the leakage current and causing a large off-state current.

A method for manufacturing a low temperature polysilicon thin film according to an embodiment of the present invention includes the steps of: preparing a substrate; forming a buffer layer on the substrate; forming a first amorphous silicon thin film on the buffer layer; Forming a particle of a catalyst in an amorphous silicon thin film, forming a second amorphous silicon thin film so as to cover the particles of the first amorphous silicon thin film and the catalyst, and using the particles of the catalyst, the first amorphous silicon And forming a low temperature polysilicon thin film by crystallizing the thin film and the second amorphous silicon thin film.

The low temperature polysilicon thin film according to another embodiment of the present invention is obtained by the method for producing the low temperature polysilicon thin film.

A low temperature polysilicon thin film transistor according to another embodiment of the present invention, comprising a substrate, the low temperature polysilicon thin film, and formed on the substrate and between the source region, the drain region, and the source region and the drain region. A semiconductor layer including a channel region positioned in the first region; a gate insulating layer sequentially formed on the semiconductor region; a gate corresponding to a position of the channel region; and a first layer formed on the gate and the gate insulating layer And a dielectric layer having a via hole and a second via hole, a source electrode connected to the source region via the first via hole, and a drain electrode connected to the drain region via the second via hole.

A display device according to still another embodiment of the present invention includes an array substrate, and the low temperature polysilicon thin film transistor is formed on the array substrate.

BRIEF DESCRIPTION OF DRAWINGS To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the drawings required for describing the embodiments or the prior art will be introduced. In addition, the following drawings are of course only examples of one embodiment of the present invention. Of course, those skilled in the art can obtain other drawings by the drawings even without creative labor.
1 to 3 are schematic views of a cross section of a manufacturing process according to an embodiment of the method for producing a low temperature polysilicon thin film,
4-8 is a schematic diagram of the cross section of the manufacturing process by the Example which concerns on the manufacturing method of the low temperature polysilicon thin film of this invention.
9 is a schematic diagram of a low temperature polysilicon thin film transistor according to an embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS Hereinafter, the technical solutions related to the embodiments of the present invention will be described in detail with reference to the drawings in order to clarify the objects, technical solutions, and advantages of the embodiments of the present invention. In addition, the described embodiment is only a part of the embodiment related to the present invention, but not all of the embodiments. In addition, all other embodiments that can be obtained by those skilled in the art based on the embodiments of the present invention in the absence of creative labor are included in the present invention.

An embodiment of the present invention provides a process for producing a low temperature polysilicon thin film using Interlayer Grain Growth Silicon (hereinafter, referred to as IGS) as an important technology. By placing a catalyst layer such as nickel at an intermediate position of the amorphous silicon layer so as to be positioned at an intermediate portion of the polysilicon layer in which later-growing metal silicon oxide, for example Ni silicide, is formed, It is prevented from being formed at the gate oxide interface. This effectively suppresses the off-state current of the transistor to prevent leakage.

Hereinafter, a description will be given in more detail with reference to the drawings and specific embodiments of the present invention.

<First Embodiment>

4 is a cross-sectional schematic diagram (1) of a manufacturing process of an embodiment of a method for manufacturing a low temperature polysilicon thin film according to the present invention, and FIG. 5 is a cross section of a manufacturing process of an embodiment of a manufacturing method of a low temperature polysilicon thin film according to the present invention. 6 is a schematic diagram (2), and FIG. 6 is a schematic cross-sectional view (3) of the manufacturing process of an embodiment of the method for producing a low temperature polysilicon thin film according to the present invention, and FIG. 7 is a method for manufacturing a low temperature polysilicon thin film according to the present invention. 8 is a cross-sectional schematic view 4 of the manufacturing process of the embodiment, and FIG. 8 is a cross-sectional schematic view 5 of the manufacturing process of the embodiment of the method for producing a low temperature polysilicon thin film according to the present invention. According to each of the above drawings, the method of this embodiment includes the following steps. In other words,

Step 101: A buffer layer is formed on the substrate.

Referring to FIG. 4, a substrate 11 is first provided, and the substrate 11 may be a glass substrate or a plastic substrate. A buffer layer 12 is formed on the substrate 11. The buffer layer 12 may be an oxide layer, for example, a silicon oxide layer. It is possible to prevent the material in the substrate 11 from affecting the quality of the low temperature polysilicon thin film produced by diffusion in the next process.

Step 102: Deposit a first amorphous silicon layer on the buffer layer.

Referring to FIG. 5, a first amorphous silicon thin film layer 21 is deposited on the buffer layer 12, and the first amorphous silicon thin film layer 21 is formed by a plasma enhanced chemical vapor deposition method or the like.

Step 103: The catalyst particles are applied to the first amorphous silicon thin film layer.

Subsequently, catalyst particles 22 are applied to the first amorphous silicon thin film layer 21 with reference to FIG. 6. For example, very small nickel particles may be used. The catalyst may be a polymetal or a mixture thereof, such as Cu, Al, Er, Cr, in addition to nickel.

Step 104: Deposit a second amorphous silicon thin film layer.

Referring to FIG. 7, a second amorphous silicon thin film layer 23 is formed on the first amorphous silicon thin film layer 21 and the plurality of catalyst particles 22. The second amorphous silicon thin film layer 23 completely covers the plurality of catalyst particles 22. The method for forming the second amorphous silicon thin film layer 23 may be the same as the method for forming the first amorphous silicon thin film layer 21.

Step 105: The amorphous silicon thin film layer is crystallized to form a low temperature polysilicon thin film with respect to the amorphous silicon thin film layer.

Rapid thermal annealing (hereinafter abbreviated as RTA), or heat treatment in a polysilicon smelter and then crystallize. Referring to FIG. 8, after the crystallization process, the amorphous silicon thin film forms a polysilicon thin film. The polysilicon thin film includes a first polysilicon thin film layer 21 'and a second polysilicon thin film layer 23', all of which include polysilicon particles 24 formed by growing a plurality of catalyst particles 22 as nuclei. do.

In this process, since the catalyst particles 22 are located at the interface between the first polysilicon thin film layer 21 'and the second polysilicon layer 23', the material in the catalyst particles 22 and the amorphous silicon thin film react. The metal silicon oxide (for example, Ni silicide) obtained by this is also located in the said interface surface. That is, it is located in the middle portion of the formed polysilicon thin film layer without being formed on the contact surface 16 between the formed polysilicon layer shown in FIG. 3 and the buffer layer on the lower surface. Therefore, the metal silicon oxide (for example, Ni silicide) effectively suppresses the leakage of the transistor without affecting the electrical properties of the low temperature polysilicon thin film transistor obtained in the next step.

According to the method for producing a low-temperature polysilicon thin film of this embodiment, by placing a catalyst layer such as nickel at an intermediate position of an amorphous silicon layer, a metal silicon oxide (for example, Ni silicide), which is formed later, is formed on an intermediate portion of the polysilicon layer. Position it. As a result, the transistor fabricated using the low temperature polysilicon thin film formed by the method has a good distribution characteristic of Vth and at the same time effectively suppresses the off-state current.

Second Embodiment

This embodiment provides a low temperature polysilicon thin film. The low temperature polysilicon thin film is obtained by the method for producing a low temperature polysilicon thin film described in the first embodiment.

Third Embodiment

This embodiment provides a low temperature polysilicon thin film transistor. The transistor is obtained from the low temperature polysilicon thin film described in the second embodiment.

Specifically, as shown in FIG. 9, the low-temperature polysilicon thin film transistor of the present embodiment includes a substrate 100, a semiconductor layer 110, a gate insulating layer 120, a gate 130, a dielectric layer 140, and a source. The electrode 151 and the drain electrode 152 are included. The substrate 100 may be a glass substrate, a plastic substrate, or the like. The semiconductor layer 110 is formed on the substrate 100 and formed of the low temperature polysilicon thin film described in the third embodiment, and includes a source region 111, a drain region 112, the source region 111 and The channel region 113 is disposed between the drain regions 112. The gate insulating layer 120 and the gate 130 are sequentially formed on the semiconductor layer 110, and the gate 130 corresponds to the position of the channel region 113. The dielectric layer 140 is formed on the gate 130 and the gate insulating layer 1200, and at the same time, the first via hole V1 and the second via hole V2 are formed in the dielectric layer 140. The drain electrode is connected to the source region 111 through a first via hole V1 and the drain electrode is connected to the drain region 112 through the second via hole V2. ) May be made of a metallic material.

The low temperature polysilicon thin film transistor is used as a switching element of a pixel of a TFT-LCD. As shown in FIG. 9, a pixel electrode 160 is formed in the dielectric layer 140, and the pixel electrode 160 is electrically connected to the drain electrode 152. As the pixel electrode 160, for example, a transparent conductive material of indium tin oxide (ITO) or indium zinc oxide (IZO) is employed. The low temperature polysilicon thin film transistor is also used, for example, as a switching element of a pixel of an organic light emitting diode (OLED), in which case the drain electrode is connected to the cathode of the pixel.

Since the low-temperature polysilicon thin film transistor of this embodiment places Ni silicide in the low-temperature polysilicon thin film employed in its fabrication at an intermediate position of the polysilicon layer, the channel region of the transistor has a good threshold voltage distribution and an off state. The current can be suppressed effectively.

<Fourth Embodiment>

Embodiments of the present invention also provide a display device. The display device includes an array substrate and a low temperature polysilicon thin film transistor formed on the array substrate. The device employs the low temperature polysilicon thin film transistor described in the third embodiment to form a switching element.

The display device of the present embodiment may be an OLED which is an organic light emitting diode, or a liquid crystal display (hereinafter, abbreviated as LCD). Since the electrical characteristics of the low-temperature polysilicon thin film transistors employed in the display device are stable, generation of off-state current can be effectively prevented, thereby improving display quality of the display device.

Finally, the above-described embodiments have been described only with reference to the technical solutions of the present invention, but are not limited thereto. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art can modify or change the technical solutions described in each of the above embodiments, and the partial technical features thereof can be interchanged equally. It is to be understood that the substance of the corresponding technical proposals does not depart from the spirit and scope of the technical solutions of each embodiment of the present invention.

11-substrate, 12-buffer layer, 13-nickel, 14-amorphous layer, 15-polysilicon crystal grain, 16-contact surface, 21-first amorphous silicon thin film layer, 22-catalyst particle, 23-second amorphous silicon thin film layer, 24 -Polysilicon crystal particles.

Claims (9)

As a method for producing a low temperature polysilicon thin film,
Preparing a substrate;
Forming a buffer layer on the substrate;
Forming a first amorphous silicon thin film on the buffer layer;
Forming particles of a catalyst on the first amorphous silicon thin film;
Forming a second amorphous silicon thin film to cover the first amorphous silicon thin film and the particles of the catalyst; And
Forming a low temperature polysilicon thin film by performing crystallization on the first amorphous silicon thin film and the second amorphous silicon thin film using the particles of the catalyst;
Method for producing a low temperature polysilicon thin film comprising a. The method of claim 1, wherein the buffer layer formed on the substrate is an oxide layer of silicon. The method of claim 1 or 2, wherein the particles of the catalyst comprises Ni, Cu, Al, Er or Cr. The method of claim 1 or 2, wherein the crystallization is a high-speed annealing heat treatment. The method of claim 3, wherein the crystallization is a high-speed annealing heat treatment. The low temperature polysilicon thin film obtained by the manufacturing method of the low temperature polysilicon thin film of Claim 1. Low temperature polysilicon thin film transistor,
Board;
A semiconductor layer comprising a low temperature polysilicon thin film according to claim 6 and formed on the substrate and including a source region, a drain region, and a channel region located between the source region and the drain region;
A gate corresponding to a position of the gate insulating layer and the channel region, which are sequentially formed on the semiconductor region;
A dielectric layer formed on the gate and the gate insulating layer and having a first via hole and a second via hole formed therein;
A source electrode connected to the source region via the first via hole; And
A drain electrode connected to the drain region via the second via hole;
Low temperature polysilicon thin film transistor comprising a. A display device comprising an array substrate, wherein the low temperature polysilicon thin film transistor according to claim 7 is formed on the array substrate. The display device of claim 8, wherein the display device is an active matrix organic light emitting diode or a liquid crystal display device.
KR1020110046992A 2010-05-18 2011-05-18 Low-temperature polysilicon thin film and method of manufacturing the same, transistor and display apparatus KR20110127091A (en)

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