KR20110120675A - A method of fabricating nano-scaled structure with non-uniform roughness - Google Patents

Abstract

PURPOSE: A method for manufacturing a nano-scale structure is provided to prevent the damage of a substrate while non-uniform roughness is generated on the nano-scale structure based on impurities introduced in a polycrystalline silicon structure forming process. CONSTITUTION: A method for manufacturing a nano-scale structure includes the following: An oxide layer(20) is formed on the surface of a substrate(10). A polycrystalline silicon structure(11) is formed on the upper side of the oxide layer by introducing impurities. Non-uniform roughness(13) is formed on the polycrystalline silicon structure through an etching process. The substrate is a silicon wafer. The etching process is based on XeF_2. The impurities are nitrogen gas.

Description

A method of manufacturing a nanoscale structure having non-uniform roughness using impurities {A METHOD OF FABRICATING NANO-SCALED STRUCTURE WITH NON-UNIFORM ROUGHNESS}

The present invention relates to a method of manufacturing a nanoscale structure having non-uniform roughness using impurities. In particular, the present invention relates to a method of implanting impurities in the process of forming a polycrystalline silicon structure, and generating non-uniform roughness using such impurities in an etching process.

Nano or micro structures require high processing technology as the electronic and electronic devices are micronized, and most of them are formed by growing and forming thin films on a single substrate and physically and chemically cutting them into predetermined shapes. You get

Nanoscale structures, ie nanostructures, can be applied to quantum well lasers, photoluminescence, electrometers, nanocrystal memories, and the like.

The method of fabricating nanostructures can be largely divided into two methods. One is to use the lithographic process and the other is to use the self-organized process.

In general, in forming a structure, a photolithography process, a plasma etching process, an imprint lithography process, and the like are applied as patterning, and most of them are used in the process of forming a structure of a regularized form.

However, in special cases, structures having disordered shapes in micro units or nano units may be required in addition to the normalized structure. In particular, in order to maximize the surface where the structure is in contact with the outside, structures with disordered roughness of nano units are needed. For example, it is known that the micro tip, which is the electron emission source in the field emission device, has a plurality of edges rather than a single electron emission edge. In addition, increasing the surface area may also function in increasing the capacity of the capacitor.

As a method of obtaining a structure having such disordered roughness, the general process used to date is not suitable, and a new manufacturing method is required.

In the related art, Korean Patent Publication 1) forms a microstructure on a substrate, 2) forms a carbon polymer layer, and 3) mixes an O2 gas having an etching property with respect to the carbon polymer layer and an gas having an etching property with respect to the microstructure. First etching the carbon polymer layer by plasma etching using one reaction gas, 4) forming a mask layer by the residue of the carbon polymer layer, and 5) performing a second etching with the gas. A method of producing nanosurface roughness while removing is disclosed.

However, in this case, the first etching is performed in the process of forming the mask layer by the residue of the carbon polymer layer, and then the second etching is performed again so that the etching process is performed twice. This big problem occurs. In addition, the surface roughness is determined during the secondary etching process by adjusting the thickness of the mask layer due to the residue of the carbon polymer layer formed through the primary etching, and controlling the thickness of the mask layer is very technically. It is difficult.

In particular, in order to control the thickness of the mask layer due to the residue of the carbon polymer layer, as shown in the related art, etching is performed by using an O2 plasma, and the damage and physical properties of the substrate due to heat deformation are caused by the heat generated. The problem of change arises. In particular, even greater problems arise when the substrate is glass.

In addition, the process of obtaining the desired non-uniform roughness has a problem that it is quite difficult to meet the process conditions. Therefore, there is a demand for a method for obtaining non-uniform roughness without controlling process conditions.

The present invention has been made to solve the above problems, firstly, to generate non-uniform roughness on the surface of the nano and micro structures.

Second, to reduce manufacturing costs by reducing the number of processes compared to processes that produce non-uniform roughness, and to provide a new process that improves product reliability by eliminating risks that could be applied to materials in the operating environment. to be.

Third, to provide a new process that can achieve this effect without controlling the process conditions for obtaining uneven roughness.

The present invention includes the following problem solving means to solve the above problems.

The present invention relates to a method of manufacturing a nanoscale structure having non-uniform roughness, and to forming an oxidation layer 20 on the surface of a substrate 10. In addition, a second step of forming the polycrystalline silicon structure 11 while adding an impurity on the upper side of the oxide layer 20, and through the etching (etching) process the non-uniform roughness 13 to the polycrystalline silicon structure (11) Forming a third step.

In another embodiment, a first step of forming an oxidation layer 20 on a surface of a substrate 10 and a polycrystalline silicon structure 11 of the oxide layer 20 are formed by using a PECVD process. And a third step of forming a non-uniform roughness 13 in the polycrystalline silicon structure 11 through an etching process.

Preferably, the substrate used in the first step is a silicon wafer.

In the third step, the etching process preferably uses XeF2.

The impurity added in the second step may be nitrogen gas, or nitrogen gas may be included in the process of depositing a polycrystalline silicon structure through a PECVD process.

The present invention has been made to solve the above problems, firstly, there is an effect of generating non-uniform roughness on the surface of the nano and micro structures.

Second, compared to the process of producing non-uniform roughness, the number of processes can be reduced to reduce manufacturing costs, and a new process for improving product reliability by eliminating risks that may be applied to materials in the operating environment can be achieved. There is.

Third, there is an effect of providing a new process that can achieve this effect without controlling the process conditions for obtaining uneven roughness.

1 is a process chart for manufacturing a nanostructure of the present invention.
2 is a flow chart for manufacturing a nanostructure of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention. However, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, FIG. 1 shows a general process diagram, and if the parts to be displayed are different even though the terms are the same, the reference numerals will be described in advance.

The terms to be described below are terms set in consideration of functions in the present invention, and may be changed according to a user's intention or custom such as an experimenter and a measurer, and the definitions should be made based on the contents throughout the present specification.

With reference to FIG. 1, a method of manufacturing a nanoscale structure having non-uniform roughness according to the present invention will be described.

Steps (1) to (2) are steps of forming an oxidation layer 20 on the surface of the substrate 10. A material used as a substrate is preferably a silicon wafer, but a glass substrate may be used, and the scope of the present invention is not limited to the material.

If the material of the substrate is a silicon wafer is used, the step of forming a wet oxidation layer 20 of 2000 kPa through silicon oxide should be involved on the surface. It is difficult to deposit polycrystalline silicon wafer structures on the surface of the silicon wafer itself. In addition, the oxide layer 20 may function as an insulating layer depending on the purpose of the structure.

Steps (2) to (3) are steps of forming the polycrystalline silicon structure 11 on the oxide layer 20.

The polycrystalline silicon structure 11 may be formed by depositing polycrystalline silicon on an oxide layer formed on a substrate. Properties such as electrical conductivity of polycrystalline silicon vary depending on the content of impurities.

Poly-Si is different from amorphous-Si. Amorphous is that atoms close to each other in the atomic arrangement have regularity in the number of atoms, bond distances, etc. In the dimensional range, it refers to a substance that does not have regularity. On the other hand, crystalline (Poly) material refers to a material having a long distance regularity as well as short distance.

Differences in the material properties of amorphous silicon and crystalline silicon also cause differences in the mobility of carriers that carry charges. For example, products made of amorphous silicon have a very low carrier mobility compared to crystalline silicon. For example, it is essential to use crystalline silicon in order to realize high resolution and large area in AM OLED, which is driven by applying current to the TFT.

However, the core of the present invention is related to intentionally containing impurities in the process of depositing a polycrystalline silicon structure. Therefore, a deposition process that intentionally contains impurities is recognized as a major technical element.

The method of depositing a polycrystalline silicon structure is mainly using a high temperature method, which is the LPCVD method as the crystallization method proceeds for several hours at a high temperature of 600 ℃ or more.

This LPCVD method is mainly used because of the advantage that impurities are not included in the deposition by the deposition temperature environment of 600 to 700 ℃.

The CVD method is classified into an APCVD method of laying a wafer down and an LPCVD method of depositing a thin film by standing a wafer. The LPCVD method is the same as the APCVD method, but since the wafer is deposited upright, more wafers can be made simultaneously and the process speed can be further increased. In general, in the LPCVD method, the reactant is placed on the wafer, and when the reactant approaches the wafer, SiCl4 is physically attached to the wafer by the adsorption action. In addition, a chemical reaction occurs on the surface (SiCl 4 + 2 H 2-> Si + 4 HCl), and then Si is deposited as the HCl falls off.

In addition, the PECVD method has the advantage that it can be deposited faster because it can proceed at a lower temperature than the above two methods, and when SiH4 is placed in the plasma, it collides with molecules in the plasma and decomposes into Si and H. to be.

However, the PECVD method is not used in the process of depositing polycrystalline silicon because the deposition temperature environment is about 300 ° C. and a large amount of impurities are included in the deposition process.

However, in the present invention, since the purpose is to contain impurities in the process of intentionally depositing polycrystalline silicon, the main technique is to use the PECVD method.

In particular, the impurity is preferably a gas of N2, which may further include artificially supplying.

In addition, the LPCVD method has a uniform process characteristics, but because the process proceeds for a long time there is a change due to the thermal expansion of the substrate to use a high-priced quartz substrate, there is a problem that the production cost increases and the productivity is low because of a long process. PECVD has the advantage of being shorter in time and capable of producing on low cost glass substrates.

Most of the problems encountered in the manufacture of crystalline silicon products are associated with the inability to raise the process temperature to high temperatures due to the heat resistance of fragile glass substrates. If the glass is used as a substrate, the heat-resistant glass developed so far has a strain point near 670 ° C, and rapid self-deformation occurs when a heat treatment is performed at a temperature of 640 ° C or higher. Further, above 450 ° C., the glass shrinks rapidly. Such deformation and shrinkage of the glass substrate is a cause of limiting the allowable temperature of the product manufacturing process using crystalline silicon to less than 600 ℃.

The appearance of (3) can be seen that the pores are formed inside the polycrystalline silicon structure (11). It is formed due to the presence of impurities. These pores cause nonuniformity in the time and distance of the reaction gas in contact with the polycrystalline silicon structure 11 in the etching process.

When the etching process is performed after the polycrystalline silicon structure 11 is deposited without containing impurities in a high temperature environment by LPCVD, pores are not present, etching is uniformly performed to obtain uniform roughness. In addition, even if a separate process is added, it is difficult to precisely control the etching process to obtain uneven roughness.

However, when the polycrystalline silicon structure 11 is deposited at a low temperature while adding impurities of nitrogen gas as in the present invention, etching is unevenly generated only on the surface regardless of the time and pressure exposed to the etching process. That is, even if the etching process is performed under extreme conditions, roughness occurs only on the surface, and there is an effect that the entire etching does not occur.

Steps (3) to (4) are steps of forming non-uniform roughness 13 in the polycrystalline silicon structure 11 through an etching process.

The etchant used for the etching of silicon, etc. in the micro-processing ranges from liquids such as Ethylene Diamine Pyrocatechol (EDP), KOH, and high energy plasma used with Cl2 or SF6. Xenon difluoride (hereinafter referred to as XeF2) is a dry gaseous silicon etchant with several advantages over the silicon etchant described above. XeF2 is a white solid at atmospheric pressure at room temperature, and has a characteristic of subliming at a pressure of 3.8 Torr or less at room temperature (25 ° C). The etching method using sublimated XeF2 has high selectivity for materials such as aluminum or photosensitive agent, and the silicon is etched in the gas phase, thereby minimizing the problem of adhesion of the structure to the floor. In addition, the isotropic etching characteristics and fast etching rate can be used to quickly etch the bottom of a large structure.

Therefore, in the etching process, it is preferable to use a fluorine compound of XeF2 as the dry etching process. This is a material having reactivity to the polycrystalline silicon structure 11. However, the oxide layer 20 does not show reactivity.

(4) is the shape of the nanoscale structure with uneven roughness obtained through the final step. The present invention may provide the effect of widening the surface area by manufacturing a nanostructure having a non-uniform roughness of the surface, or may provide a structure with different scales of roughness. That is, in (4), when the polycrystalline silicon structure 11 is roughness of a large scale with respect to the board | substrate 10, the surface of the polycrystalline silicon structure 11 is provided with the roughness of a small scale.

Nanoscale structures having such non-uniform roughness may be applied to the fabrication process of supercapacitors. The supercapacitor refers to an improvement in the specific storage capacity by 100 to 1000 times or more compared to the conventional one. The supercapacitor has a higher power density, a longer cycle life, a higher discharge rate, and various other advantages as compared with the secondary battery. The supercapacitor may be manufactured by increasing the surface area, and in the case of the nanoscale structure having the non-uniform roughness according to the present invention, the surface area may be increased by more than 10 times compared to the flat structure.

The capacitor consists of two flat electrode layers and a dielectric layer provided therebetween. In the process of generating the electrode layer, when the nanoscale structure having non-uniform roughness according to the present invention is produced, its surface area is greatly increased. Therefore, the capacity can be increased, and the accuracy can be improved.

In addition, nanoscale structures with non-uniform roughness according to the present invention can be used to create structures with double roughness. This makes it possible to adjust the contact angle of the liquid and solid (contact angle). That is, when liquid is present on the surface provided with the double roughness, the contact angle is greatly increased, thereby making it possible to create a surface having an increased hydrophobicity.

The present invention is not limited to the scope of the embodiments by the above embodiments, all having the technical spirit of the present invention can be seen to fall within the scope of the present invention, the present invention is the scope of the claims by the claims Note that is determined.

10: substrate, 11 polycrystalline silicon structure, 13 roughness, 20 oxide layer

Claims (7)

In the method of manufacturing a nano-scale structure having a non-uniform roughness using impurities,
A first step of forming an oxidation layer on the surface of the substrate,
A second step of forming a polycrystalline silicon structure while adding impurities to the upper side of the oxide layer;
A third step of forming non-uniform roughness in the polycrystalline silicon structure through an etching process,
A method of manufacturing a nanoscale structure having non-uniform roughness using impurities. In the method of manufacturing a nano-scale structure having a non-uniform roughness using impurities,
A first step of forming an oxidation layer on the surface of the substrate,
Forming a polycrystalline silicon structure of the oxide layer by using a PECVD process;
A third step of forming non-uniform roughness in the polycrystalline silicon structure through an etching process,
A method of manufacturing a nanoscale structure having non-uniform roughness using impurities. The method according to claim 1 or 2,
The substrate used in the first step is a silicon wafer,
A method of manufacturing a nanoscale structure having non-uniform roughness using impurities. The method according to claim 1 or 2,
In the third step, the etching process uses XeF2,
A method of manufacturing a nanoscale structure having non-uniform roughness using impurities. The method according to claim 1,
The impurity added in the second step is nitrogen gas,
A method of manufacturing a nanoscale structure having non-uniform roughness using impurities. The method according to claim 2,
Providing an impurity gas in the process of depositing a polycrystalline silicon structure through the PECVD process in the second step,
A method of manufacturing a nanoscale structure having non-uniform roughness using impurities. The method of claim 6,
The impurity gas is nitrogen gas,
A method of manufacturing a nanoscale structure having non-uniform roughness using impurities.

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