KR20110119977A

KR20110119977A - Method of programming a semiconductor memory device

Info

Publication number: KR20110119977A
Application number: KR1020100039435A
Authority: KR
Inventors: 강효영
Original assignee: 주식회사 하이닉스반도체
Priority date: 2010-04-28
Filing date: 2010-04-28
Publication date: 2011-11-03

Abstract

PURPOSE: A semiconductor memory device and a program thereof are provided to separate the channel of a cell in which data is not allowed to be programmed from the channel of a different cell by depleting the junction of a memory cell completely. CONSTITUTION: In a semiconductor memory device and a program thereof, a voltage applied to a 0-th word line is converted into a program voltage(Vpgm). A second pass voltage is applied to first and second word lines(WL1,WL2). A junction area adjacent to the first memory cell(C1) is changed into a depletion region. The channel of 0-th memory cell is isolated from a different channel.

Description

Method of programming a semiconductor memory device

The present invention relates to a program method of a semiconductor memory device.

There is an increasing demand for a semiconductor memory device that can be electrically programmed and erased and that can be stored without data being erased even when power is not supplied. In order to develop a large-capacity memory device capable of storing a large number of data, high integration technology of memory cells has been developed. In a semiconductor memory device, a plurality of memory cells are connected in series to form a string, and one memory cell array includes a plurality of cell strings.

In general, a flash memory cell includes a gate in which a tunnel insulating film, a floating gate, a dielectric film, and a control gate are stacked on a semiconductor substrate, and a junction region formed in a semiconductor substrate on both sides of the gate. It is programmed as it is injected and is erased as the injected electrons are discharged by FN tunneling.

1 shows a cross section of a cell string.

Referring to FIG. 1, a cell string of a semiconductor memory device includes a 0 th to 31 th memory cells MC0 to MC31 connected in series between a drain select transistor (DST) and a source select transistor (SST). Leads to.

The drain of the drain select transistor DST is connected to the bit line BL, and the source of the source select transistor SST is connected to the common source line SL.

A plurality of structures in which cell strings and bit lines are connected are connected in parallel to form a memory block. The memory block includes a drain selection transistor DST and a source in which the selection transistors DST and SST and the 0 th to 31 th memory cells MC0 to MC31 are arranged in a row and column matrix. The gate of the select transistor SST is connected to a drain select line DSL and a source select line SSL, respectively. In addition, the gates of the 0th to 31st memory cells MC0 to MC31 arranged in the same column are connected to the 0th to 31st word lines WL0 to WL31, respectively.

In the semiconductor memory device having the above-described structure, when programming, a high voltage between the channel region of the selected memory cell and the control gate is applied by applying a voltage of 0 V to the selected bit line and a program voltage Vpgm to the selected word line. Fowler-Nordheim due to the difference (hereinafter referred to as "FN") Tunneling (tunneling) by the injection of electrons in the channel region into the floating gate program.

However, the program voltage Vpgm may be applied not only to the selected memory cell but also to unselected memory cells arranged along the same word line so that the unselected memory cells connected to the same word line may be programmed. This phenomenon is called program disturb.

In order to prevent program disturb, when the bit line connected to the cell string including the unselected memory cells is precharged, the program voltage Vpgm is applied to the selected word line, and the pass voltage Vpass is applied to the unselected word line, Channels of memory cells included in the same cell string are boosted. As a result, the non-selected memory cells are not programmed.

To do this, the channel of the cell string must first be precharged. This channel precharge is achieved through the bit lines. If the voltage of the word line is increased while the cell string is floated, the channel is boosted and the voltage of the channel is changed.

In general, the closer to the source select transistor SST, the higher the probability that the channel precharge of the cell string is not properly performed. That is, when the zero word line WL0 is selected and the program voltage is applied, there is a case where the precharge is not sufficiently performed to the channel of the zero memory cell MC0 connected to the zero word line WL0. If the channel is not sufficiently precharged, channel boosting of the cell string to which the program is to be inhibited is not sufficient. If the channel of the cell string to which the program should be inhibited is not boosted, the channel voltage does not increase sufficiently. Thus, an FN tunneling program disturbance in which the memory cell to be programmed may be programmed may occur.

In a semiconductor memory device according to an embodiment of the present invention, when programming a memory cell adjacent to a source select transistor, a cell of another cell whose channel is to be prohibited by completely depleting the junction of the adjacent memory cell is completely depleted. The present invention provides a method of programming a semiconductor memory device in which channel boosting can be greatly separated from a channel of the channel.

Program method of a semiconductor memory device according to an embodiment of the present invention,

Providing a semiconductor memory device comprising a plurality of cell strings, each cell string including memory cells connected in series between a source select transistor and a drain select transistor; Selecting a memory cell adjacent to the source select transistor to apply a program voltage to a gate of the selected memory cell, apply a first pass voltage to the gates of at least two memory cells adjacent to the selected memory cell, and And performing a program by applying a second pass voltage to a gate, wherein the first pass voltage is set to change all of the junction regions adjacent to the at least two memory cells to a depletion region. do.

Performing a program test by entering a test mode to set the first pass voltage; Deriving a voltage at a point where all of the junction regions adjacent to the at least two memory cells are changed to a depletion region by using the result of the program test; And setting the derived voltage to the first pass voltage and terminating the test mode, wherein the set first pass voltage is used during a program operation in a normal mode.

The first pass voltage is lower than the second pass voltage.

In a method of programming a semiconductor memory device according to an embodiment of the present invention, when programming a memory cell adjacent to a source select transistor, the junction of adjacent memory cells is fully depleted so that the channel of the cell string is separated. By doing so, the channel containing the memory cell to which the program should be inhibited is effectively boosted.

1 shows a cross section of a cell string.
2A to 2C are cross-sectional views of a cell string for explaining self boosting of the cell string.
3 is a view for explaining a program method according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2A to 2C are cross-sectional views of a cell string for explaining self boosting of the cell string.

Referring to FIG. 2A, a cell string of a semiconductor memory device may include a 0 th to 31 th memory cell C0 to C31 between a drain select transistor (DST) and a source select transistor (SST). Are connected in series. In FIG. 2B and FIG. 2C, the same reference numerals as those of FIG. 2A are omitted.

The cell string includes a gate in which the tunnel insulating film 201, the floating gate 202, the dielectric film 203, and the control gate 204 are stacked on the semiconductor substrate sub, and a junction region 205 formed on the semiconductor substrate at both sides of the gate. )

A bit line is connected to the drain of the drain select transistor DST, and a source of the source select transistor SST is connected to the common source line SL in common.

If the cell string shown in FIG. 2B is a cell string to be program inhibited, the bit line BL is precharged. At this time, the drain select transistor DST is turned on.

The voltage precharged on the bit line is transferred to the channel 207 of the cell string. The pass voltage Vpass is applied to all word lines while the channel is precharged.

After the channel precharge, the voltage applied to the zeroth word line WL0 selected for the program is changed to the program voltage Vpgm. Accordingly, the channel 207 of the cell string is boosted.

As shown in FIG. 2C, when the program voltage Vpgm is input to the zeroth word line WL0, the channel is boosted to increase the voltage of the channel. Therefore, the voltage difference between the gate and the channel of the zero memory cell C0 to which the zero word line WL0 is connected may be reduced, thereby preventing the zero memory cell C0 from being programmed.

In general, when the program voltage is applied to the zeroth memory cell C0 closest to the source select transistor SST, the channel of the cell string in which the program is to be inhibited is not often boosted.

In the program method according to an exemplary embodiment of the present invention, when programming the zeroth memory cell C0 adjacent to the source select transistor SST, the first and second memory cells C1 and C2 adjacent to the zeroth memory cell C0 are programmed. ), So that the channel boosting to the 0th memory cell C0 is performed well by adjusting the pass voltage Vpass.

3 is a view for explaining a program method according to an embodiment of the present invention.

Since the cross section of the cell string shown in FIG. 3 is the same as that of FIG. 2A, reference numerals are omitted, and a description of the cell string is omitted since it has already been described with reference to FIG. 2A.

First, channel precharge of a cell string is performed as shown in FIG. 2B for a program. In this case, the first pass voltage Vpass1 is applied to all word lines, or the second pass voltage Vpass2 is applied to the first and second word lines WL1 and WL2, and the first pass voltage is applied to the remaining word lines. Apply Vpass1).

After the channel is precharged, the voltage applied to the zeroth word line WL0 is changed to the program voltage Vpgm as shown in FIG. 3, and the second pass voltages are applied to the first and second word lines WL1 and WL2. Apply Vpass2). If the second pass voltage Vpass2 is applied to the first and second word lines WL1 and WL2 when the channel is precharged, only the voltage applied to the zeroth word line WL0 is changed to the program voltage Vpgm. . The first pass voltage Vpass1 applied when the channel is precharged is continuously applied to the remaining word lines WL3 to WL31.

The size of the second pass voltage Vpass2 is set to such an extent that all of the junction regions 205 adjacent to the first memory cell C1 can be changed to the fully depletion regions 206. The conditions for changing all of the junction regions 205 adjacent to the first memory cell C1 to the depletion region 206 depend on various variables that appear during the processing of the semiconductor memory device.

Therefore, preferably, during the test process included in the manufacturing process of the semiconductor memory device, the second pass voltage Vpass2 in which the junction regions 205 are all duplicated for each wafer is determined, and thereafter, during the program operation of the semiconductor memory device. The second pass voltage Vpass2 is stored as option information to be applied to the second pass voltage Vpass2.

In the cell string of FIG. 3 according to an embodiment of the present invention, the first pass voltage Vpass1 is applied at 8V and the second pass voltage Vpass2 is applied at 6V. As a result, all of the junction regions 205 adjacent to the first memory cell C1 are changed to the depletion regions 206.

Accordingly, the channel toward the zeroth memory cell C0 is isolated from the other channel. Therefore, when the program voltage Vpgm is applied to the zeroth word line WL0, only the channel of the zeroth memory cell C0 is boosted.

That is, as shown in FIG. 3, when all of the junction regions 205 adjacent to the first memory cell C1 are changed to the depletion region 206, the channels of the cell strings are the first channel CH1 and the second channel. The effect of separating into channels CH2 occurs.

The length of the first channel CH1, which is the channel of the 0th memory cell C0, is shortened and boosted by the program voltage Vpgm applied to the 0th word line WL0, and the second channel CH2 is low. Boosted. Therefore, the zeroth memory cell C0 may be effectively program inhibited.

The above-described method is a method of separating channels similarly to the local boosting method, but the path voltage is applied to the first and second word lines WL1 and WL2 rather than using an isolation voltage for channel separation. By adjusting, all of the junction regions 205 adjacent to the first memory cell C1 are changed to the depletion regions 206 to enable local boosting.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

201: tunnel insulating film 202: floating gate
203 dielectric film 204 control gate
205: junction region 206: depletion region

Claims

Providing a semiconductor memory device comprising a plurality of cell strings, each cell string including memory cells connected in series between a source select transistor and a drain select transistor; And
Selecting a memory cell adjacent to the source selection transistor to apply a program voltage to a gate of the selected memory cell, a first pass voltage to the gate of at least two memory cells adjacent to the selected memory cell, and a gate of the remaining memory cells Performing a program by applying a second pass voltage to the second circuit;
And wherein the first pass voltage is set to change all of the junction regions adjacent to the at least two memory cells into a depletion region.

The method of claim 1,
In order to set the first pass voltage,
Entering a test mode to perform a program test;
Deriving a voltage at a point where all of the junction regions adjacent to the at least two memory cells are changed to a depletion region by using the result of the program test; And
Setting the derived voltage to the first pass voltage and ending the test mode;
And using the set first pass voltage during a program operation in a normal mode.

The method of claim 1,
And the first pass voltage is lower than the second pass voltage.